<Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE PS21765 / PS21767 / PS21767-V Table of contents CHAPTER 1 Mini DIPIPM Ver.4 INTRODUCTION ............................................................................................ 2 1.1 Target Applications ......................................................................................................................................................2 1.2 Product Line-up ...........................................................................................................................................................2 1.3 Functions and Features ...............................................................................................................................................2 CHAPTER 2 SPECIFICATIONS AND CHARACTERISTICS ............................................................................. 4 2.1 Mini DIPIPM Ver.4 Specifications ................................................................................................................................4 2.1.1 Maximum Ratings ......................................................................................................................................................................................................... 4 2.1.2 Thermal Resistance...................................................................................................................................................................................................... 5 2.1.3 Electric Characteristics (Power Part) ........................................................................................................................................................................... 5 2.1.4 Electric Characteristics (Control Part) .......................................................................................................................................................................... 6 2.1.5 Recommended Operating Conditions .......................................................................................................................................................................... 7 2.1.6 Mechanical Characteristics and Ratings ...................................................................................................................................................................... 8 2.2 Protective Functions and Operating Sequence ...........................................................................................................8 2.2.1 Short Circuit Protection ................................................................................................................................................................................................ 8 2.2.2 Control Supply UV Protection ...................................................................................................................................................................................... 9 2.3 Package Outlines ...................................................................................................................................................... 11 2.3.1 Package Outline Drawing ............................................................................................................................................................................................11 2.3.2 Laser Marking ............................................................................................................................................................................................................. 12 2.3.3 Terminal Description ................................................................................................................................................................................................... 13 2.4 Mounting Method .......................................................................................................................................................15 2.4.1 Electric Spacing .......................................................................................................................................................................................................... 15 2.4.2 Mounting Method and Precautions ............................................................................................................................................................................ 15 2.4.3 Soldering Conditions .................................................................................................................................................................................................. 16 CHAPTER 3 SYSTEM APPLICATION HIGHLIGHT ........................................................................................ 17 3.1 Application Guidance .................................................................................................................................................17 3.1.1 System connection ..................................................................................................................................................................................................... 17 3.1.2 Interface Circuit (Direct Coupling Interface. One shunt) ............................................................................................................................................ 18 3.1.3 Interface Circuit (Opto-coupler Isolated Interface) ..................................................................................................................................................... 19 3.1.4 External SC Protection Circuit with Using Three Shunt Resistors ............................................................................................................................. 20 3.1.5 Circuits of Signal Input terminals and Fo Terminal ..................................................................................................................................................... 20 3.1.6 Snubber Circuit ........................................................................................................................................................................................................... 23 3.1.7 Recommended Wiring method around Shunt Resistor ............................................................................................................................................. 23 3.1.8 Precaution for wiring on PCB ..................................................................................................................................................................................... 25 3.1.9 Parallel operation of DIPIPM ...................................................................................................................................................................................... 26 3.1.10 SOA of Mini DIPIPM Ver.4 ........................................................................................................................................................................................ 26 3.1.11 SCSOA ..................................................................................................................................................................................................................... 27 3.1.12 Power Life Cycles ..................................................................................................................................................................................................... 28 3.2 Power Loss and Thermal Dissipation Calculation......................................................................................................29 3.2.1 Power Loss Calculation .............................................................................................................................................................................................. 29 3.2.2 Temperature Rise Considerations and Calculation Example .................................................................................................................................... 31 3.3 Noise Withstand Capability ........................................................................................................................................32 3.3.1 Evaluation Circuit........................................................................................................................................................................................................ 32 3.3.2 Countermeasures and Precautions............................................................................................................................................................................ 32 3.3.3 Static Electricity Withstand Capability ........................................................................................................................................................................ 33 CHAPTER 4 KEY PARAMETERS SELECTING GUIDANCE .......................................................................... 34 4.1 Determination of Shunt Resistance ...........................................................................................................................34 4.2 Bootstrap Circuit Operation .......................................................................................................................................35 4.2.1 Bootstrap Circuit Operation ........................................................................................................................................................................................ 35 4.2.2 Bootstrap Supply Circuit Current at Switching State .................................................................................................................................................. 36 4.2.3 Note for designing the bootstrap circuit...................................................................................................................................................................... 36 CHAPTER 5 Interface Demo Board .................................................................................................................... 38 5.1 Mini DIPIPM Ver.4 Interface Demo Board .................................................................................................................38 5.2 Pattern Wiring ............................................................................................................................................................39 5.3 Circuit Schematic and Parts List ................................................................................................................................40 CHAPTER 6 PACKAGE HANDLING ................................................................................................................ 42 6.1 Packaging Specification.............................................................................................................................................42 6.2 Handling Precautions ................................................................................................................................................43 Publication Date : November 2012 1 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE CHAPTER 1 Mini DIPIPM Ver.4 INTRODUCTION 1.1 Target Applications Motor drives for household equipment such as air conditioners, hot water system and low power industrial equipments. 1.2 Product Line-up Table 1-1. Mini DIPIPM Ver.4 Line-up Type Name IGBT Rating Motor Rating 1) Isolation Voltage V iso = 2500Vrms PS21765 20A/600V 1.5kW/220VAC (Sine 60Hz, 1min PS21767/-V 2) 30A/600V 2.2kW/220VAC All shorted pins-heat sink) Note 1: The motor ratings are simulation results under following conditions: VAC=220V, VD=VDB=15V, Tc=100°C, Tj=125°C, fPWM=5kHz, P.F=0.8, motor efficiency=0.75, current ripple ratio=1.05, motor over load 150% 1min. Note 2: PS21767-V is faster switching type. 1.3 Functions and Features Mini DIPIPM Ver.4 is an ultra-small compact intelligent power module with transfer mold package favorable for larger mass production. Power chips, drive and protection circuits are integrated in the module, which makes it easy for AC100-200V class low power motor inverter control. Fig.1-1, Fig.1-2 and Fig.1-3 show the photograph, internal cross-section structure and the circuit block diagram respectively. One of the most important features of Mini DIPIPM Ver.4 is that realized higher thermal dissipation by built-in thermal structure with high thermal conductive insulated sheet, due to which, the chip shrinking becomes possible and therefore achieved super small package with lower temperature rise than previous DIPIPM. Cu frame Al wire Epoxy mold resin Fig.1-1 Package photograph FWDi IGBT IC Insulated thermal Au wire radiating sheet (Cu foil + insulated resin) Fig.1-2 Internal cross-section structure Publication Date : November 2012 2 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE DIPIPM VUFB VUFS VP1 UP P HVIC1 VCC VB IN HO COM VS VVFB VVFS VP1 VP VP Di1 U HVIC2 VCC VB IN HO COM VS VWFB VWFS VP1 IGBT1 IGBT2 Di2 V HVIC3 VCC VB IN HO COM VS IGBT3 Di3 W IGBT4 LVIC Di4 UOUT VN1 VCC NU IGBT5 Fo Di5 Fo VOUT UN UN VN VN WN WN NV IGBT6 Di6 W OUT NW VNO VNC GND VNO CIN CIN CFO CFO Fig.1-3 Internal circuit schematic Features: ● For P-side IGBTs: -Drive circuit; -High voltage level shift circuit; -Control supply under voltage (UV) lockout circuit (without fault signal output). ● For N-side IGBTs: -Drive circuit; -Short circuit (SC) protection circuit (by using external shunt resistor) -Control supply under voltage (UV) lockout circuit (with fault signal output) ● Fault Signal Output -Corresponding to N-side IGBT SC protection, N-side UV protection and OT. ● IGBT Drive Supply -Single DC15V power supply. ● Control Input Interface -Schmitt-triggered 3V,5V input compatible, high active logic. ● UL recognized -UL1557 File E80276 Publication Date : November 2012 3 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE CHAPTER 2 SPECIFICATIONS AND CHARACTERISTICS 2.1 Mini DIPIPM Ver.4 Specifications The Mini DIPIPM Ver.4 specifications are described below by using PS21767(30A/600V) as an example. Please refer to respective datasheet for the detailed description of other types. 2.1.1 Maximum Ratings The maximum ratings of PS21767 are shown in Table 2-1. Table 2-1 Maximum Ratings of PS21767 Inverter Part: Item Supply voltage Supply voltage (surge) Collector-emitter voltage Condition Applied between P-NU,NV,NW Applied between P-NU,NV,NW Symbol VCC VCC(surge) VCES Rating Unit 450 500 V V 600 V Each IGBT collector current ±IC Tc=25°C 30 A Each IGBT collector current (peak) ±ICP Tc=25°C, less than 1ms 60 A Collector dissipation PC Tc=25°C, per 1 chip 90.9 W Junction temperature Tj -20~+150 °C (1) (2) (3) (4) (5) Control (Protection) Part Item Control supply voltage Symbol VD Control supply voltage VDB Input voltage VIN Fault output supply voltage Fault output current Current sensing input voltage VFO IFO VSC Condition Applied between VP1-VNC,VN1-VNC Applied between VUFB-VUFS, VVFB-VVFS ,VWFB-VWFS Applied between UP,VP,W P-VNC, UN,VN,W N-VNC Applied between Fo-VNC Sink current at Fo terminal Applied between CIN-VNC Rating 20 Unit V 20 V -0.5~VD+0.5 V -0.5~VD+0.5 1 -0.5~VD+0.5 V mA V Rating Unit 400 V -20~+100 -40~+125 °C °C 2500 Vrms Total System Item Condition VD=13.5~16.5V, Inverter part Tj=125°C, non-repetitive less than 2µs (Note2) Symbol Supply voltage self protection limit (short circuit protection capability) VCC(PROT) Module case operation temperature Storage temperature Tc Tstg Isolation voltage Viso 60Hz, Sinusoidal, AC 1 minutes, All connected pins to heat-sink plate (6) (Note1) Tc measurement position Control terminals DIPIPM 18mm 18mm Groove (7) IGBT chip position FWDi chip position Tc point Heat sink side Power terminals Item explanation: (1) Vcc The maximum voltage can be biased between P-N in the steady state. A voltage suppressing circuit such as a brake circuit is necessary if P-N voltage exceeds this value. (2) Vcc(surge) The maximum P-N surge voltage is generated in switching state. A snubber circuit is necessary if P-N voltage exceeds Vcc(surge). (3) VCES The maximum sustained collector-emitter voltage of built-in IGBT and FWDi. (4) +/-IC The allowable DC current continuously can flow at Tc=25°C. (5) Tj The maximum junction temperature rating is 150°C.But for safe operation, it is recommended to limit the average junction temperature up to 125°C. Repetive temperature variation ΔTj affects the life time of power cycle. (6) Vcc(prot) The maximum supply voltage for IGBT when it can turn off safely in case of an SC fault. The power chip might be damaged if supply voltage exceeds this rating. (7) Tc position Due to the control schemes such different control between P and N-side, there is the possibility that highest Tc point is different from above point. In such cases, it is necessary to change the measuring point to that under the highest power chip. Publication Date : November 2012 4 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE 2.1.2 Thermal Resistance Table 2-2 shows the thermal resistance of PS21767. Table 2-2 Thermal resistance of PS21767 Thermal Resistance : Item Junction to case thermal resistance Symbol Condition Rth(j-c)Q Inverter IGBT part (per 1/6 module) (Note 2) Rth(j-c)F Inverter FWD part (per 1/6 module) Min. Typ. Max. - - 1.1 2.8 Unit K/W (Note 2)Grease with good thermal conductivity and long-term quality should be applied evenly with +100μm~+200μm on the contacting surface of DIPIPM and heat-sink. The contacting thermal resistance between DIPIPM case and heat sink (Rth(c-f)) is determined by the thickness and the thermal conductivity of the applied grease. For reference, Rth(c-f) (per 1/6 module) is about 0.3K/W when the grease thickness is 20μm and the thermal conductivity is 1.0W/m·k The above data shows the thermal resistance between chip junction and case at steady state. The thermal resistance goes into saturation in about 10 seconds. The thermal resistance under 10s is called as transient thermal impedance which is shown in Fig.2-1. Zth(j-c)* is the normalized value of the transient thermal impedance. (Zth(j-c)*= Zth(j-c) / Rth(j-c)max) For example, the IGBT transient thermal impedance of PS21767 in 0.2s is 1.1×0.8=0.88K/W. The transient thermal impedance isn’t used for constantly current, but for short period current (ms order). (e.g. In the cases at motor starting, at motor lock・・・) Thermal impedance Zth(j-c)* 1.0 FWD IGBT 0.1 0.01 0.1 Time(sec.) 1 10 Fig.2-1 Typical transient thermal impedance 2.1.3 Electric Characteristics (Power Part) Table 2-3 shows the typical static characteristics and switching characteristics of PS21767. Table 2-3 Static characteristics and switching characteristics of PS21767 Inverter Part Item Collector-emitter saturation voltage FWDi forward voltage Switching times Collector-emitter cut-off current Symbol VCE(sat) VEC ton trr tc(on) toff tc(off) ICES Condition VD=VDB=15V Tj=25°C IC=30A, VIN=5V Tj=125°C -IC=30A, VIN=0V VCC=300V, VD=VDB=15V IC=30A Tj=125°C Inductive load VIN=0-5V VCE=VCES Tj=25°C Tj=125°C Min. 0.70 - Typ. 1.60 1.70 1.50 1.30 0.30 0.50 1.50 0.40 - Max. 2.10 2.20 2.00 1.90 0.80 2.10 0.60 1 10 Switching time definition and performance test method are shown in Fig.2-2 and 2-3. Publication Date : November 2012 5 Unit V V µs mA <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE trr VCE Irr VB VP1 V DB P- Side IGBT Ic L O UT IN VCIN(P) 90% 90% VS COM A P-Side Input Signal VCC B 10% 10% 10% 10% VN1 VD tc(on) tc(off) VCIN(N) VCIN td(on) tr ( ton=td(on)+tr ) IN VNC td(off) tf ( toff=td(off)+tf ) OUT VNO CIN L N- Side IGBT N-Side Input Signal Fig.2-2 Switching time definition Fig.2-3 Evaluation circuit (inductive load) Short A for N-side IGBT, and short B for P-side IGBT evaluation t:200ns/div Turn on t:200ns/div Turn off Ic:10A/div Ic:10A/div VCE:100V/div VCE:100V/div Conditions : VCC=300V, VD=VDB=15V, Tj=125°C, Ic=30A, Inductive load half-bridge circuit Fig.2-4 Typical switching waveform (PS21767) 2.1.4 Electric Characteristics (Control Part) Table 2-4 Control (Protection) characteristics of PS21767 Control (Protection) Part: Item Circuit current Fo output voltage Short circuit trip level Input current Supply circuit undervoltage protection Symbol ID VFOH VFOL VSC(ref) IIN UVDBt UVDBr UVDt UVDr tFO Vth(on) Vth(off) Condition VD=VDB=15V Total of VP1-VNC,VN1-VNC VIN=5V VUFB-U, VVFB-V, VWFB-W VD=VDB=15V Total of VP1-VNC,VN1-VNC VIN=0V VUFB-VUFS,VVFB-VVFS,VWFB-VWFS VSC=0V,Fo terminal pull-up to 5V by 10kΩ VSC=1V, IFO=1mA VD=15V (Note3) VIN=5V Trip level Tj≤125°C Reset level Trip level Reset level CFO=22nF (Note4) Applied between UP,VP,W P-VNC, UN,VN,W N-VNC Min. 4.9 0.43 1.0 10.0 10.5 10.3 10.8 1.0 0.8 Typ. 0.48 1.5 1.8 2.3 1.4 Max. 7.00 0.55 7.00 0.55 0.95 0.53 2.0 12.0 12.5 12.5 13.0 2.6 - Unit mA V V mA V Fault output pulse width ms ON threshold voltage OFF threshold voltage V ON/OFF threshold Vth(hys) 0.5 0.9 hysteresis voltage (Note 3) Short circuit protection is functioning only at the lower-arms. Please select the external shunt resistance such that the SC trip-level is less than 2.0 times of the current rating. (Note 4) Fault signal is output when the low-arms short circuit or control supply under-voltage protective functions works. The fault output pulse-width tFO depends on the capacitance of CFO according to the following approximate equation : -6 CFO= 12.2 × 10 × tFO [F] Publication Date : November 2012 6 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE 2.1.5 Recommended Operating Conditions The recommended operating conditions of PS21767 are given in Table 2-5. Although these conditions are the recommended but not the necessary ones, it is highly recommended to operate the modules within these conditions so as to ensure DIPIPM safe operation. Table 2-5 Recommended operating conditions of PS21767 Recommended Operation Conditions Item Symbol Supply voltage Control supply voltage VCC VD Control supply voltage VDB Control supply variation Arm-shoot-through blocking time PWM input frequency Output r.m.s. current ∆VD, ∆VDB tdead fPWM IO Recommended Max. Min. Typ. 0 300 400 15.0 13.5 16.5 Applied between P-NU,NV,NW Applied between VP1-VNC,VN1-VNC Applied between VUFB-VUFS,VVFB-VVFS,VWFB-VWFS For each input signal, Tc≤100°C Tc≤100°C, Tj≤125°C VCC=300V, VD=VDB=15V, P.F=0.8, fPWM=5kHz sinusoidal PWM, Tj≤125°C, Tc≤100°C (Note 7) fPWM=15kHz PWIN(on) (Note 8) PWIN(off) Below rated current Between rated current and 1.7 times of rated current Between 1.7 times and 2.0 times of rated current Minimum input pulse width VNC VNC voltage variation Condition 200V≤VCC≤350V, 13.5V≤VD≤16.5V, 13.0V≤VDB≤18.5V, -20°C≤Tc≤100°C, N-line wiring inductance less than 10nH (Note 9) Between VNC-NU,NV,NW (including surge) Unit V V 13.0 15.0 18.5 V -1 2.0 - - 1 20 V/μs μs kHz - - 21 - - 16 0.3 - - 1.5 - - 3.0 - - 3.6 - - -5.0 - 5.0 Arms μs V Tj Junction temperature -20 125 °C (Note 7) The allowable r.m.s. current value depends on the actual application conditons. (Note 8) Input signal with ON pulse width less than PWIN(on) might make no response. (Note 9) IPM might make delayed response (less than about 2μs) or no response for the input signal with off pulse width less than PWIN(off). Please refer below about delayed responce. About Delayed Response Against Shorter Input Off Signal Than PWIN(off) (P side only) P Side Control Input Internal IGBT Gate Output Current Ic t2 t1 Real line…off pulse width>PWIN(off); turn on time t1 Broken line…off pulse width<PWIN(off); turn on time t2 About control supply variation If high frequency noise superimposed to the control supply line, IC malfunction might happen and cause DIPIPM erroneous operation. To avoid such problem happens, line ripple voltage should meet the following specifications: dV/dt ≤ +/-1V/μs, Vripple≤2Vp-p Publication Date : November 2012 7 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE 2.1.6 Mechanical Characteristics and Ratings The mechanical characteristics and ratings are shown in Table 2-6 Please refer to Section 2.4 for the detailed mounting instruction of Mini DIPIPM Ver.4. Table 2-6 Mechanical characteristics and ratings of PS21767 Mechanical Characteristics and Ratings Item Mounting torque Condition Mounting screw: M3 (Note 5) Recommended: 0.78N·m Weight Heat-sink flatness (Note 5) Plain washers (ISO 7089~7094) are recommended. (Note 6) Flatness measurement position: (Note 6) Min. 0.59 Typ. − Max. 0.98 Unit N·m − 21 −50 − − 100 µm g 12.78mm Measurement position + - 4.65mm 13.5mm 23mm Heat sink side + Heat sink side 2.2 Protective Functions and Operating Sequence Mini DIPIPM Ver.4 has the protection function that are SC protection and UV protection. Their operating principle and sequence are described below. 2.2.1 Short Circuit Protection Mini DIPIPM Ver.4 uses external shunt resistor for the current detection as shown in Fig.2-5. The protection circuit inside the IC captures the excessive large current by comparing the CIN voltage feedback from the shunt with the referenced SC trip voltage, and perform protection automatically. The threshold voltage level of the SC protection is 0.48V(typ.). In case of SC protection happens, all the gates of N-side three phase IGBTs will be interrupted together with a fault signal output. To prevent DIPIPM erroneous protection due to the switching noise at normal operation and/or recovery current, it is necessary to set an RC filter(time constant: 1.5μ ~ 2μs) to the CIN terminal input (Fig.2-5, 2-6). Also, please make the pattern wiring around the shunt resistor as short as possible. DIPIPM Drive Circuit Collect current Ic P P-side IGBTs U V W N-side IGBTs SC protective level SC protection external parts Shunt resistor N1 R C NU NV NW Collector current Drive Circuit 0 CIN VNC 2 Input pulse width tw (μs) SC Protection Fig.2-5 SC protecting circuit Fig.2-6 Filter time constant setting Publication Date : November 2012 8 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE SC protection (N-side only with the external shunt resistor and RC filter) a1. Normal operation: IGBT ON and carrying current. a2. Short circuit detection (SC trigger). a3. IGBT gate hard interruption. a4. IGBT turns OFF. a5. Fo timer operation starts. The pulse width of the Fo signal is set by the external capacitor CFO. a6. Input = “L”. IGBT OFF. a7. Input = “H”. But IGBT is still OFF state during outputting Fo. a8. IGBT turns ON when L→H signal is input after Fo is reset. N-side control input a6 Protection circuit state a7 SET Internal IGBT gate RESET a3 a2 SC a8 a1 a4 Output current Ic SC reference voltage Sense voltage of the shunt resistor RC circuit time constant delay Fault output Fo a5 Fig.2-7 SC protection timing chart 2.2.2 Control Supply UV Protection The UV protection is designed to prevent unexpected operating behavior as described in Table 2-7. Both P-side and N-side have UV protecting function. However, fault signal (Fo) output only corresponds to N-side UV protection. Fo output continuously during UV state. In addition, there is a noise filter (typ. 10μs) integrated in the UV protection circuit to prevent instantaneous UV erroneous trip. Therefore, the control signals are still transferred in the initial 10μs after UV happened. Table 2-7 DIPIPM operating behavior versus control supply voltage Control supply voltage Operating behavior Equivalent to zero power supply. UV function is inactive, no Fo output. Normally IGBT does not work. But, external noise may cause DIPIPM 0-4.0V (P, N) malfunction (turns ON), so DC-link voltage need to turn on after control supply turning on. UV function becomes active and output Fo (N-side only). 4.0-UVDt (N), UVDBt (P) Even if control signals are applied, IGBT does not work IGBT can work. However, conducting loss and switching loss will UVDt (N)-13.5V UVDBt (P)-13.0V increase, and result extra temperature rise at this state,. 13.5-16.5V (N), 13.0-18.5V (P) Recommended conditions. IGBT works. However, switching speed becomes fast and saturation 16.5-20.0V (N),18.5-20.0V (P) current becomes large at this state, increasing SC broken risk. 20.0V- (P, N) The control circuit will be destroyed. Note: UV fault signals are asserted only for VD supply. Ripple Voltage Limitation of Control Supply If high frequency noise superimposed to the control supply line, IC malfunction might happen and cause DIPIPM erroneous operation. To avoid such problem, line ripple voltage should meet the following specifications: dV/dt ≤ +/-1V/μs, Vripple≤2Vp-p Publication Date : November 2012 9 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE N-side UV Protection Sequence b1. Control supply voltage V D rises: After VD level reaches under voltage reset level (UVDr), the circuits start to operate when next input is applied. b2. Normal operation: IGBT turn on and carry current. b3. VD level falls to under voltage trip level. (UVDt). b4. All N-side IGBTs turn OFF in spite of control input condition. b5. Fo is output for the period determined by the capacitance CFO but continuously during UV period. b6. VD level rises to UVDr. b7. Normal operation: IGBT turn on and carry current. Control input Protection circuit state RESET SET RESET b1 Control supply voltage VD UVDr b6 UVDt b3 b4 b2 b7 Output current Ic b5 Fault output Fo Fig.2-8 Timing chart of N-side UV protection P-side UV Protection Sequence c1. Control supply voltage rises: After the voltage level reaches UVDBr, the circuits start to operate. c2. Normal operation: IGBT turns on and carry current. c3. VDB level falls to under voltage trip level (UVDBt). c4. P-side IGBT turns OFF in spite of control input signal level, but there is no Fo signal output. c5. VDB level rises to UVDBr. c6. Normal operation: IGBT turns on and carries current. Control input Protection circuit state RESET Control supply voltage VDB UVDBr c1 SET UVDBt RESET c5 c3 c4 c2 c6 Output current Ic Fault output Fo High-level (no fault output) Fig.2-9 Timing Chart of P-side UV protection Publication Date : November 2012 10 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE 2.3 Package Outlines 2.3.1 Package Outline Drawing Fig.2-10 Package outline drawing Publication Date : November 2012 11 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE 2.3.2 Laser Marking The laser marking specification of Mini DIPIPM Ver.4 is described in Fig.2-11. Mitsubishi Corporation mark, Type name, Lot number, and QR code mark are marked in the upper side of module. *1) `JAPAN` marking is not printed for products of . *2) QR Code is registered trademark of DENSO WAVE INCORPORATED in JAPAN and other countries. Fig.2-11 Laser marking view The Lot number indicates production year, month, and running number. The detailed is described as below. (1) Products of JAPAN (Example) 1 2 A A1 Running number Product month (however O: October, N: November, D: December) Last figure of Product year (e.g. '1' in the case of 2011) (2) Products of CHINA (Example) H 1 2 A A1 Running number Product month (however O: October, N: November, D: December) Last figure of Product year (e.g. '1' in the case of 2011) Factory Identification Publication Date : November 2012 12 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE 2.3.3 Terminal Description Table 2-8 Terminal description Terminal Terminal Description No. Name 1 VUFS U-phase P-side drive supply GND terminal 2 UPG Dummy-pin 3 VUFB U-phase P-side drive supply positive terminal 4 VP1 U-phase P-side control supply positive terminal 5 COM Dummy-pin 6 UP U-phase P-side control input terminal 7 VVFS V-phase P-side drive supply GND terminal 8 VPG Dummy-pin 9 VVFB V-phase P-side drive supply positive terminal 10 VP1 V-phase P-side control supply positive terminal 11 COM Dummy-pin 12 VP V-phase P-side control input terminal 13 VWFS W-phase P-side drive supply GND terminal 14 WPG Dummy-pin 15 VWFB W-phase P-side drive supply positive terminal 16 VP1 W-phase P-side control supply positive terminal 17 COM Dummy-pin 18 WP W-phase P-side control input terminal 19 UNG Dummy-pin 20 VNO N-side IGBT gate signal referenced GND terminal 21 UN U-phase N-side control input terminal 22 VN V-phase N-side control input terminal 23 WN W-phase N-side control input terminal 24 FO Fault signal output terminal 25 CFO Fault pulse output width setting terminal 26 CIN SC current trip voltage detecting terminal 27 VNC N-side control supply GND terminal 28 VN1 N-side control supply positive terminal 29 WNG Dummy-pin 30 VNG Dummy-pin 31 NW WN-phase IGBT emitter 32 NV VN-phase IGBT emitter 33 NU UN-phase IGBT emitter 34 W W-phase output terminal 35 V V-phase output terminal 36 U U-phase output terminal 37 P Inverter DC-link positive terminal 38 NC No connection Note) Dummy pin has some potential like gate voltage. Don’t connect all dummy-pins to any other terminals or PCB pattern. Publication Date : November 2012 13 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE Table 2-9 Detailed description of input and output terminals Item Symbol Description • Drive supply terminals for P-side IGBTs. • By virtue of applying the bootstrap circuit scheme, individual isolated power supplies are not needed for the DIPIPM P-side IGBT drive. Each bootstrap capacitor is charged by the N-side VD supply during ON-state of the P-side drive supply positive terminal corresponding N-side IGBT in the loop. VUFB- VUFS • Abnormal operation might happen if the VD supply is not aptly stabilized or VVFB- VVFS has insufficient current capability. In order to prevent malfunction caused by VWFB- VWFS P-side drive supply such unstability as well as noise and ripple in supply voltage, a bypass GND terminal capacitor with favorable frequency and temperature characteristics should be mounted very closely to each pair of these terminals. • Inserting a Zener diode (24V/1W) between each pair of control supply terminals is helpful to prevent control IC from surge destruction. • Control supply terminals for the built-in HVIC and LVIC. • In order to prevent malfunction caused by noise and ripple in the supply P-side control voltage, a bypass capacitor with good frequency characteristics should be supply terminal mounted very closely to these terminals. VP1 • Design the supply carefully so that the voltage ripple caused by operation VN1 N-side control keep within the specification. (dV/dt ≤ +/-1V/μs, Vripple≤2Vp-p) supply terminal • It is recommended to insert a Zener diode (24V/1W) between each pair of control supply terminals to prevent surge destruction. • Control ground terminal for the built-in HVIC and LVIC. N-side control VNC • Ensure that line current of the power circuit does not flow through this GND terminal terminal in order to avoid noise influences. VNO terminal VNO • The terminal for N-side IGBT gate signal reference. • Control signal input terminals. • Voltage input type. These terminals are internally connected to Schmitt trigger circuit and pulled down by min 2.5kΩ resistor internally UP,VP,W P Control input • The wiring of each input should be as short as possible to protect the terminal DIPIPM from noise interference. UN,VN,W N • Use RC coupling in case of signal oscillation. Pay attention to threshold voltage of input terminal, because input circuit has pull down resistor. Short-circuit trip • For short circuit protection, input the potential of external shuint resistor to voltage detecting CIN CIN terminal through RC filter (for the noise immunity). • The time constant of RC filter is recommended to be up to 2μs. terminal • Fault signal output terminal. Fault signal output • Fo signal line should be pulled up to the logic supply. (In the case pulling up FO to 5V supply, over 5kΩ resistor is needed for limitting the Fo sink current IFo terminal up to 1mA. Normally 10kΩ is recommended.) • The terminal is for setting the fault pulse output width. Fault pulse output • An external capacitor should be connected between this terminal and VNC. width setting CFO • When 22nF is connected, then the Fo pulse width becomes 1.8ms. terminal CFO (F) = 12.2 × 10-6 × tFO (Required Fo pulse width) • DC-link positive power supply terminal. • Internally connected to the collectors of all P-side IGBTs. Inverter DC-link • To suppress surge voltage caused by DC-link wiring or PCB pattern P inductance, smoothing capacitor should be inserted very closely to the P positive terminal and N terminal. It is also effective to add small film capacitor with good frequency characteristics. • Open emitter terminal of each N-side IGBT Inverter DC-link NU,NV,NW • Usually, these terminals are connected to the power GND through individual negative terminal shunt resistor. • Inverter output terminals for connection to inverter load (e.g. AC motor). Inverter power U, V, W • Each terminal is internally connected to the intermidiate point of the output terminal corresponding IGBT half bridge arm. Note: 1) Use oscilloscope to check voltage waveform of each power supply terminals and P&N terminals, the time division of OSC should be set to about 1μs/div. Please ensure the voltage (including surge) not exceed the specified limitation. Publication Date : November 2012 14 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE 2.4 Mounting Method This section shows the electric spacing and assembling precautions of Mini DIPIPM Ver.4. 2.4.1 Electric Spacing The electric spacing specification of Mini DIPIPM Ver.4 is shown in Table 2-10 Table 2-10 Minimum insulation distance of Mini DIPIPM Ver.4 Clearance(mm) Between power terminals Between control terminals Between terminals and heat sink 4.0 2.5 3.0 Creepage(mm) 4.0 6.0 4.0 Between power terminals Between control terminals Between terminals and heat sink 2.4.2 Mounting Method and Precautions When installing the module to the heat sink, excessive or uneven fastening force might apply stress to inside chips. Then it will lead to a broken or degradation of the device. The recommended fastening procedure is shown in Fig.2-12. When fastening, it is necessary to use the torque wrench and fasten up to the specified torque. Also, pay attention not to have any desert remaining on the contact surface between the module and the heat sink. (2) (1) Temporary fastening (1)(2) Permanent fastening (1)(2) Note: Generally, the temporary fastening torque is set to 20-30% of the maximum torque rating. Not care the order of fastening (1) or (2), but need to fasten alternately. Fig.2-12 Recommended screw fastening order Table 2-12 Mounting torque and heat sink flatness specifications Item Condition Mounting torque Recommended 0.78N·m, Screw : M3 Flatness of outer heat sink Refer Fig.2-13 Min. 0.59 Typ. - Max. 0.98 Unit N·m -50 - +100 μm Note: Recommend to use plain washer (ISO7089-7094) in fastening the screws. Measurement part for heat sink flatness + - - + Measurement part for heat sink flatness Outer heat sink Fig.2-13 Measurement point of heat sink flatness In order to get effective heat dissipation, it is necessary to keep the contact area as large as possible to minimize the contact thermal resistance. Regarding the heat sink flatness (warp, concavity and convexity) on the module installation surface, the surface finishing-treatment should be within Rz12. Evenly apply thermally conductive grease with 100μ-200μm thickness over the contact surface between the module and the heat sink, which is also useful for preventing corrosion. The contacting thermal resistance between DIPIPM case and heat sink Rth(c-f) is determined by the thickness and the thermal conductivity of the applied grease. For reference, Rth(c-f) is about 0.3°C/W (per 1/6 module, grease thickness: 20μm, thermal conductivity: 1.0W/m·k). When applying grease and fixing heat sink, pay attention not to take air into grease. It might lead to make contact thermal resistance worse or loosen fixing in operation. Publication Date : November 2012 15 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE 2.4.3 Soldering Conditions The recommended soldering condition is mentioned as below. (Note: The reflow soldering cannot be recommended for DIPIPM.) (1) Flow (wave) Soldering DIPIPM is tested on the condition described in Table 2-12 about the soldering thermostability, so the recommended conditions for flow (wave) soldering are soldering temperature is up to 265°C and the immersion time is within 11s. For pre-heat temperature, it is recommended to be below 125°C because of the maximum storage temperature of DIPIPM is 125°C. However, the condition might need some adjustment based on flow condition of solder, the speed of the conveyer, the land pattern and the through hole shape on the PCB, etc. It is necessary to confirm whether it is appropriate or not for your real PCB finally. Table 2-12 Reliability test specification Item Condition Soldering Thermostability 260±5°C, 10±1s (2) Hand soldering Since hand soldering condition depends on the soldering iron types (wattages, shape of soldering tip, etc.) and the land pattern on PCB, the unambiguous condition of hand soldering cannot be decided. As a general requirement of the temperature profile for hand soldering, the temperature of the root of the DIPIPM terminal should be kept below 150°C for considering glass transition temperature (Tg) of the package molding resin and the thermal withstand capability of internal chips. Therefore, it is necessary to check the DIPIPM terminal root temperature, solderability and so on in your real PCB, when configure the soldering temperature profile. (It is recommended to set the soldering time as short as possible.) For reference, the evaluation example of hand soldering with 50W soldering iron is described as below. [Evaluation method] a. Sample: Mini DIPIPM Ver.4 b. Evaluation procedure - Put the soldering tip of 50W iron (temperature set to 400°C) on the terminal within 1mm from the toe. (The lowest heat capacity terminal (=control terminal) is selected.) - Measure the temperature rise of the terminal root part by the thermocouple installed on the terminal root. Soldering iron Thermocouple DIPIPM Temp. of terminal root (°C) 1mm 200 150 100 50 0 0 5 10 15 Heating time (s) Fig.2-14 Heating and measuring point Fig.2-15 Temperature alteration of the terminal root (Typcal) [Note] For soldering iron, it is recommended to select one for semiconductor soldering (12~24V low voltage type, and the earthed iron tip) and with temperature adjustment function. Publication Date : November 2012 16 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE CHAPTER 3 SYSTEM APPLICATION HIGHLIGHT 3.1 Application Guidance This chapter states the Mini DIPIPM Ver.4 application method and interface circuit design hints. 3.1.1 System connection P-side input C1: Electrolytic type with good temperature and frequency characteristics. Note: the capacitance also depends on the PWM control strategy of the application system C2:0.22μ-2μF ceramic capacitor with good temperature, frequency and DC bias characteristics C3:0.1μ-0.22μF Film capacitor (for snubber) D1: Bootstrap diode. High speed type with VRRM: over Vces(600V), trr: up to 100ns D2: Zener diode 24V/1W for surge absorber Input signal conditioning Input signal conditioning Input signal conditioning Level shift Level shift Level shift UV lockout circuit Drive circuit UV lockout circuit Drive circuit C1 D2 C2 D1 Bootstrap circuit UV lockout circuit Drive circuit Inrush limiting circuit DIPIPM P P-side IGBTs AC line input Noise filter U V W C3 Varistor M AC output C GDT N N1 N-side IGBTs VNC CIN VNO Drive circuit C : AC filter(ceramic capacitor 2.2n -6.5nF) (Common-mode noise filter) Input signal conditioning N-side input Fo Logic Fo Protection circuit (SC) UV lockout circuit C2 D2 C1 CFO Fo output VNC Fig.3-1 Application System block diagram of Mini DIPIPM Ver.4 Publication Date : November 2012 17 (15V line) VD <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE 3.1.2 Interface Circuit (Direct Coupling Interface. One shunt) Fig.3-2 shows a typical application circuit of interface schematic, in which control signals are transfered directly from a controller (MCU or DSP). VUFB(3) D2 P(37) IGBT1 + Di1 VUFS(1) C1 D1 C2 VP1(4) HVIC U(36) C2 UP(6) VVFB(9) D2 IGBT2 + Di2 VVFS(7) C1 D1 C2 VP1(10) HVIC V(35) C2 M VP(12) VWFB(15) D2 IGBT3 + Di3 VWFS(13) C1 D1 C2 VP1(16) HVIC W(34) MCU C2 WP(18) + IGBT4 Di4 C3 UN(21) NU (33) VN(22) IGBT5 WN(23) Di5 5V R2 NV (32) Fo(24) LVIC CFO(25) 15V VD C1 IGBT6 Di6 NW(31) VN1(28) + D1 C2 VNC(27) C VNO(20) CIN(26) B C4 D Shunt resistor R1 A Control GND wiring N1 Power GND wiring Fig.3-2 Interface circuit example (Direct coupling interface with one shunt resistor) Note: (1) If control GND is connected with power GND by common broad pattern, it may cause malfunction by power GND fluctuation. It is recommended to connect control GND and power GND at only a point N1 (near the terminal of shunt resistor). (2) To prevent surge destruction, the wiring between the smoothing capacitor and the P, N1 terminals should be as short as possible. Generally a 0.1μ-0.22μF snubber capacitor C3 between the P-N1 terminals is recommended. (3) The time constant R1C4 of the protection circuit is recommended to be in the range of 1.5-2μs. SC interrupting time might vary with the wiring pattern. Tight tolerance, temp-compensated type is recommended for R1, C4. (4) All capacitors should be mounted as close to the terminals as possible. (C1: good temperature, frequency characteristic electrolytic type and C2:0.22μ-2μF, good temperature, frequency and DC bias characteristic ceramic type are recommended.) (5) It is recommended to insert a Zener diode D1(24V/1W) between each pair of control supply terminals to prevent surge destruction. (6) The point D at which the wiring to CIN filter is divided should be near the terminal of shunt resistor. (7) For shunt resistor, the variation within 1% (including temperature characteristics), low inductance SMD type is recommended. (8) To prevent malfunction or surge destruction, the wiring of A, B, C should be as short as possible. (9) Fo output is open drain type. It should be pulled up to control power supply (e.g. 5V) by a resistor that makes IFo up to 1mA. (In the case pulling up to 5V supply, over 5kΩ resistor is needed. Normally 10kΩ is recommended.) -6 (10) Fo pulse width can be set by the capacitor connected to CFO terminal. CFO(F) = 12.2 x 10 x tFO (Required Fo pulse width). (11) High voltage (VRRM =600V or more) and fast recovery type (trr=100ns or less) diode D2 should be used for bootstrap circuit. (12) Input drive is High-active type. There is a min. 2.5kΩ pull-down resistor in the input circuit of IC. To prevent malfunction, the wiring of each input should be as short as possible. When using RC coupling circuit, make sure the input signal level meet the turn-on and turn-off threshold voltage.Due to integrate the HVIC, direct coupling to MCU without isolation circuit is possible. (13) If high frequency noise superimposed to the control supply line, IC malfunction might happen and cause DIPIPM erroneous operation. To avoid such problem, line ripple voltage should meet dV/dt ≤+/-1V/μs, Vripple≤2Vp-p. Publication Date : November 2012 18 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE 3.1.3 Interface Circuit (Opto-coupler Isolated Interface) 5V VUFB(3) D2 P(37) IGBT1 + Di1 VUFS(1) C1 D1 C2 VP1(4) HVIC U(36) C2 UP(6) VVFB(9) D2 IGBT2 + Di2 VVFS(7) C1 D1 C2 VP1(10) HVIC V(35) C2 M VP(12) VWFB(15) D2 IGBT3 + Di3 VWFS(13) C1 D1 C2 VP1(16) HVIC W(34) MCU C2 WP(18) + IGBT4 Di4 C3 UN(21) NU (33) VN(22) IGBT5 WN(23) Di5 NV (32) Fo(24) LVIC CFO(25) 15V VD + C1 D1 IGBT6 Di6 NW(31) VN1(28) C2 VNC(27) C VNO(20) CIN(26) B D Shunt resistor R1 C4 A Fig.3-3 Interface circuit example with opto-coupler Note: (1) High speed (high CMR) opto-coupler is recommended. (2) Max. Fo terminal sink current is 1mA. A buffer circuit is necessary to drive an opto-coupler. Publication Date : November 2012 19 N1 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE 3.1.4 External SC Protection Circuit with Using Three Shunt Resistors DIPIPM Drive circuit P P-side IGBTs U V W N-side IGBTs External protection circuit Rf C NW NV NU Protection circuit Vref 5V + Rf D - Cf Vref CIN A - Cf Drive circuit VNC B Shunt resistors OR output + Rf - Cf + Comparators (Open collector output type) Vref N1 Fig.3-4 Interface Circuit example Note: (1) It is necessary to set the time constant RfCf of external comparator input so that IGBT can stop within 2μs when short circuit occurs. SC interrupting time might vary with the wiring pattern, comparator speed and so on. (2) The threshold voltage Vref should be set up the same rating of short circuit trip level (Vsc(ref) typ. 0.48V). (3) Select the shunt resistance so that SC trip-level is less than specified value.(2times of rating current for Mini DIPIPM Ver.4) (4) To avoid malfunction, the wiring A, B, C should be as short as possible. (5) The point D at which the wiring to comparator is divided should be near the terminal of shunt resistor. (6) OR output high level should be over 0.53V (=maximum Vsc(ref)). 3.1.5 Circuits of Signal Input terminals and Fo Terminal (1) Internal Circuit of Control Input Terminals DIPIPM is high-active input logic. Each input circuits of the DIPIPM has a 2.5kΩ(min) pull-down resistor as shown in UP,VP,W P Fig.3-5, so external pull-down resistor is not needed. Furthermore, by lowering the turn on and turn off threshold value of input signal as shown in U ,V ,W N N N Table 3-1, a direct coupling to 3V class microcomputer or DSP becomes possible. DIPIPM 1kΩ Level Shift Circuit Gate Drive Circuit 2.5kΩ (min) 1kΩ Gate Drive Circuit 2.5kΩ (min) Fig.3-5. Internal structure of control input terminals Table 3-1 Input threshold voltage ratings(VD=15V,Tj=25°C) Item Symbol Condition Turn-on threshold voltage Vth(on) UP,VP,W P-VNC terminals Turn-off threshold voltage Vth(off) UN,VN,W N-VNC terminals Threshold voltage hysterisis Vth(hys) Publication Date : November 2012 20 Min. 0.8 0.5 Typ. 2.3 1.4 0.9 Max. 2.6 - Unit V <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE The wiring of each input should be patterned as short as possible. And if the pattern is long and the noise is imposed on the pattern, it may be effective to insert RC filter. 5V 10kΩ DIPIPM UP,VP,WP,UN,VN,WN MCU Fo VNC(Logic) Fig.3-6 Control input connection Note: The RC coupling (parts shown in the dotted line) at each input depends on user’s PWM control strategy and the wiring impedance of the printed circuit board. The DIPIPM signal input section integrates a 2.5kΩ(min) pull-down resistor. Therefore, when using an external filtering resistor, please pay attention to the signal voltage drop at input terminal. There are limits for the minimum input pulse width in the DIPIPM. The DIPIPM might make no response or delayed response, if the input pulse width (both on and off) is shorter than the specified value. (Table 3-2) Table 3-2 Allowable minimum input pulse width Symbol Condition On signal Off signal PWIN(on) - 200≤VCC≤350V, 13.5≤VD≤16.5V, 13.5≤V DB≤18.5V, PWIN(off) -20≤TC≤100°C, N line wiring inductance less than 10nH Up to rated current From rated current to 1.7times of rated current From 1.7 times to 2.0 times of rated current PN PS21765 Min. value 0.3 PS21767 0.3 PS21765 1.4 PS21767 1.5 PS21765 2.5 PS21767 3.0 PS21765 3.0 PS21767 3.6 Unit µs *) Input signal with ON pulse width less than PWIN(on) might make no response. IPM might make delayed response (less than about 2μs) or no response for the input signal with off pulse width less than PWIN(off). Please refer below about delayed responce. P Side Control Input Internal IGBT Gate Output Current Ic t2 t1 Real line: off pulse width>PWIN(off); turn on time t1 Broken line: off pulse width<PWIN(off); turn on time t2 (t1:Normal switching time) Fig.3-7 Delayed Response with shorter input off (P-side only) Publication Date : November 2012 21 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE (2) Internal Circuit of Fo Terminal FO terminal is open drain type, it should be pulled up to a 5V supply as shown in Fig.3-6. Fig.3-8 shows the typical V-I characteristics of Fo output. The maximum sink current of Fo output is 1mA. If opto-coupler is applied to this output, please pay attention to the opto-coupler driving current. Table 3-3 Electric characteristics of Fo output Item Symbol Condition VFOH VSC=0V,Fo=10kΩ,5V pulled-up Fault output voltage VFOL VSC=1V,Fo=1mA Min. 4.9 - Typ. - 0.30 0.25 VFo(V) 0.20 0.15 0.10 0.05 0.00 0 0.2 0.4 0.6 0.8 1 IFo(mA) Fig.3-8 Fo terminal typical V-I characteristics (VD=15V, Tj=25°C) Publication Date : November 2012 22 Max. 0.95 Unit V V <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE 3.1.6 Snubber Circuit In order to prevent DIPIPM from extra surge destruction, the wiring length between the smoothing capacitor and DIPIPM P-N terminals should be as short as possible. Also, a 0.1μ~0.22μF/630V snubber capacitor should be mounted between P and N terminals close to DIPIPM. There are two positions (1) or (2) to mount a snubber capacitor as shown in Fig.3-9. Snubber capacitor should be installed in the position (2) so as to suppress surge voltage effectively. However, the charge and discharge currents generated by the wiring inductance and the snubber capacitance will flow through the shunt resistor, which might cause erroneous protection if this current is large enough. In order to suppress the surge voltage maximally, the wiring at part-A (including shunt resistor parasitic inductance) and part-B should be as small as possible. A better wiring example is shown in location (3). DIPIPM Wiring Inductance P (2) (1) + (3) A N Shunt resistor Fig.3-9 Recommended snubber circuit location 3.1.7 Recommended Wiring method around Shunt Resistor External shunt resistor is employed to detect short-circuit accident. A longer wiring between the shunt resistor and DIPIPM might cause so much large surge that might damage built-in IC. To decrease the pattern inductance, the wiring between the shunt and DIPIPM should be as short as possible and using low inductance type resistor such as SMD resistor instead of long-lead type resistor. It is recommended to make the inductance of this part (including the shunt resistor) under 10nH. For shunt resistor, it is recommended to use as low inductance type as possible. DIPIPM e.g. Inductance of copper pattern (width=3mm,length=17mm) is about 10nH. VNO NU Shunt resistor NV VNC NW Please make the GND wiring connection of shunt resistor to the VNC terminal as close as possible. (a) Wiring instruction (For one shunt ) It is recommended to make the inductance of this part (including the shunt resistor) under 10nH. For shunt resistor, it is recommended to use as low inductance type as possible. e.g. Inductance of copper pattern (width=3mm,length=17mm) is about 10nH. DIPIPM VNO NU NV VNC NW Shunt resistors Please make the GND wiring connection of shunt resistor to the VNC terminal as close as possible. (b) Wiring instruction (For three shunts) Fig.3-10 Recommended wiring method of shunt resistor Publication Date : November 2012 23 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE Influence of pattern wiring around the shunt resistor is shown below. Drive Circuit DIPIPM P P-side IGBTs U V W SC protection external part DC-bus current route N-side IGBTs B NW NV NU Drive Circuit A R2 C CIN C1 SC protection VNC Shunt resistor D N1 Fig.3-11 External protection circuit (1) Influence of the part-A wiring The ground of Low-side IGBT gate is VNC. If part-A wiring pattern in Fig.3-11 is too long, extra voltage generated by the wiring parasitic inductor will result the potential of IGBT emitter variation during switching operation. Please install shunt resistor as close to the N terminal as possible. (2) Influence of the part-B wiring The part-B wiring affects SC protection level. SC protection works by judging the voltage of the CIN terminals. If part-B wiring is too long, extra surge voltage generated by the wiring inductance will lead to deterioration of SC protection level. It is necessary to connect CIN and VNC terminals directly to the two ends of shunt resistor and avoid long wiring. (3) Influence of the part-C wiring pattern C1R2 filter is added to remove noise influence occurring on shunt resistor. Filter effect will dropdown and noise will easily superimpose on the wiring if part-C wiring is too long. Please install the C1R2 filter near CIN, VNC terminals as close as possible. (4) Influence of the part-D wiring pattern Part-D wiring pattern gives influence to all the items described above, maximally shorten the GND wiring is expected. Publication Date : November 2012 24 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE 3.1.8 Precaution for wiring on PCB These wires' potentials fluctuate between Vcc and GND potential at switching. If wires for control (e.g. control input Vin, control supply) are located near by or cross these wires. It may cause malfunction It is recommended to locate wires for control as far from these wires as possible. Capacitors and Zener diode should be located at near terminals DIPIPM VUFS,VUFS,VWFS Output (to motor) P VUFB,VUFB,VWFB Bootstrap diode 4 U Power supply line UP, VP, WP Vin V UN, VN, WN +15V VN1,VP1 3 Capacitors and Zener diode should be located at near terminals Snubber Capacitor W VNC NU CFO 2 Shunt resistor NV CIN Capacitors for CIN filter and Fo pulse width should be connected to control GND (not to Power GND) Cin wiring should be as short as possible Power GND line N1 NW 1 The control GND should be connected to the power GND at only a point. (not broad pattern) Control GND line NU, NV, NW should be connected each other as close to the terminals as possible. Fig.3-12 Precaution for wiring on PCB The case example of trouble due to PCB pattern 1 Case example •Control GND pattern overlaps power GND pattern. •Ground loop pattern exists. 2 •Long pattern between NU, NV, NW terminals and N1(including inductance of shunt resistor) 3 Capacitors or zener diodes are nothing or located far from the terminals. The input lines are located parallel and close to the floating supply lines for P-side drive. 4 Matter of trouble The surge, generated by the wiring pattern and di/dt of noncontiguous big current flows to power GND, transfers to control GND pattern. It causes the control GND level fluctuation, so that the input signal based on the control GND fluctuates too. Then the arm short might occur. Stray current flows to GND loop pattern, so that the control GND level and input signal level (based on the GND) fluctuates. Then the arm short might occur. Long wiring pattern has big parasitic inductance and generates high surge when switching. This surge causes the matter as below. •HVIC malfunction by VS voltage (output terminal potential) decreasing excessively. •LVIC surge destruction IC surge destruction or malfunction might occurs. The cross talk noise might be transferred through the capacitance between these floating supply lines and input lines to DIPIPM. Then since the incorrect signals are input to DIPIPM input, the arm short might occur. Publication Date : November 2012 25 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE 3.1.9 Parallel operation of DIPIPM Fig.3-13 shows the circuitry of parallel connection of two DIPIPMs. Route (1) and (2) indicate the gate charging path of low-side IGBT in DIPIPM No.1 & 2 respectively. In the case of DIPIPM 1, the parasitic inductance becomes large by long wiring and it might have a negative effect on DIPIPM's switching operation. (Charging of bootstrap capacitor for high-side might be affected similarly.) Also, such a wiring makes DIPIPM be affected by noise easily, then it might lead to malfunction. If more DIPIPMs are connected in parallel, GND pattern becomes longer and the influence to other circuit (power supply, protection circuit etc.) by the fluctuation of GND potential might occur. Therefore parallel connection is not recommended. Also because DIPIPM doesn't consider about the fluctuation of characteristics between each phases definitely, it cannot be recommended to drive same load by parallel connection with other phase IGBT or IGBT of other DIPIPM. DIPIPM 1 VP DC15V P VP1 VP1 U,V,W M AC100/200V VN1 N VNC Shunt resistor (1) DIPIPM 2 VP1 P VP VP1 U,V,W M VN1 N VN Shunt resistor (2) Fig.3-13 Parallel operation 3.1.10 SOA of Mini DIPIPM Ver.4 The following describes the SOA (Safety Operating Area) of the Mini DIPIPM Ver.4. Maximum rating of IGBT collector-emitter voltage VCES : VCC : Supply voltage applied on P-N terminals VCC(surge): The total amount of VCC and the surge voltage generated by the wiring inductance and the DC-link capacitor. VCC(PROT) : DC-link voltage that DIPIPM can protect itself. Collector current Ic ≤Vcc(surge) ≤VCC ≤Vcc(surge) Short-circuit current ≤VCC(PROT) VCE=0, IC=0 VCE=0, IC=0 ≤2μs Fig.3-14 SOA at switching mode and short-circuit mode In Case of switching VCES represents the maximum voltage rating (600V) of the IGBT. By subtracting the surge voltage (100V or less) generated by internal wiring inductance from VCES is VCC(surge), that is 500V. Furthermore, by subtracting the surge voltage (50V or less) generated by the wiring inductor between DIPIPM and DC-link capacitor from VCC(surge) derives VCC, that is 450V. In Case of Short-circuit VCES represents the maximum voltage rating (600V) of the IGBT. By Subtracting the surge voltage (100V or less) generated by internal wiring inductor from VCES is VCC(surge), that is, 500V. Furthermore, by subtracting the surge voltage (100V or less) generated by the wiring inductor between the DIPIPM and the electrolytic capacitor from VCC(surge) derives VCC, that is, 400V. Publication Date : November 2012 26 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE 3.1.11 SCSOA Fig.3-15,16 shows the typical SCSOA performance curves example of PS21765,PS21767. Conditions: Vcc=400V, Tj=125°C at initial state, Vcc(surge)≤500V(surge included), non-repetitive,2m load. Fig.3-15 shows PS21765 can shutdown safely an SC current that is about 9 times of its current rating under the conditions only if the IGBT conducting period is less than 4.5μs. Since the SCSOA operation area will vary with the control supply voltage, DC-link voltage, and so on, it is necessary to set time constant of RC filter with a margin. 300 VD =18.5V 250 VD =16.5V Ic(peak) [A] 200 VD =15V ↑ Max. Saturation Current≈186A @VD =16.5V 150 100 CSTBT SC operation area 50 0 0 1 2 3 4 4.5 5 6 7 Input pulse width [μs] Fig.3-15 Typical SCSOA curve of PS21765 400 VD=18.5V 350 VD=16.5V Ic(peak) [A] 300 200 ↑ Max. Saturation Current≈290A @VD=16.5V 150 CSTBT SC operation area 250 VD=15V 100 50 0 0 1 2 3 4 4.5 5 Input pulse width [μs] Fig.3-16 Typical SCSOA curve of PS21767 Publication Date : November 2012 27 6 7 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE 3.1.12 Power Life Cycles When DIPIPM is in operation, repetitive temperature variation will happens on the IGBT junctions (∆Tj). The amplitude and the times of the junction temperature variation affect the device lifetime. Fig.3-17 shows the IGBT power cycle curve as a function of average junction temperature variation (∆Tj). (The curve is a regression curve based on 3 points of ∆Tj=46, 88, 98K with regarding to failure rate of 0.1%, 1% and 10%. These data are obtained from the reliability test of intermittent conducting operation) 10000000 1% 10% 0.1% Power Cycles 1000000 100000 10000 1000 10 100 Average junction temperature variation ΔTj(K) Fig.3-17 Power cycle curve Publication Date : November 2012 28 1000 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE 3.2 Power Loss and Thermal Dissipation Calculation 3.2.1 Power Loss Calculation Simple expressions for calculating average power loss are given below: ● Scope The power loss calculation intends to provide users a way of selecting a matched power device for their VVVF inverter application. However, it is not expected to use for limit thermal dissipation design. ● Assumptions (1) PWM controlled VVVF inverter with sinusoidal output; (2) PWM signals are generated by the comparison of sine waveform and triangular waveform. (3) Duty amplitude of PWM signals varies between 1− D 1+ D (%/100), (D: modulation depth). ~ 2 2 (4) Output current various with Icp·sinx and it does not include ripple. (5) Power factor of load output current is cosθ, ideal inductive load is used for switching. ● Expressions Derivation PWM signal duty is a function of phase angle x as 1 + D × sin x which is equivalent to the output voltage 2 variation. From the power factor cosθ, the output current and its corresponding PWM duty at any phase angle x can be obtained as below: Output current = Icp × sin x 1 + D × sin( x + θ ) PWM Duty = 2 Then, VCE(sat) and VEC at the phase x can be calculated by using a linear approximation: Vce( sat ) = Vce( sat )(@ Icp × sin x) Vec = (−1) × Vec(@ Iecp(= Icp) × sin x) Thus, the static loss of IGBT is given by: 1 2π ∫ π 0 ( Icp × sin x) ×Vce( sat )(@ Icp × sin x) × 1 + D sin( x + θ ) • dx 2 Similarly, the static loss of free-wheeling diode is given by: 1 2π 2π ∫π ((−1) × Icp × sin x)((−1) × Vec(@ Icp × sin x) × 1 + D sin( x + θ ) • dx 2 On the other hand, the dynamic loss of IGBT, which does not depend on PWM duty, is given by: 1 2π ∫ π 0 ( Psw(on)(@ Icp × sin x) + Psw(off )(@ Icp × sin x)) × fc • dx Publication Date : November 2012 29 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE FWDi recovery characteristics can be approximated by the ideal curve shown in Fig.3-18, and its dynamic loss can be calculated by the following expression: trr IEC VEC t Irr Vcc Fig.3-18 Ideal FWDi recovery characteristics curve Psw = Irr × Vcc × trr 4 Recovery occurs only in the half cycle of the output current, thus the dynamic loss is calculated by: 1 2π Irr (@ Icp × sin x) × Vcc × trr (@ Icp × sin x) × fc • dx 4 2 ∫π 1 2π = ∫ Irr (@ Icp × sin x) × Vcc × trr (@ Icp × sin x) × fc • dx 8 ρ ● Attention of applying the power loss simulation for inverter designs ・ Divide the output current period into fine-steps and calculate the losses at each step based on the actual values of PWM duty, output current, VCE(sat), VEC, and Psw corresponding to the output current. The worst condition is most important. ・ PWM duty depends on the signal generating way. ・ The relationship between output current waveform or output current and PWM duty changes with the way of signal generating, load, and other various factors. Thus, calculation should be carried out on the basis of actual waveform data. ・ VCE(sat),VEC and Psw(on, off) should be the values at Tj=125°C. Publication Date : November 2012 30 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE 3.2.2 Temperature Rise Considerations and Calculation Example Fig.3-19 shows the typical characteristics of allowable motor rms current versus carrier frequency under the following inverter operating conditions based on power loss simulation results. Conditions: VCC=300V, VD=VDB=15V, VCE(sat)=Typ., Switching loss=Typ., Tj=125°C, Tf=100°C, Rth(j-f)=Max., Rth(c-f)=0.3°C/W (per 1/6 module), P.F=0.8, 3-phase PWM modulation, 60Hz sine waveform output 24 22 20 18 Io(Arms) 16 14 PS21767 12 PS21765 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 fc(kHz) Fig.3-19 Effective current-carrier frequency characteristics Fig.3-19 shows an example of estimating allowable inverter output rms current under different carrier frequency and permissible maximum operating temperature condition (Tf=100°C. Tj=125°C). The results may change for different control strategy and motor types. Anyway please ensure that there is no large current over device rating flowing continuously. The allowable motor current can also be obtained from the free power loss simulation software provided at our web site. URL: http://www.MitsubishiElectric.com/semiconductors/ Publication Date : November 2012 31 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE 3.3 Noise Withstand Capability 3.3.1 Evaluation Circuit Mini DIPIPM Ver.4 series have been confirmed to be with over +/-2.0kV noise withstand capability by the noise evaluation under the conditions shown in Fig.3-20. However, noise withstand capability greatly depends on the test environment, the wiring patterns of control substrate, parts layout, and other factors; therefore an additional confirmation on prototype is necessary. C R Breaker U V W DIPIPM S T AC input M Fo Voltage slider Control supply (15V single power source) I/F Isolation transformer Heat sink Inverter DC supply Noise simulator AC100V Fig.3-20 Noise withstand capability evaluation circuit Note: C1: AC line common-mode filter 4700pF, PWM signals are input from microcomputer by using opto-couplers, 15V single power supply, Test is performed with IM Test conditions VCC=300V, VD=15V, Ta=25°C, no load Scheme of applying noise: From AC line (R, S, T), Period T=16ms, Pulse width tw=0.05-1μs, input in random. 3.3.2 Countermeasures and Precautions DIPIPM improves noise withstand capabilities by means of reducing parts quantity, lowering internal wiring parasitic inductance, and reducing leakage current. But when the noise affects on the control terminals of DIPIPM (due to wiring pattern on PCB), the short circuit or malfunction of SC protection may occur. In that case, below countermeasures are recommended. P C2+ C2 Increase the capacitance of C2 and locate it as close to the terminal as possible. C2+ C2 C2+ MCU Insert the RC filter C2 VUFB VUFS VP1 HVIC U UP VVFB VVFS VP1 HVIC V VP M VWFB VWFS VP1 HVIC W + WP C3 UN NU VN WN NV Fo LVIC CFo Increase the capacitance of C4 with keeping the same time constant R1·C4, and locate the C4 as close to the terminal as possible. NW VD + C2 VN1 VNC VNO CIN C4 R1 Fig.3-21 Example of countermeasures for inverter part Publication Date : November 2012 32 N1 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE 3.3.3 Static Electricity Withstand Capability DIPIPM has been confirmed to be with +/-200V or more withstand capability against static electricity from the following tests shown in Fig.3-22, 23. The results (typical data) are described in Table 3-4. R=0Ω LVIC HVIC R=0Ω VN1 UN VN WN C=200pF VP1 VUFB UP Ho VPC VUFS C=200pF VNC Fig.3-22 LVIC terminal Surge Test circuit Fig.3-23 HVIC terminal Surge Test circuit Conditions: Surge voltage increases in steps of 0.1V and only one-shot surge pulse is impressed at each voltage. (Limit voltage of surge simulator: ±4.0kV, Judgment method; change in V-I characteristic) Table 3-4 Typical ESD capability for PS219765, PS21767 [Control terminal part] For control part, since both have same circuit in the control IC, they have same capability. Terminals UP, VP, WP-VNC VP1 - VNC VUFB-VUFS, VVFB-VVFS,VWFB-VWFS UN, VN, WN-VNC VN1-VNC CIN-VNC Fo-VNC CFO-VNC VNO-VNC + - 0.9 1.5 3.7 1.0 1.8 1.1 1.0 0.3 2.0 1.8 1.6 3.5 1.5 3.1 1.6 1.9 0.7 3.1 + 4.0 or more 3.2 4.0 or more 4.0 or more + 4.0 or more 4.0 or more 4.0 or more 4.0 or more (Unit: kV) [Power terminal part for PS21765] Terminals P-N U-N, V-N, W-N [Power terminal part for PS21767] Terminals P-N U-N, V-N, W-N Publication Date : November 2012 33 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE CHAPTER 4 KEY PARAMETERS SELECTING GUIDANCE 4.1 Determination of Shunt Resistance (1) Shunt resistance The value of current sensing resistance is calculated by the following expression: RShunt = VSC(ref)/SC where VSC(ref) is the referenced SC trip voltage. The maximum value of SC trip level should be set less than the IGBT minimum saturation current which is 2.0 times as large as the rated current. For example, the maximum SC trip level of PS21767 should be set to 2.0 x 30=60.0A. The parameters (VSC(ref), RShunt) dispersion should be considered when designing the SC trip level. For example of PS21767, there is +/-0.05V dispersion in the spec of VSC(ref) as shown in Table 4-1. (unit: V) Min 0.43 Table 4-1 Specification for VSC(ref) Condition Specification at Tj=25°C, VD=15V Typ 0.48 Max 0.53 Then, the range of SC trip level can be calculated by the following expressions: RShunt(min)=VSC(ref) max /SC(max) RShunt(typ)= RShunt(min) / 0.95* then SC(typ) = VSC(ref) typ / RShunt(typ) RShunt(max)= RShunt(typ) x 1.05* then SC(min)= VSC(ref) min / RShunt(max) *)This is the case that shunt resistance dispersion is within +/-5%. So the SC trip level range is described as Table 4-2. Table 4-2 Operative SC Range (unit: A) (RShunt=8.8mΩ(min), 9.3mΩ(typ), 9.8mΩ(max) min. typ. max. at Tj=25°C 43.9 51.6 60.0 (e.g. 8.8mΩ (Rshunt(min))= 0.53V (=VSC(max)) / 60A(=SC(max)) Condition There is the possibility that the actual SC protection level becomes less than the calculated value. This is considered due to the resonant signals caused mainly by parasitic inductance and parasitic capacity. It is recommended to make a confirmation of the resistance by prototype experiment. (2) RC Filter Time Constant It is necessary to set an RC filter in the SC sensing circuit in order to prevent malfunction of SC protection due to noise interference. The RC time constant is determined depending on the applying time of noise interference and the SCSOA of the DIPIPM. When the voltage drop on the external shunt resistor exceeds the SC trip level, The time (t1) that the CIN terminal voltage rises to the referenced SC trip level can be calculated by the following expression: VSC = R shunt ⋅ I c ⋅ (1 − ε t1 = −τ ⋅ ln(1 − − VSC R shunt ⋅ I c t1 τ ) ) where Vsc : CIN terminal input voltage, Ic: peak current, τ : RC time constant. On the other hand, the typical time delay t2 (from Vsc voltage reaches Vsc(ref) to IGBT gate shutdown) of IC is shown in Table 4-3. Table 4-3 Internal time delay of IC Item min typ max Unit μs IC transfer delay time 0.3 0.5 1.0 Therefore, the total delay time from an SC level current happened to the IGBT gate shutdown becomes: tTOTAL=t1+t2 Publication Date : November 2012 34 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE 4.2 Bootstrap Circuit Operation 4.2.1 Bootstrap Circuit Operation For three phase inverter circuit driving, normally four isolated control supplies (three for P-side driving and one for N-side driving) are necessary. But using floating control supply with bootstrap circuit can reduce the number of isolated control supplies from four to one (N-side control supply). Bootstrap circuit consists of a bootstrap diode(BSD), a bootstrap capacitor(BSC) and a current limiting resistor. It uses the BSC as a control supply for driving P-side IGBT. The BSC supplies gate charge when P-side IGBT turning ON and circuit current of logic circuit on P-side driving IC. (Fig.4-2) Since a capacitor is used as substitute for isolated supply, its supply capability is limited. This floating supply driving with bootstrap circuit is suitable for small supply current products like DIPIPM. Charge consumed by driving circuit is re-charged from N-side 15V control supply to BSC via current limiting resistor and BSD when voltage of output terminal (U, V or W) goes down to GND potential in inverter operation. But there is the possibility that enough charge doesn't perform due to the conditions such as switching sequence, capacitance of BSC, limiting resistance and so on. Deficient charge leads to low voltage of BSC and might work under voltage protection (UV). This situation makes the loss of P-side IGBT increase by low gate voltage or stop switching. So it is necessary to consider and evaluate enough for designing bootstrap circuit. For more detail information about driving by the bootstrap circuit, refer the DIPIPM application note "Bootstrap Circuit Design Manual" The circuit current characteristics in switching situation of P-side IGBT are described below. Current limiting resistor Bootstrap diode (BSD) BSC + P-side IGBT VP1 VD=15V N-side IGBT VN1 LVIC N-side FWDi VPC P(Vcc) + Gate Drive U,V,W VFS ↑High voltage area VFB Logic & UV protection P-side FWDi Level Shift Low voltage area Level Shift VPC VFB BSD 15V P(Vcc) HVIC VP1 Bootstrap capacitor (BSC) P-side IGBT P-side FWDi VFS U,V,W Voltage of VFS that is reference voltage of BSC swings between VCC and GND level. If voltage of BSC is lower than 15V when VFS becomes to GND potential, BSC is charged from 15V N-side control supply. VNC N(GND) Fig.4-1 Bootstrap Circuit Diagram Fig.4-2 Bootstrap Circuit Diagram Publication Date : November 2012 35 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE 4.2.2 Bootstrap Supply Circuit Current at Switching State Circuit current (mA) Bootstrap supply circuit current IDB at steady state is max.0.55mA for PS2176* series. But at switching state, because gate charge and discharge are repeated by switching, the circuit current will exceed 0.55mA and increases proportional to carrier frequency. For reference, Fig.4-3 to Fig.4-4 are the circuit current IDB for P-side IGBT driving supply (VDB) vs. carrier frequency characteristics. (@ VD=VDB=15V, Tj=125°C (largest IDB temperature point), IGBT ON Duty=10, 30, 50, 70, 90%) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 10% 30% 50% 70% 90% 0 5 10 Carrier frequency (kHz) 15 20 Circuit current (mA) Fig.4-3 IDB vs. Carrier frequency for PS21765 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 10% 30% 50% 70% 90% 0 5 10 Carrier frequency (kHz) 15 20 Fig.4-4 IDB vs. Carrier frequency for PS21767 4.2.3 Note for designing the bootstrap circuit When each device for bootstrap circuit is designed, it is necessary to consider various conditions such as temperature characteristics, change by lifetime, variation and so on. Note for designing these devices are listed as below. For more detail information about driving by the bootstrap circuit, refer the DIPIPM application note "Bootstrap Circuit Design Manual" (1) Bootstrap capacitor Electrolytic capacitors are used for BSC generally. And recently ceramic capacitors with large capacitance are also applied. But DC bias characteristic of the ceramic capacitor when applying DC voltage is considerably different from that of electrolytic capacitor. (Especially large capacitance type) Some differences of capacitance characteristics between electrolytic and ceramic capacitors are listed in Table 4-4. Publication Date : November 2012 36 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE Table 4-4 Differences of capacitance characteristics between electrolytic and ceramic capacitors Ceramic capacitor Electrolytic capacitor (large capacitance type) Different due to temp. characteristics • Aluminum type: Temperature rank Low temp.: -10% High temp: +10% characteristics Low temp.: -5%~0% • Conductive polymer aluminum solid type: (Ta:-20~ 85°C) High temp.: -5%~-10% Low temp.: -5% High temp: +10% (in the case of B,X5R,X7R ranks) DC bias characteristics (Applying DC15V) Different due to temp. characteristics, rating voltage, package size and so on -70%~-15% Nothing within rating voltage DC bias characteristic of electrolytic capacitor is not matter. But it is necessary to note ripple capability by repetitive charge and discharge, life time which is greatly affected by ambient temperature and so on. Above characteristics are just example data which are obtained from the WEB, please refer to the capacitor manufacturers about detailed characteristics. (2) Bootstrap diode It is recommended for BSD to have same or higher blocking voltage with collector-emitter voltage VCES of IGBT in DIPIPM. (i.e. 600V or more is needed in the case of 600V DIPIPM.) And its recovery time trr should be less than 100ns. (Fast recovery type) Also it is highly recommended to apply the high quality product such as small variations of blocking voltage. If BSD broke by impressed overvoltage and shorted, it leads to the control ICs over voltage destruction because DC-link voltage (Vcc) is impressed upon low voltage area of control ICs. Then DIPIPM will lose various functions like protection and gate driving and it may lead to serious system destruction. (3) Current limiting resistor When designing limiting resistor, it is important to note its power rating, surge withstand capability (there is the possibility that surge may be impressed on the resistor when switching ON or OFF timing) and so on. Especially if small chip type resistor is applied, it is recommended to select anti-surge designed type. For detailed information, please refer to the resistor manufacturer. Publication Date : November 2012 37 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE CHAPTER 5 Interface Demo Board 5.1 Mini DIPIPM Ver.4 Interface Demo Board This chapter describes the interface demo board of Mini DIPIPM Ver.4 as a reference for the design of user application PCB with Mini DIPIPM Ver.4. (1) Demo Board Outline The demo board consists of the minimum necessary components such as snubber capacitor, bootstrap circuit elements of Mini DIPIPM Ver.4 interface shown in Fig.5-1. C2 C1 Inrush Circuit P DIPIPM AC Supply HVIC Motor ~ LVIC C Z N VNC VN1 CIN RC Filter Mini DIPIPM Ver.4 Interface circuit GND VD (15V Line) UP~WN Fo Fig.5-1 Demo board interface circuit (2) Demo Board Photos Top view Side view Fig.5-2 Demo board photo Note: Board dimension 70.0×54.0×24.2mm (including snubber capacitor height and module height) Publication Date : November 2012 38 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE 5.2 Pattern Wiring (1) PCB Pattern Layout (a) Component side (b) Solder side Fig.5-3 Demo board PCB pattern layout This evaluation board is made for your quick and temporary evaluation. Please confirm and comply with your design standard when designing PCB pattern with reference to these patterns. Publication Date : November 2012 39 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE 5.3 Circuit Schematic and Parts List (1) Circuit Schematic T1 D1 R1 C1 C4 UP R2 C5 T2-1 VVFS C8 D3 U VVFB VP1 VP R3 C3 C9 C6 U Mini DIPIPM C2 VWFB VWFS V T2-2 V VP1 WP WP C10 UN VN VN WN WN FO W VN1 UN ZD1 GND C14 NU NV VNC VNO CFO NW CIN C15 C11 T2-3 W FO R4 +5V +15V P VP1 D2 VP P VUFS C7 UP T3-1 VUFB R5 C13 C12 R6 T3-2 N1 Fig.5-4 Demo board circuit schematic Note: Although there is no zener diode mounted to P-side three floating drive supplies (between VUFB-VUFS, VVFB-VVFS,VWFB-VWFS) on this demo board, it is highly recommend to add these zener diodes in actual system board. Publication Date : November 2012 40 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE (2) Parts List Table 5-1 Parts list (only for reference) Symbol Type Name D1 D2 D3 ZD1 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 R1 R2 R3 R4 R5 R6-1 R6-2 R6-3 T1 T2-1 T2-2 T2-3 T3-1 T3-2 10DRA60 10DRA60 10DRA60 U1ZB24 UPW1H220MDD UPW1H220MDD UPW1H220MDD C1608X7R1H102K C1608X7R1H102K C1608X7R1H102K C1608X7R1H102K C1608X7R1H102K C1608X7R1H102K C1608X7R1H102K UPW1H470MED GRM39R223K50 C1608X7R1H102K MDDSA0.22μF630 V RK73H1JTD10F RK73H1JTD10F RK73H1JTD10F RK73H1JTD10kF RK73H1JTD2kF SL2TBK33/47LOF SL2TBK33/47LOF SL2TBK33/47LOF B10P-VH TP42097-21 TP42097-21 TP42097-21 TP42097-21 TP42097-21 Description 1A 600V Diode 1A 600V Diode 1A 600V Diode 24V 1W Zener Diode 22μF50V Al electrolytic capacitor 22μF50V Al electrolytic capacitor 22μF50V Al electrolytic capacitor 1000pF50V ceramic capacitor 1000pF50V ceramic capacitor 1000pF50V ceramic capacitor 1000pF50V ceramic capacitor 1000pF50V ceramic capacitor 1000pF50V ceramic capacitor 1000pF50V ceramic capacitor 47μF50V Al electrolytic capacitor 0.022μF50V ceramic capacitor 1000pF50V ceramic capacitor 0.22μF630V snubber capacitor 1/16W 10ΩF 1/16W 10Ω F 1/16W 10Ω F 1/16W 10KΩ F 1/16W 2KΩ F PS21765: 47mΩ, ±1%, 2WX3 PS21767: 33mΩ, ±1%, 2WX3 10pin Socket Note Japan International Japan International Japan International Toshiba Nichicon Nichicon Nichicon TDK TDK TDK TDK TDK TDK TDK Nichicon Murata TDK Hitachi AIC Hokuriku Denko Hokuriku Denko Hokuriku Denko Hokuriku Denko Hokuriku Denko KOA, Current detecting resistor JST Kyoushin Kyoushin Kyoushin Kyoushin Kyoushin Faston* tab Faston* tab Faston* tab Faston* tab Faston* tab * Faston is the trademark of Tyco Electronics Corporation. These are example of parts for this evaluation board. When selecting parts for your PCB, please comply with your design standard and consider life time, reliability and so on. Publication Date : November 2012 41 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE CHAPTER 6 PACKAGE HANDLING 6.1 Packaging Specification (55) (19) Plastic Tube Quantity: 9pcs per 1 tube DIPIPM (520) 4 columns Total amount in one box (max): ・・・ When it isn't fully filled by tubes at top stage, cardboard spacers or empty tubes are inserted for filling the spcae of top stage. ・・・ ・・・ ・・・ 8 stages Tube Quantity: 4 × 8=32pcs IPM Quantity: 32 × 9=288pcs (230) (175) Weight (max): About 21g per 1pcs of DIPIPM About 300g per 1 tube About 11kg per 1 box (545) Packaging box Spacers are inserted into the top and bottom of the box. If there is some space on top of the box, additional buffer materials are also inserted. Fig.6-1 Mini DIPIPM Ver.4 Packaging Specification Publication Date : November 2012 42 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE 6.2 Handling Precautions ! Cautions Transportation ·Put package boxes in the correct direction. Putting them upside down, leaning them or giving them uneven stress might cause electrode terminals to be deformed or resin case to be damaged. ·Throwing or dropping the packaging boxes might cause the devices to be damaged. ·Wetting the packaging boxes might cause the breakdown of devices when operating. Pay attention not to wet them when transporting on a rainy or a snowy day. Storage ·We recommend temperature and humidity in the ranges 5-35°C and 45-75%, respectively, for the storage of modules. The quality or reliability of the modules might decline if the storage conditions are much different from the above. Long storage ·When storing modules for a long time (more than one year), keep them dry. Also, when using them after long storage, make sure that there is no visible flaw, stain or rust, etc. on their exterior. Surroundings ·Keep modules away from places where water or organic solvent may attach to them directly or where corrosive gas, explosive gas, fine dust or salt, etc. may exist. They might cause serious problems. Flame resistance ·The case material is flame-resistant type (UL standard 94V-0), but they are not noninflammable. Static electricity ·ICs and power chips with MOS gate structure are used for the DIPIPM power modules. Please keep the following notices to prevent modules from being damaged by static electricity. (1)Precautions against the device destruction caused by the ESD The ESD of human bodies and packaging and/or excessive voltage applied across the gate to emitter may damage and destroy devices. The basis of anti-electrostatic is to inhibit generating static electricity possibly and quick dissipation of the charged electricity. *Containers that charge static electricity easily should not be used for transit and for storage. *Terminals should be always shorted with a carbon cloth or the like until just before using the module. Never touch terminals with bare hands. *Should not be taking out DIPIPM from tubes until just before using DIPIPM and never touch terminals with bare hands. *During assembly and after taking out DIPIPM from tubes, always earth the equipment and your body. It is recommended to cover the work bench and its surrounding floor with earthed conductive mats. *When the terminals are open on the printed circuit board with mounted modules, the modules might be damaged by static electricity on the printed circuit board. *If using a soldering iron, earth its tip. (2)Notice when the control terminals are open *When the control terminals are open, do not apply voltage between the collector and emitter. It might cause malfunction. *Short the terminals before taking a module off. Publication Date : November 2012 43 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE Revision Record Rev. Date 1 2011/6/15 2 2012/11/15 Points New P.32 Fig.3-21 Example of countermeasures for inverter part P.35 Section 4.2 Bootstrap Circuit Operation Publication Date : November 2012 44 <Dual-In-Line Package Intelligent Power Module> MINI DIPIPM Ver.4 Series APPLICATION NOTE Keep safety first in your circuit designs! Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. 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