PSS05S72FT

< Dual-In-Line Package Intelligent Power Module >
PSS05S72FT
TRANSFER MOLDING TYPE
INSULATED TYPE
OUTLINE
MAIN FUNCTION AND RATINGS
 3 phase DC/AC inverter
 1200V / 5A (CSTBT)
 N-side IGBT open emitter
 Built-in bootstrap diodes with current limiting resistor
APPLICATION
 AC 400Vrms(DC voltage:800V or below) class
low power motor control
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS
● For P-side
: Drive circuit, High voltage high-speed level shifting, Control supply under-voltage (UV) protection
● For N-side
: Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC),
● Fault signaling : Corresponding to SC fault (N-side IGBT), UV fault (N-side supply)
● Temperature output : Outputting LVIC temperature by analog signal
● Input interface : 5V line, Schmitt trigger receiver circuit (High Active)
● UL Recognized : UL1557 File E80276
INTERNAL CIRCUIT
VUFS(1)
VUFB(3)
P(37)
HVIC1
IGBT1
VP1(4)
UP(6)
Di1
HO
U(36)
VVFS(7)
VVFB(9)
HVIC2
IGBT2
VP1(10)
VP(12)
Di2
HO
V(35)
VWFS(13)
VWFB(15)
HVIC3
IGBT3
Di3
VP1(16)
W P(18)
HO
W(34)
IGBT4
Di4
LVIC
VOT(20)
UOUT
NU(33)
UN(21)
IGBT5
Di5
VN(22)
W N(23)
VOUT
NV(32)
FO(24)
IGBT6
Di6
CFO(25)
CIN(26)
W OUT
NW(31)
VNC(27)
VN1(28)
Publication Date : March 2015
1
< Dual-In-Line Package Intelligent Power Module >
PSS05S72FT
TRANSFER MOLDING TYPE
INSULATED TYPE
MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted)
INVERTER PART
Symbol
VCC
VCC(surge)
VCES
±IC
±ICP
Tj
Parameter
Supply voltage
Supply voltage (surge)
Collector-emitter voltage
Each IGBT collector current
Each IGBT collector current (peak)
Junction temperature
Condition
Applied between P-NU,NV,NW
Applied between P-NU,NV,NW
TC= 25°C
TC= 25°C, less than 1ms
(Note 1)
Ratings
900
1000
1200
5
10
-30~+150
Unit
V
V
V
A
A
°C
Ratings
20
20
-0.5~VD+0.5
-0.5~VD+0.5
1
-0.5~VD+0.5
Unit
V
V
V
V
mA
V
Ratings
Unit
800
V
-30~+100
-40~+125
°C
°C
2500
Vrms
Note1: Pulse width and period are limited due to junction temperature.
CONTROL (PROTECTION) PART
Symbol
VD
VDB
VIN
VFO
IFO
VSC
Parameter
Control supply voltage
Control supply voltage
Input voltage
Fault output supply voltage
Fault output current
Current sensing input voltage
Condition
Applied between VP1-VNC, VN1-VNC
Applied between VUFB-VUFS, VVFB-VVFS ,VWFB-VWFS
Applied between UP, VP, WP-VPC, UN, VN, WN-VNC
Applied between FO-VNC
Sink current at FO terminal
Applied between CIN-VNC
TOTAL SYSTEM
Symbol
TC
Tstg
Parameter
Self protection supply voltage limit
(Short circuit protection capability)
Module case operation temperature
Storage temperature
Viso
Isolation voltage
VCC(PROT)
Condition
VD = 13.5~16.5V, Inverter Part
Tj = 125°C, non-repetitive, less than 2μs
Measurement point of Tc is provided in Fig.1
60Hz, Sinusoidal, AC 1min, between connected all pins
and heat sink plate
Fig. 1: TC MEASUREMENT POINT
Control terminals
18mm
18mm
Groove
IGBT chip position
FWDi chip position
Tc point
Heat sink side
Power terminals
THERMAL RESISTANCE
Symbol
Rth(j-c)Q
Rth(j-c)F
Parameter
Junction to case thermal
resistance
(Note 2)
Condition
Inverter IGBT part (per 1/6 module)
Inverter FWDi part (per 1/6 module)
Min.
-
Limits
Typ.
-
Max.
2.2
2.7
Unit
K/W
K/W
Note 2: Grease with good thermal conductivity and long-term endurance should be applied evenly with about +100μm~+200μm on the contacting surface of
DIPIPM and heat sink. The contacting thermal resistance between DIPIPM case and heat sink Rth(c-f) is determined by the thickness and the thermal
conductivity of the applied grease. For reference, Rth(c-f) is about 0.3K/W (per 1/6 module, grease thickness: 20μm, thermal conductivity: 1.0W/m•k).
Publication Date : March 2015
2
< Dual-In-Line Package Intelligent Power Module >
PSS05S72FT
TRANSFER MOLDING TYPE
INSULATED TYPE
ELECTRICAL CHARACTERISTICS (Tj = 25°C, unless otherwise noted)
INVERTER PART
Symbol
VCE(sat)
VEC
ton
tC(on)
toff
tC(off)
trr
ICES
Parameter
Condition
IC= 5A, Tj= 25°C
IC= 5A, Tj= 125°C
Collector-emitter saturation
voltage
VD=VDB = 15V, VIN= 5V
FWDi forward voltage
VIN= 0V, -IC= 5A
Switching times
VCC= 600V, VD= VDB= 15V
IC= 5A, Tj= 125°C, VIN= 0↔5V
Inductive Load (upper-lower arm)
Collector-emitter cut-off
current
VCE=VCES
Tj= 25°C
Tj= 125°C
Min.
1.10
-
Limits
Typ.
1.40
1.50
1.70
1.80
0.45
2.40
0.50
0.50
-
Max.
2.10
2.20
2.30
2.50
0.90
3.40
0.90
1
10
Min.
0.45
10.0
10.5
10.3
10.8
2.51
4.9
1.6
0.70
0.8
0.5
16
Limits
Typ.
0.48
2.64
2.4
1.00
0.9
20
Max.
6.00
6.00
0.55
0.55
0.51
12.0
12.5
12.5
13.0
2.76
0.95
1.50
3.5
1.3
24
Unit
V
V
μs
μs
μs
μs
μs
mA
CONTROL (PROTECTION) PART
Symbol
Parameter
Condition
ID
VD=15V, VIN=0V
VD=15V, VIN=5V
VD=VDB=15V, VIN=0V
VD=VDB=15V, VIN=5V
Total of VP1-VNC, VN1-VNC
Circuit current
Each part of VUFB- VUFS,
VVFB- VVFS, VWFB- VWFS
IDB
VSC(ref)
UVDBt
UVDBr
UVDt
UVDr
VOT
VFOH
VFOL
tFO
IIN
Vth(on)
Vth(off)
VF
R
Short circuit trip level
VD = 15V
P-side Control supply
under-voltage protection(UV)
N-side Control supply
under-voltage protection(UV)
Temperature Output
Fault output voltage
Fault output pulse width
Input current
ON threshold voltage
OFF threshold voltage
Bootstrap Di forward voltage
Built-in limiting resistance
(Note 3)
Trip level
Reset level
Trip level
Reset level
Tj ≤125°C
Pull down R=5.1kΩ, LVIC Temperature=85°C (Note 4)
VSC = 0V, FO terminal pulled up to 5V by 10kΩ
VSC = 1V, IFO = 1mA
(Note 5)
CFO=22nF
VIN = 5V
Applied between UP, VP, WP, UN, VN, WN-VNC
IF=10mA including voltage drop by limiting resistor
(Note 6)
Included in bootstrap Di
Unit
mA
V
V
V
V
V
V
V
V
ms
mA
V
V
Ω
Note 3 : SC protection works only for N-side IGBT. Please select the external shunt resistance such that the SC trip-level is less than 2.0 times of the current rating.
4 : DIPIPM don't shutdown IGBTs and output fault signal automatically when temperature rises excessively. When temperature exceeds the protective level that
user defined, controller (MCU) should stop the DIPIPM. Temperature of LVIC vs. VOT output characteristics is described in Fig. 3.
5 : Fault signal Fo outputs when SC or UV protection works. Fo pulse width is different for each protection modes. At SC failure, Fo pulse width is a fixed width
which is specified by the capacitor connected to CFO terminal. (CFO=9.1 x 10-6 x tFO [F]), but at UV failure, Fo outputs continuously until recovering from UV
state. (But minimum Fo pulse width is the specified time by CFO.)
6 : The characteristics of bootstrap Di is described in Fig.2.
Fig. 2 Characteristics of bootstrap Di VF-IF curve (@Ta=25°C) including voltage drop by limiting resistor (Right chart is enlarged chart.)
800
50
700
45
40
600
35
IF [mA]
IF [mA]
500
400
300
30
25
20
15
200
10
100
5
0
0
0
1
2
3
4
5
6
7 8 9 10 11 12 13 14 15
VF [V]
0.0
Publication Date : March 2015
3
0.2
0.4
0.6
0.8 1.0
VF [V]
1.2
1.4
1.6
1.8
< Dual-In-Line Package Intelligent Power Module >
PSS05S72FT
TRANSFER MOLDING TYPE
INSULATED TYPE
Fig. 3 Temperature of LVIC vs. VOT output characteristics
3.5
Max.
3.3
Typ.
Min.
3.1
2.9
VOT output (V)_
2.7
2.76
2.64
2.5
2.51
2.3
2.1
1.9
1.7
1.5
55
65
75
85
95
105
115
LVIC temperature (°C)
Fig. 4 VOT output circuit
Inside LVIC
of DIPIPM
Temperature
Signal
VOT
Ref
VNC
MCU
5.1kΩ
(1) It is recommended to insert 5.1kΩ pull down resistor for getting linear output characteristics at low temperature below room temperature.
When the pull down resistor is inserted between VOT and VNC(control GND), the extra circuit current, which is calculated approximately
by VOT output voltage divided by pull down resistance, flows as LVIC circuit current continuously. In the case of using VOT for detecting
high temperature over room temperature only, it is unnecessary to insert the pull down resistor.
(2) In the case of not using VOT, leave VOT output NC (No Connection).
Refer the application note for this product about the usage of VOT.
Publication Date : March 2015
4
< Dual-In-Line Package Intelligent Power Module >
PSS05S72FT
TRANSFER MOLDING TYPE
INSULATED TYPE
MECHANICAL CHARACTERISTICS AND RATINGS
Parameter
Condition
Mounting torque
Terminal pulling strength
Terminal bending strength
Mounting screw : M3 (Note 7)
Load 9.8N
Load 4.9N, 90deg. bend
Recommended 0.78N·m
EIAJ-ED-4701
EIAJ-ED-4701
Min.
0.59
10
2
Limits
Typ.
-
-
21
-
g
-50
-
100
μm
Weight
Heat-sink flatness
(Note 8)
Max.
0.98
-
Unit
N·m
s
times
Note 7: Plain washers (ISO 7089~7094) are recommended.
Note 8: Measurement point of heat sink flatness
12.78mm
Measurement position
-+
4.65mm
13.5mm
23mm
Heat sink side
+
-
Heat sink side
RECOMMENDED OPERATION CONDITIONS
Symbol
Parameter
VCC
VD
VDB
ΔVD, ΔVDB
tdead
fPWM
Supply voltage
Control supply voltage
Control supply voltage
Control supply variation
Arm shoot-through blocking time
PWM input frequency
IO
Allowable r.m.s. current
VNC
Tj
Limits
Typ.
600
15.0
15.0
-
Max.
800
16.5
18.5
+1
20
fPWM= 5kHz
-
-
2.7
fPWM= 15kHz
-
-
1.9
2.0
-
-
2.5
-
-
2.9
-
-
-5.0
-20
-
+5.0
+125
Applied between P-NU, NV, NW
Applied between VP1-VNC, VN1-VNC
Applied between VUFB-VUFS, VVFB-VVFS, VWFB-VWFS
For each input signal
TC ≤ 100°C, Tj ≤ 125°C
VCC = 600V, VD = 15V, P.F = 0.8,
Sinusoidal PWM
TC ≤ 100°C, Tj ≤ 125°C
(Note9)
PWIN(on)
PWIN(off)
Min.
350
13.5
13.0
-1
3.0
-
Condition
(Note 10)
Minimum input pulse width
VNC variation
Junction temperature
200V≤VCC≤350V,
Below rated current
13.5V≤VD≤16.5V,
13.0V≤VDB≤18.5V,
Between rated current
-20°C≤Tc≤100°C,
and 1.7 times of rated
N-line wiring inductance
current
less than 10nH (Note 11)
Between VNC-NU, NV, NW (including surge)
Unit
V
V
V
V/μs
μs
kHz
Arms
μs
V
°C
Note 9: Allowable r.m.s. current depends on the actual application conditions.
10: DIPIPM might not make response if the input signal pulse width is less than PWIN(on)
11: IPM might make delayed response or no response for the input signal with off pulse width less than PWIN(off). Please refer below about delayed response.
Delayed Response against Shorter Input Off Signal than PWIN(off) (P-side only)
P Side Control Input
Real line: off pulse width > PWIN(off); turn on time t1
Broken line: off pulse width < PWIN(off); turn on time t2
(t1:Normal switching time)
Internal IGBT Gate
Output Current Ic
t2
t1
Publication Date : March 2015
5
< Dual-In-Line Package Intelligent Power Module >
PSS05S72FT
TRANSFER MOLDING TYPE
INSULATED TYPE
Fig. 5 Timing Charts of The DIPIPM Protective Functions
[A] Short-Circuit Protection (N-side only with the external shunt resistor and RC filter)
a1. Normal operation: IGBT ON and outputs current.
a2. Short circuit current detection (SC trigger)
(It is recommended to set RC time constant 1.5~2.0μs so that IGBT shut down within 2.0μs when SC.)
a3. All N-side IGBT's gates are hard interrupted.
a4. All N-side IGBTs turn OFF.
a5. FO outputs. The pulse width of the Fo signal is set by the external capacitor CFO.
a6. Input = “L”: IGBT OFF
a7. Fo finishes output, but IGBTs don't turn on until inputting next ON signal (LH).
(IGBT of each phase can return to normal state by inputting ON signal to each phase.)
a8. Normal operation: IGBT ON and outputs current.
Lower-side control
input
a6
SET
RESET
Protection circuit state
a3
Internal IGBT gate
a4
SC trip current level
a8
Output current Ic
a1
a7
a2
SC reference voltage
Sense voltage of
the shunt resistor
Delay by RC filtering
Error output Fo
a5
[B] Under-Voltage Protection (N-side, UVD)
b1. Control supply voltage V D exceeds under voltage reset level (UVDr), but IGBT turns ON by next ON signal (LH).
(IGBT of each phase can return to normal state by inputting ON signal to each phase.)
b2. Normal operation: IGBT ON and outputs current.
b3. VD level drops to under voltage trip level. (UVDt).
b4. All N-side IGBTs turn OFF in spite of control input condition.
b5. Fo outputs for the period set by the capacitance CFO, but output is extended during VD keeps below UVDr.
b6. VD level reaches UVDr.
b7. Normal operation: IGBT ON and outputs current.
Control input
RESET
Protection circuit state
Control supply voltage VD
UVDr
SET
b1
UVDt
b2
b3
b4
Output current Ic
Error output Fo
b5
Publication Date : March 2015
6
RESET
b6
b7
< Dual-In-Line Package Intelligent Power Module >
PSS05S72FT
TRANSFER MOLDING TYPE
INSULATED TYPE
[C] Under-Voltage Protection (P-side, UVDB)
c1. Control supply voltage VDB rises. After the voltage reaches under voltage reset level UVDBr, IGBT turns on by next ON signal (LH).
c2. Normal operation: IGBT ON and outputs current.
c3. VDB level drops to under voltage trip level (UVDBt).
c4. IGBT of the correspond phase only turns OFF in spite of control input signal level, but there is no FO signal output.
c5. VDB level reaches UVDBr.
c6. Normal operation: IGBT ON and outputs current.
Control input
RESET
SET
RESET
Protection circuit state
UVDBr
Control supply voltage VDB
c3
c1
c5
UVDBt
c2
c4
c6
Output current Ic
Error output Fo
Keep High-level (no fault output)
Publication Date : March 2015
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< Dual-In-Line Package Intelligent Power Module >
PSS05S72FT
TRANSFER MOLDING TYPE
INSULATED TYPE
Fig. 6 Example of Application Circuit
P
VUFB(3)
+
IGBT1
Di1
VUFS(1)
C1 D1 C2
HVIC
VP1(4)
C2
U
UP(6)
VVFB(9)
+
IGBT2
Di2
VVFS(7)
C1 D1 C2
HVIC
VP1(10)
C2
V
VP(12)
VWFB(15)
IGBT3
+
M
Di3
VWFS(13)
C1 D1 C2
HVIC
VP1(16)
C2
W
MCU
W P(18)
+
Di4
IGBT4
C3
VOT(20)
5.1kΩ
UN(21)
NU
VN(22)
IGBT5
Di5
W N(23)
5V
NV
R2
LVIC
Fo(24)
IGBT6
Di6
CFO(25)
15V
VD
C1 + D1
NW
VN1(28)
C2
Long wiring here might
cause short circuit failure
VNC(27)
Long wiring here might cause SC
level fluctuation and malfunction.
CIN(26)
Long GND wiring here might
generate noise to input signal and
cause IGBT malfunction.
B
C4
C
D
R1
Shunt resistor
A
Control GND wiring N1 Power GND wiring
(1) If control GND is connected with power GND by common broad pattern, it may cause malfunction by power GND fluctuation.
It is recommended to connect control GND and power GND at only a point N1 (near the terminal of shunt resistor).
(2) It is recommended to insert a Zener diode D1(24V/1W) between each pair of control supply terminals to prevent surge destruction.
(3) To prevent surge destruction, the wiring between the smoothing capacitor and the P, N1 terminals should be as short as possible.
Generally a 0.1-0.22μF snubber capacitor C3 between the P-N1 terminals is recommended.
(4) R1, C4 of RC filter for preventing protection circuit malfunction is recommended to select tight tolerance, temp-compensated type.
The time constant R1C4 should be set so that SC current is shut down within 2μs. (1.5μs~2μs is recommended generally.) SC
interrupting time might vary with the wiring pattern, so the enough evaluation on the real system is necessary.
(5) To prevent malfunction, the wiring of A, B, C should be as short as possible.
(6) The point D at which the wiring to CIN filter is divided should be near the terminal of shunt resistor. NU, NV, NW terminals should be
connected at near NU, NV, NW terminals when it is used by one shunt operation. Low inductance SMD type with tight tolerance,
temp-compensated type is recommended for shunt resistor.
(7) All capacitors should be mounted as close to the terminals as possible. (C1: good temperature, frequency characteristic electrolytic
type and C2:0.22μ-2μF, good temperature, frequency and DC bias characteristic ceramic type are recommended.)
(8) Input logic is High-active. There is a 3.3kΩ(min.) pull-down resistor in the input circuit of IC. To prevent malfunction, the input wiring
should be as short as possible. When using RC coupling, make the input signal level meet the turn-on and turn-off threshold voltage.
(9) Fo output is open drain type. It should be pulled up to power supply of MCU (e.g. 5V,15V) by a resistor that makes IFo up to 1mA. (IFO
is estimated roughly by the formula of control power supply voltage divided by pull-up resistance. In the case of pulled up to 5V,
10kΩ (5kΩ or more) is recommended.)
-6
(10) Fo pulse width can be set by the capacitor connected to CFO terminal. CFO(F) = 9.1 x 10 x tFO (Required Fo pulse width).
(11) If high frequency noise superimposed to the control supply line, IC malfunction might happen and cause DIPIPM erroneous
operation. To avoid such problem, line ripple voltage should meet dV/dt ≤+/-1V/μs, Vripple≤2Vp-p.
(12) For DIPIPM, it isn't recommended to drive same load by parallel connection with other phase IGBT or other DIPIPM.
Publication Date : March 2015
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< Dual-In-Line Package Intelligent Power Module >
PSS05S72FT
TRANSFER MOLDING TYPE
INSULATED TYPE
Fig. 7 MCU I/O Interface Circuit
5V line
10kΩ
Note)
Design for input RC filter depends on PWM control scheme used
in the application and wiring impedance of the printed circuit board.
DIPIPM input signal interface integrates a minimum 3.3kΩ
pull-down resistor. Therefore, when inserting RC filter, it is
necessary to satisfy turn-on threshold voltage requirement.
Fo output is open drain type. It should be pulled up to control
power supply (e.g. 5V, 15V) with a resistor that makes Fo sink
current IFo 1mA or less. In the case of pulled up to 5V supply, 10kΩ
（5kΩ or more） is recommended.
DIPIPM
UP,VP,W P,UN,VN,W N
MCU
3.3kΩ(min)
Fo
VNC(Logic)
Fig. 8 Pattern Wiring Around the Shunt Resistor
NU, NV, NW should be connected
each other at near terminals.
DIPIPM
DIPIPM
Wiring Inductance should be less than 10nH.
Each wiring Inductance should be less than 10nH.
Inductance of a copper pattern with
length=17mm, width=3mm is about 10nH.
NU
NV
NW
VNC
Inductance of a copper pattern with
length=17mm, width=3mm is about 10nH.
N1
Shunt
resistor
NU
NV
NW
VNC
GND wiring from VNC should
be connected close to the
terminal of shunt resistor.
N1
Shunt
resistors
GND wiring from VNC should
be connected close to the
terminal of shunt resistor.
Low inductance shunt resistor like surface mounted (SMD) type is recommended.
Fig. 9 Pattern Wiring Around the Shunt Resistor (for the case of open emitter)
When DIPIPM is operated with three shunt resistors, voltage of each shunt resistor cannot be input to CIN terminal directly. In that case, it is necessary to use
the external protection circuit as below.
DIPIPM
Drive circuit
P
P-side IGBT
U
V
W
External protection circuit
Comparators
(Open collector output type)
N-side IGBT
Rf
C
Drive circuit
VNC
NW
NV
NU
Protection circuit
CIN
Cf
B
-
Vref
+
Vref
+
Vref
+
5V
D
Shunt
resistors
A
OR output
-
N1
(1) It is necessary to set the time constant RfCf of external comparator input so that IGBT stops within 2μs when short circuit occurs.
SC interrupting time might vary with the wiring pattern, comparator speed and so on.
(2) It is recommended for the threshold voltage Vref to set to the same rating of short circuit trip level (Vsc(ref): typ. 0.48V).
(3) Select the external shunt resistance so that SC trip-level is less than specified value (=2.0 times of rating current).
(4) To avoid malfunction, the wiring A, B, C should be as short as possible.
(5) The point D at which the wiring to comparator is divided should be close to the terminal of shunt resistor.
(6) OR output high level when protection works should be over 0.51V (=maximum Vsc(ref) rating).
(7) GND of Comparator, GND of Vref circuit and Cf should be not connected to power GND but to control GND wiring.
Publication Date : March 2015
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< Dual-In-Line Package Intelligent Power Module >
PSS05S72FT
TRANSFER MOLDING TYPE
INSULATED TYPE
Fig. 10 Package Outlines
Terminal of ( ) is the dummy terminal for internal use. This terminal should be kept NC (no connection).
Dimensions in mm
QR Code is registered trademark of DENSO WAVE INCORPORATED in JAPAN and other countries.
Publication Date : March 2015
10
< Dual-In-Line Package Intelligent Power Module >
PSS05S72FT
TRANSFER MOLDING TYPE
INSULATED TYPE
Revision Record
Rev.
Date
Page
1
13/ 3/2015
-
Revised contents
New
Publication Date : March 2015
11
< Dual-In-Line Package Intelligent Power Module >
PSS05S72FT
TRANSFER MOLDING TYPE
INSULATED TYPE
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more
reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors
may lead to personal injury, fire or property damage. Remember to give due consideration to safety when
making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
•These materials are intended as a reference to assist our customers in the selection of the Mitsubishi
semiconductor product best suited to the customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
•Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any
third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.
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Publication Date : March 2015
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