MITSUBISHI MITSUBISHI SEMICONDUCTOR SEMICONDUCTOR <Dual-In-Line <Dual-In-Line Package Package Intelligent Intelligent Power Power Module> Module> PS21767-V PS21767-V TRANSFER-MOLD TRANSFER-MOLD TYPE TYPE INSULATED INSULATED TYPE TYPE PS21767-V INTEGRATED POWER FUNCTIONS 600V/30A low-loss CSTBTTM inverter bridge with N-side three-phase output DC-to-AC power conversion INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS • • • • • For upper-leg IGBTS : Drive circuit, High voltage high-speed level shifting, Control supply under-voltage (UV) protection. For lower-leg IGBTS : Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC). Fault signaling : Corresponding to an SC fault (Lower-leg IGBT) or a UV fault (Lower-side supply). Input interface : 3, 5V line (High Active) UL Approved : Yellow Card No. E80276 APPLICATION AC100V~200V three-phase inverter drive for small power motor control. Fig. 1 PACKAGE OUTLINES A = 1.78 ±0.2 B = 4.32 ±0.2 2.04 ±0.3 B B B B B A A A A A D 34 35 36 37 0.5 6.6 ±0.3 7.62 ±0.3 7.62 ±0.3 7.62 ±0.3 7.62 ±0.3 3.3 ±0.3 3.3 ±0.3 2.2 17.7 38 TERMINAL CODE (1) 3.95 ±0.3 46 ±0.2 1.55 3.1 ±0.1 3.25 52.5 (0.6) (1) (φ3.5) φ3.3 0.5 1.5 (2.9) (1.6) (1) (1.75) 1 2 (0.75) 7.1 12.7 E HEAT SINK SIDE ) 33 (0°~ 5° 32 C (2.8) 31 15.5 C QR CODE 31 0.5 3.3 2-φ (13) Ty p e n a m e , L o t N o . 30 1.5 29 .6) TH2 DEP .2( 5-φ2 (12.78) 32 1 (13.5) 65 4 (3.5) 9 87 17.7 121110 (1.96) 151413 (1.7) (1.7) 2 (5.5) 28 27 26 25 24 23 22 21 2019 18 1716 (2.2) (2.2) F 5.6 35.9 ±0.5 (11×1.78) 1.78 ±0.2 Dimensions in mm (φ3.7) C-C DETAIL D Note: All outer lead terminals are with lead free solder (Sn-Cu) plating. DETAIL E 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 VUFS (UPG) VUFB VP1 (COM) UP VVFS (VPG) VVFB VP1 (COM) VP VWFS (WPG) VWFB VP1 (COM) WP (UNG) 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 VNO UN VN WN FO CFO CIN VNC VN1 (WNG) (VNG) NW NV NU W V U P NC Aug. 2007 1 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> PS21767-V TRANSFER-MOLD TYPE INSULATED TYPE MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted) INVERTER PART Symbol VCC VCC(surge) VCES ±IC ±ICP PC Tj Parameter Condition Applied between P-NU, NV, NW Supply voltage Supply voltage (surge) Collector-emitter voltage Each IGBT collector current Each IGBT collector current (peak) Collector dissipation Junction temperature Ratings 450 500 600 30 60 90.9 –20~+150 Unit V V V A A W °C Ratings Unit 20 V 20 V –0.5~VD+0.5 V –0.5~VD+0.5 1 –0.5~VD+0.5 V mA V Ratings Unit Applied between P-NU, NV, NW Tc = 25°C Tc = 25°C, less than 1ms Tc = 25°C, per 1 chip CONTROL (PROTECTION) PART Symbol VD Parameter Control supply voltage VDB Control supply voltage VIN Input voltage VFO Fault output supply voltage Fault output current Current sensing input voltage IFO VSC Condition Applied between VP1-VNC, VN1-VNC Applied between VUFB-VUFS, VVFB-VVFS, VWFB-VWFS Applied between UP, VP, WP, UN, VN, WNVNC Applied between FO-VNC Sink current at FO terminal Applied between CIN-VNC TOTAL SYSTEM Symbol Condition VD = 13.5~16.5V, Inverter part Tj = 125°C, non-repetitive, less than 2 µs (Note 1) Parameter Self protection supply voltage limit VCC(PROT) (short circuit protection capability) Module case operation temperature Tc Tstg Storage temperature Viso 60Hz, Sinusoidal, AC 1 minute, All pins to heat-sink plate Isolation voltage 400 V –20~+100 °C –40~+125 °C 2500 Vrms Note 1 : TC measurement point Control Terminals 18mm DIP-IPM 18mm Groove IGBT Chip position FWDi Chip position Tc point Heat sink side Power Terminals Aug. 2007 2 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> PS21767-V TRANSFER-MOLD TYPE INSULATED TYPE THERMAL RESISTANCE Symbol Rth(j-c)Q Rth(j-c)F Condition Parameter Junction to case thermal resistance (Note 2) Inverter IGBT part (per 1/6 module) Inverter FWD part (per 1/6 module) Min. — — Limits Typ. — — Max. 1.1 2.8 Unit °C/W °C/W Note 2 : Grease with good thermal conductivity should be applied evenly with about +100µm~+200µm on the contacting surface of DIP-IPM and heat-sink. The contacting thermal resistance between DIP-IPM case and heat sink (Rth(c-f)) is determined by the thickness and the thermal conductivity of the applied grease. For reference, Rth(c-f) (per 1/6 module) is about 0.3°C/W when the grease thickness is 20µm and the thermal conductivity is 1.0W/m·k ELECTRICAL CHARACTERISTICS (Tj = 25°C, unless otherwise noted) INVERTER PART Symbol VCE(sat) VEC ton trr tc(on) toff tc(off) ICES Condition Parameter Collector-emitter saturation voltage FWDi forward voltage VD = VDB = 15V IC = 30A, Tj = 25°C VIN = 5V IC = 30A, Tj = 125°C Tj = 25°C, –IC = 30A, VIN = 0V Switching times VCC = 300V, VD = VDB = 15V IC = 30A, Tj = 125°C, VIN = 0 ↔ 5V Inductive load (upper-lower arm) Collector-emitter cut-off current VCE = VCES Tj = 25°C Tj = 125°C Min. — — — Limits Typ. 0.70 — — — — — — 1.70 1.80 1.50 1.30 0.30 0.50 1.50 0.35 — — Max. 2.20 2.30 2.00 1.90 — 0.80 2.10 0.55 1 10 Min. — — — — 4.9 — 0.43 1.0 10.0 10.5 10.3 10.8 1.0 — 0.8 0.5 Limits Typ. — — — — — — 0.48 1.5 — — — — 1.8 2.3 1.4 0.9 Max. 7.00 0.55 7.00 0.55 — 0.95 0.53 2.0 12.0 12.5 12.5 13.0 — 2.6 — — Unit V V µs µs µs µs µs mA CONTROL (PROTECTION) PART Symbol ID Parameter Circuit current Condition VD = VDB = 15V Total of VP1-VNC, VN1-VNC VIN = 5V VUFB-VUFS, VVFB-VVFS, VWFB-VWFS VD = VDB = 15V Total of VP1-VNC, VN1-VNC VIN = 0V VUFB-VUFS, VVFB-VVFS, VWFB-VWFS VSC = 0V, FO terminal pull-up to 5V with 10kΩ VSC = 1V, IFO = 1mA Tj = 25°C, VD = 15V (Note 3) VIN = 5V Trip level Reset level Tj ≤ 125°C Trip level Reset level CFO = 22nF (Note 4) Unit mA mA mA mA V V V mA V V V V ms V V V VFOH Fault output voltage VFOL Short circuit trip level VSC(ref) Input current IIN UVDBt Control supply under-voltage UVDBr protection UVDt UVDr Fault output pulse width tFO ON threshold voltage Vth(on) Applied between UP, VP, WP, UN, VN, WN-VNC OFF threshold voltage Vth(off) ON/OFF threshold hysteresis voltage Vth(hys) Note 3 : Short circuit protection is functioning only at the low-arms. Please select the external shunt resistance such that the SC trip-level is less than 2.0 times of the current rating. 4 : Fault signal is output when the low-arms short circuit or control supply under-voltage protective functions works. The fault output pulsewidth tFO depends on the capacitance of CFO according to the following approximate equation : CFO = 12.2 ✕ 10-6 ✕ tFO [F]. Aug. 2007 3 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> PS21767-V TRANSFER-MOLD TYPE INSULATED TYPE MECHANICAL CHARACTERISTICS AND RATINGS Condition Parameter Mounting screw : M3 Mounting torque Weight Heat-sink flatness Recommended : 0.78 N·m (Note 5) Min. 0.59 — –50 Limits Typ. — 21 — Max. 0.98 — 100 Unit N·m g µm Note 5 : Flatness measurement position + – Measurement position 3mm Heat sink side – + Heat sink side RECOMMENDED OPERATION CONDITIONS Symbol Parameter VCC VD VDB ∆VD, ∆VDB tdead fPWM Supply voltage Control supply voltage Control supply voltage Control supply variation Arm shoot-through blocking time PWM input frequency IO Output r.m.s. current PWIN(on) Minimum input PWIN(off) pulse width Condition Applied between P-NU, NV, NW Applied between VP1-VNC, VN1-VNC Applied between VUFB-VUFS, VVFB-VVFS, VWFB-VWFS For each input signal, Tc ≤ 100°C Tc ≤ 100°C, Tj ≤ 125°C VCC = 300V, VD = VDB = 15V, fPWM = 5kHz P.F = 0.8, sinusoidal PWM fPWM = 15kHz Tc ≤ 100°C, Tj ≤ 125°C (Note 6) (Note 7) 200 ≤ VCC ≤ 350V, Below rated current 13.5 ≤ VD ≤ 16.5V, 13.0 ≤ VDB ≤ 18.5V, Between rated current and 1.7 times of rated current –20°C ≤ Tc ≤ 100°C, N-line wiring inductance less Between 1.7 times and than 10nH (Note 8) 2.0 times of rated current Recommended value Min. Typ. Max. Unit V V V V/µs µs kHz 0 13.5 13.0 –1 2 — 300 15.0 15.0 — — — 400 16.5 18.5 1 — 20 — — 21 — — 16 0.3 — — 1.6 — — 3.3 — — 3.9 — — Arms µs — VNC voltage variation 5.0 –5.0 V Between VNC-NU, NV, NW (including surge) — 125 –20 °C Junction temperature Note 6 : The allowable r.m.s. current value depends on the actual application conditions. 7 : Input signal with ON pulse width less than PWIN(on) might make no response. 8 : IPM might make delayed response (less than about 2µsec) or no response for the input signal with off pulse width less than PWIN(off). Please refer Fig. 2 about delayed response and Fig. 6 about N-line inductance. VNC Tj Aug. 2007 4 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> PS21767-V TRANSFER-MOLD TYPE INSULATED TYPE Fig. 2 ABOUT DELAYED RESPONSE AGAINST SHORTER INPUT OFF SIGNAL THAN PWIN (off) (P side only) P side control input Internal IGBT gate t2 Output current Ic t1 Real line ... off pulse width > PWIN(off) : turn on time t1 Broken line ... off pulse width < PWIN(off) : turn on time t2 Fig. 3 THE DIP-IPM INTERNAL CIRCUIT DIP-IPM VUFB VUFS VP1 UP P HVIC1 VB VCC IGBT1 Di1 HO IN VS COM U VVFB VVFS VP1 VP HVIC2 VB VCC IGBT2 Di2 HO IN VS COM V VWFB VWFS VP1 VP HVIC3 VB VCC IGBT3 Di3 HO IN COM VS W IGBT4 LVIC Di4 UOUT VN1 NU VCC IGBT5 Fo Fo UN UN VN VN WN WN Di5 VOUT NV IGBT6 Di6 WOUT NW VNO CIN VNC GND VNO CFO CFO CIN Aug. 2007 5 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> PS21767-V TRANSFER-MOLD TYPE INSULATED TYPE Fig. 4 TIMING CHARTS OF THE DIP-IPM PROTECTIVE FUNCTIONS [A] Short-Circuit Protection (Lower-arms only with the external shunt resistor and CR filter) a1. Normal operation : IGBT ON and carrying current. a2. Short circuit current detection (SC trigger). a3. IGBT gate hard interruption. a4. IGBT turns OFF. a5. FO timer operation starts : The pulse width of the FO signal is set by the external capacitor CFO. a6. Input “L” : IGBT OFF. a7. Input “H” a8. IGBT OFF state in spite of input “H”. Lower-arms control input a6 a7 Protection circuit state SET Internal IGBT gate RESET a3 a2 a1 SC a4 Output current Ic a8 SC reference voltage Sense voltage of the shunt resistor CR circuit time constant DELAY Fault output Fo a5 [B] Under-Voltage Protection (Lower-arm, UVD) b1. Control supply voltage rising : After the voltage level reaches UVDr, the circuits start to operate when next input is applied. b2. Normal operation : IGBT ON and carrying current. b3. Under voltage trip (UVDt). b4. IGBT turns OFF in spite of control input condition. b5. FO operation starts. b6. Under voltage reset (UVDr). b7. Normal operation : IGBT ON and carrying current. Control input Protection circuit state Control supply voltage VD RESET UVDr b1 SET UVDt b2 RESET b6 b3 b4 b7 Output current Ic Fault output Fo b5 Aug. 2007 6 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> PS21767-V TRANSFER-MOLD TYPE INSULATED TYPE [C] Under-Voltage Protection (Upper-arm, UVDB) c1. Control supply voltage rises : After the voltage level reaches UVDBr, the circuits start to operate. c2. Protection circuit state reset : IGBT ON and carrying current. c3. Normal operation : IGBT ON and carrying current. c4. Under-voltage trip (UVDBt). c5. IGBT OFF inspite of control input condition, but there is no FO signal output. c6. Under-voltage reset (UVDBr). c7. Normal operation : IGBT ON and carrying current. Control input Protection circuit state RESET Control supply voltage VDB SET RESET UVDBr c1 UVDBt c4 c2 c3 c5 c6 c7 Output current Ic High-level (no fault output) Fault output Fo Fig. 5 RECOMMENDED MCU I/O INTERFACE CIRCUIT 5V line DIP-IPM 10kΩ UP,VP,WP,UN,VN,WN MCU Fo VNC(Logic) Note : RC coupling at each input (parts shown dotted) may change depending on the PWM control scheme used in the application and the wiring impedance of the application’s printed circuit board. The DIP-IPM input signal section integrates a 2.5kΩ(min) pull-down resistor. Therefore, when using a external filtering resistor, care must be taken to satisfy the turn-on threshold voltage requirement. Fig. 6 RECOMMENDED WIRING AROUND THE SHUNT RESISTOR DIP-IPM Each wiring inductance should be less than 10nH Equivalent to the inductance of a copper pattern in dimension of width=3mm, thickness=100µm, length=17mm VNC VNO NU NV NW Shunt resistor The GND wiring from VNO, VNC should be as close to the shunt resistors as possible Aug. 2007 7 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> PS21767-V TRANSFER-MOLD TYPE INSULATED TYPE Fig. 7 TYPICAL DIP-IPM APPLICATION CIRCUIT EXAMPLE C1: Tight tolerance temp-compensated electrolytic type C2 VUFB C1 VUFS C2,C3: 0.22~2µF R-category ceramic capacitor for noise filtering DIP-IPM P HVIC1 VP1 VCC C3 UP IN HO COM C2 VVFB C1 VVFS VP1 C3 VB U VS HVIC2 VCC VB VP HO IN COM C2 C1 M VWFS HVIC3 VP1 CONTROLLER C3 V VS VWFB VCC VB WP IN HO COM W VS LVIC UOUT NU VN1 VCC C3 5V line VOUT NV UN VN WN Fo VNC UN VN WOUT C WN Fo NW CIN Too long wiring here might cause short-circuit. CFO GND VNO VNO CFO C4(CFO ) CIN If this wiring is too long, the SC level fluctuation might be larger and cause SC malfunction. 15V line Shunt resistors A B R1 + - Long GND wiring here might generate noise to input and cause IGBT malfunction. Vref B R1 + OR Logic Vref C5 B R1 + - N1 C5 Vref Comparator C5 External protection circuit Note 1 : Input drive is High-active type. There is a 2.5kΩ(Min.) pull-down resistor integrated in the IC input circuit. To prevent malfunction, the wiring of each input should be as short as possible. When using RC coupling circuit, make sure the input signal level meet the turn-on and turn-off threshold voltage. 2 : Thanks to HVIC inside the module, direct coupling to MCU without any opto-coupler or transformer isolation is possible. 3 : FO output is open drain type. It should be pulled up to the positive side of a 5V power supply by a resistor of about 10kΩ. FO output pulse width is determined by the external capacitor (CFO) between CFO and VNC terminals (e.g CFO = 22nF → tFO = 1.8ms (typ.)) 4 : To prevent erroneous protection, the wiring of A, B should be as short as possible. 5 : The time constant R1C5 of the protection circuit should be selected in the range of 1.5-2µs. SC interrupting time might vary with the wiring pattern. Tight tolerance, temp-compensated type is recommended for R1, C5. 6 : All capacitors should be mounted as close to the terminals of the DIP-IPM as possible. (C1: good temperature, frequency characteristic electrolytic type, and C2, C3: good temperature, frequency and DC bias characteristic ceramic type are recommended.) 7 : To prevent surge destruction, the wiring between the smoothing capacitor and the P, N1 terminals should be as short as possible. Generally a 0.1-0.22µF snubber between the P-N1 terminals is recommended. 8 : It is recommended to insert a Zener diode (24V/1W) between each pair of control supply terminals to prevent surge destruction. 9 : If control GND is connected to power GND by broad pattern, it may cause malfunction by power GND fluctuation. It is recommended to connect control GND and power GND at only a point. 10 : The reference voltage Vref of comparator should be set up the same rating of short circuit trip level (Vsc(ref): min.0.43V to max.0.53V). 11 : OR logic output high level should exceed the maximum short circuit trip level (Vsc(ref): max.0.53V). Aug. 2007 8