600V LARGE DIPIPM Ver.4 Series APPLICATION - Efo

<Dual-In-Line Package Intelligent Power Module>
600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
PS21A79 / PS21A7A
Table of contents
CHAPTER 1 INTRODUCTION .............................................................................................................................2
1.1 Target Applications ................................................................................................................................................. 2
1.2 Product Line-up ...................................................................................................................................................... 2
1.3 Functions and Features ......................................................................................................................................... 2
1.4 The differences of previous series (Large DIPIPM Ver.3 PS2186X) and this series .............................................. 3
CHAPTER2 SPECIFICATIONS AND CHARACTERISTICS ................................................................................4
2.1 Specifications ......................................................................................................................................................... 4
2.1.1 Maximum Ratings .................................................................................................................................................................................................... 4
2.1.2 Thermal Resistance ................................................................................................................................................................................................. 5
2.1.3 Electric Characteristics (Power Part) ....................................................................................................................................................................... 5
2.1.4 Electric Characteristics (Control Part) ..................................................................................................................................................................... 6
2.1.5 Recommended Operating Conditions ..................................................................................................................................................................... 7
2.1.6 Mechanical Characteristics and Ratings ................................................................................................................................................................. 8
2.2 Protective Functions and Operating Sequence ...................................................................................................... 9
2.2.1 Short Circuit Protection ............................................................................................................................................................................................ 9
2.2.2 Control Supply UV Protection ................................................................................................................................................................................ 12
2.2.3 Temperature analog output .................................................................................................................................................................................... 13
2.3 Package Outlines ................................................................................................................................................. 16
2.3.1 Outline Drawing ..................................................................................................................................................................................................... 16
2.3.2 Power Chip Position .............................................................................................................................................................................................. 17
2.3.3 Laser Marking Position .......................................................................................................................................................................................... 17
2.3.4 Terminal Description .............................................................................................................................................................................................. 18
2.4 Mounting Method ................................................................................................................................................. 20
2.4.1 Electric Spacing ..................................................................................................................................................................................................... 20
2.4.2 Mounting Method and Precautions ........................................................................................................................................................................ 20
2.4.3 Soldering Conditions .............................................................................................................................................................................................. 21
CHAPTER3 SYSTEM APPLICATION HIGHLIGHT ...........................................................................................22
3.1 Application Guidance ........................................................................................................................................... 22
3.1.1 System connection ................................................................................................................................................................................................ 22
3.1.2 Interface Circuit (Direct Coupling Interface example) ........................................................................................................................................... 23
3.1.3 Interface Circuit (Opto-coupler Isolated Interface) ................................................................................................................................................ 24
3.1.4 Circuits of Signal Input terminals and Fo Terminal ................................................................................................................................................ 25
3.1.5 Snubber Circuit ...................................................................................................................................................................................................... 27
3.1.6 Influence of wiring .................................................................................................................................................................................................. 28
3.1.7 Precaution for wiring on PCB ................................................................................................................................................................................ 29
3.1.8 SOA of DIPIPM ...................................................................................................................................................................................................... 30
3.1.9 SCSOA .................................................................................................................................................................................................................. 30
3.1.10 Power Life Cycles ................................................................................................................................................................................................ 32
3.2 Power Loss and Thermal Dissipation Calculation ................................................................................................ 33
3.2.1 Power Loss Calculation ......................................................................................................................................................................................... 33
3.2.2 Temperature Rise Considerations and Calculation Example ................................................................................................................................ 35
3.3 Noise Withstand Capability .................................................................................................................................. 36
3.3.1 Evaluation Circuit ................................................................................................................................................................................................... 36
3.3.2 Countermeasures and Precautions ....................................................................................................................................................................... 36
3.3.3 Static Electricity Withstand Capability.................................................................................................................................................................... 37
CHAPTER 4 Bootstrap Circuit Operation ...........................................................................................................38
4.1 Bootstrap Circuit Operation .................................................................................................................................. 38
4.2 Bootstrap Supply Circuit Current at Switching State ............................................................................................ 39
4.3 Note for designing the bootstrap circuit ................................................................................................................ 39
CHAPTER5 PACKAGE HANDLING...................................................................................................................41
5.1 Packaging Specification ....................................................................................................................................... 41
5.2 Handling Precautions ........................................................................................................................................... 42
Publication Date : October 2012
1
<Dual-In-Line Package Intelligent Power Module>
600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
CHAPTER 1 INTRODUCTION
1.1 Target Applications
Motor drives for industrial use, such as packaged air conditioners, general-purpose inverter, servo,
except for automotive applications.
1.2 Product Line-up
Table 1-1. Line-up
Type Name
IGBT Rating
Motor Rating
(Note 1)
Isolation Voltage
Viso = 2500Vrms
PS21A79
50A/600V
3.7kW/220VAC
(Sine 60Hz, 1min
PS21A7A
75A/600V
5.5kW/220VAC
All shorted pins-heat sink)
Note 1: These motor ratings are general ratings, so those may be changed by conditions.
1.3 Functions and Features
Large DIPIPM Ver.4 is a compact intelligent power module with transfer mold package favorable for larger mass
production. Power chips, drive and protection circuits are integrated in the module, which makes it easy for
AC100-200V class low power motor inverter control. Fig.1-1, Fig.1-2 and Fig.1-3 show the outline photograph,
internal cross-section structure and the circuit block diagram respectively.
One of the most important features of Large DIPIPM Ver.4 is that it realized higher thermal dissipation by
incorporating thermal structure with high thermal conductive insulated sheet, so that the chip shrink became possible
and achieved higher current rating up to 75A than previous Large DIPIPM Ver.3 series despite almost same package
size.
Copper flame
Aluminum
wire
FWDi
IGBT
Gold wire
IC
Aluminum
heat sink
Fig.1-1 Package photograph
Insulated thermal
dissipation sheet
Mold resin
Fig.1-2 Internal cross-section structure
Publication Date : October 2012
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<Dual-In-Line Package Intelligent Power Module>
600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
Features:
VUFB
•
VUFS
For P-side IGBTs
-Drive circuit
-High voltage level shift circuit
-Control supply under voltage (UV)
protection circuit (without fault signal output)
UP
Di1
Ho
U
For N-side IGBTs
-Drive circuit
-Short circuit (SC) protection circuit (by using
external current detecting resistor)
-Control supply under voltage (UV)
protection circuit (with fault signal output)
-Analog output of LVIC temperature
HVIC2
IGBT2
VP1
VP
Di2
Ho
V
VWFB
VWFS
HVIC3
VP1
WP
•
IGBT1
VVFB
VVFS
•
P
HVIC1
VP1
Fault Signal Output
-Corresponding to SC protection and
N-side UV protection
IGBT3
Di3
Ho
VPC
W
LVIC
IGBT4
Di4
UOUT
•
•
•
IGBT Drive Supply
-Single DC15V power supply
NU
VN1
IGBT5
Di5
VOUT
Control Input Interface
-High active logic
NV
UN
VN
UL recognized
UL1557 File E80276
IGBT6
Di6
W OUT
WN
NW
Fo
VOT
VNC
CFO
CIN Vsc
Fig.1-3 Internal circuit schematic
1.4 The differences of previous series (Large DIPIPM Ver.3 PS2186X) and this series
(1) Enlargement of maximum current rating to 75A
Due to change its insulation structure from mold resin insulation to insulated thermal dissipation sheet, it
became possible to decrease the thermal resistance between junction and case Rth(j-c) substantially. So that
despite almost same package size, it realized higher current rating up to 75A than previous Large DIPIPM Ver.3
series.
(2) Changing the method of short circuit protection (SC)
In the previous series the shunt resistor was inserted between N terminal and power GND line for detecting short
circuit current. But the loss at the resistor escalates with increasing current rating, so high wattage type resistor is
needed. In this series, the current detection method was changed to the one of detecting slight sense current divided
from main current by using on-chip current sense IGBTs. So that the shunt resistor inserted to main flow path for SC
protection is unnecessary. For more detail, refer Section 2.2.1.
(3) Analog output function of LVIC temperature
This function measures the temperature of control LVIC by built in temperature detecting circuit on LVIC and
output it by analog signal. But the heat generated at IGBT and FWDi transfers to LVIC through the mold package
and the inner and outer heat sink. So that LVIC temperature cannot respond to rapid temperature change of
those power chips effectively. (e.g. motor lock, short current)
It is able to replace the thermistor which was set on outer heat sink with this function. For more detail, refer
Section 2.2.3.
(4) Terminal layout
Because of above (2), (3) functions addition and divided N-side IGBT emitter, the terminal layout was
changed from Large DIPIPM Ver.3 series.
For more detail, refer Section 2.3.
Publication Date : October 2012
3
<Dual-In-Line Package Intelligent Power Module>
600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
CHAPTER2 SPECIFICATIONS AND CHARACTERISTICS
2.1 Specifications
The specifications are described below by using PS21A7A (75A/600V) as an example. Please refer to respective
datasheet for the detailed description of other types.
2.1.1 Maximum Ratings
The maximum ratings of PS21A7A are shown in Table 2-1.
Table 2-1 Maximum Ratings of PS21A7A
MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted)
INVERTER PART
Symbol
Parameter
Condition
VCC
Supply voltage
Applied between P-NU,NV,NW
VCC(surge)
Supply voltage (surge)
Applied between P-NU,NV,NW
VCES
Collector-emitter voltage
±IC
Each IGBT collector current
TC= 25°C
±ICP
Each IGBT collector current (peak)
TC= 25°C, up to 1ms
PC
Collector dissipation
TC= 25°C, per 1 chip
Tj
Junction temperature
CONTROL (PROTECTION) PART
Symbol
Parameter
VD
Control supply voltage
VDB
Control supply voltage
VIN
Input voltage
VFO
Fault output supply voltage
IFO
Fault output current
VSC
Current sensing input voltage
TOTAL SYSTEM
Symbol
Parameter
Self protection supply voltage limit
VCC(PROT)
(Short circuit protection capability)
TC
Module case operation temperature
Tstg
Storage temperature
Viso
Isolation voltage
Condition
Applied between VP1-VPC, VN1-VNC
Applied between VUFB-VUFS, VVFB-VVFS, VWFB-VWFS
Applied between UP, VP, WP-VPC, UN, VN, WN-VNC
Applied between FO-VNC
Sink current at FO terminal
Applied between CIN-VNC
Condition
VD = 13.5~16.5V, Inverter Part
Tj = 125°C, non-repetitive, up to 2μs
(Note 1)
60Hz, Sinusoidal, AC 1min, between connected all
pins and heat sink plate
Ratings
450
500
600
75
150
162
-20~+150
Unit
V
V
V
A
A
W
°C
Ratings
20
20
-0.5~VD+0.5
-0.5~VD+0.5
1
-0.5~VD+0.5
Unit
V
V
V
V
mA
V
Ratings
Unit
800
V
-20~+100
-40~+125
°C
°C
2500
Vrms
(1)
(2)
(3)
(4)
(5)
(6)
Note 1: Tc measurement point
(Under the UN-IGBT)
(7)
Tc measuring point
[Item explanation]
(1) Vcc
The maximum P-N voltage in no switching state. A voltage suppressing circuit such as a brake circuit is
necessary if the voltage exceeds this value.
(2) Vcc(surge) The maximum P-N surge voltage in switching state. A snubber circuit is necessary if the voltage exceeds
Vcc(surge).
The maximum sustained collector-emitter voltage of built-in IGBT.
(3) VCES
(4) ±IC
The allowable DC current continuously flowing at collect electrode (@Tc=25°C)
(5) Tj
The maximum junction temperature rating is 150°C.But for safe operation, it is recommended to limit the average
junction temperature up to 125°C. Repetive temperature variation ΔTj affects the life time of power cycle, so refer
life time curves (Section 3.1.10) for safety design.
(6) Vcc(prot)
The maximum supply voltage for IGBT turning off safely in case of an SC fault. The power chip might be damaged if
supply voltage exceeds this rating.
(7) Tc position Tc (case temperature) is defined to be the temperature just underneath the specified power chip. Please mount a
thermocouple on the heat sink surface at the defined position to get accurate temperature information. Due to the
control schemes such different control between P and N-side, there is the possibility that highest Tc point is different
from above point. In such cases, it is necessary to change the measuring point to that under the highest power
chip.
Publication Date : October 2012
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<Dual-In-Line Package Intelligent Power Module>
600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
2.1.2 Thermal Resistance
Table 2-2 shows the thermal resistance of PS21A7A.
Table 2-2 Thermal resistance of PS21A7A
THERMAL RESISTANCE
Symbol
Rth(j-c)Q
Rth(j-c)F
Parameter
Junction to case thermal
resistance
(Note 2)
Condition
Min.
-
Inverter IGBT part (per 1/6 module)
Inverter FWDi part (per 1/6 module)
Limits
Typ.
-
Max.
0.77
1.25
Unit
K/W
K/W
Note 2: Grease with good thermal conductivity and long-term endurance should be applied evenly with about +100μm~+200μm on the contacting surface of
DIPIPM and heat sink. The contacting thermal resistance between DIPIPM case and heat sink Rth(c-f) is determined by the thickness and the
thermal conductivity of the applied grease. For reference, Rth(c-f) is about 0.2K/W (per 1/6 module, grease thickness: 20μm, thermal conductivity:
1.0W/m•k).
The above data shows the thermal resistance between chip junction and case at steady state. The thermal
resistance goes into saturation in about 10 seconds. The thermal resistance under 10sec is called as transient
thermal impedance which is shown in Fig.2-1. Zth(j-c)* is the normalized value of the transient thermal impedance.
(Zth(j-c)*= Zth(j-c) / Rth(j-c)max) For example, the IGBT transient thermal impedance of PS21A7A in 0.1s is
0.77×0.53=0.41K/W.
The transient thermal impedance isn’t used for constantly current, but for short period current (ms order).
(E.g. In the cases at motor starting, at motor lock･･･)
Thermal impedance Zth(j-c)*
1.00
0.10
0.01
0.001
0.01
0.1
1
10
Time (s)
Fig.2-1 Typical transient thermal impedance
2.1.3 Electric Characteristics (Power Part)
Table 2-3 shows the typical static characteristics and switching characteristics of PS21A7A.
Table 2-3. Static characteristics and switching characteristics of PS21A7A
Inverter Part
Symbol
VCE(sat)
VEC
ton
tC(on)
toff
tC(off)
trr
ICES
Parameter
Tj= 25°C
Min.
1.80
-
Limits
Typ.
1.55
1.65
1.70
2.40
0.40
3.40
0.60
0.30
-
Max.
2.05
2.10
2.20
3.60
0.60
4.80
1.20
1
Tj= 125°C
-
-
10
Condition
Tj= 25°C
Tj= 125°C
Collector-emitter saturation
voltage
VD=VDB = 15V
VIN= 5V, IC= 75A
FWDi forward voltage
-IC= 75A, VIN= 0V
Switching times
VCC= 300V, VD= VDB= 15V
IC= 75A, Tj= 125°C, VIN= 0↔5 V
Inductive Load (upper-lower arm)
Collector-emitter cut-off
current
VCE=VCES
Switching time definition and performance test method are shown in Fig.2-2 and 2-3.
Publication Date : October 2012
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Unit
V
V
μs
μs
μs
μs
μs
mA
<Dual-In-Line Package Intelligent Power Module>
600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
trr
VCE
Irr
P-Side IGBT
Ic
VP1
90%
90%
VB
L
VCIN(P)
IN
COM
OUT
VS
A
P-Side Input Signal
VCC
10%
10%
10%
tc(on)
B
10%
VD
tc(off)
VCIN(N)
VCIN
td(on)
VN1
OUT
IN
VNC
tr
td(off)
( ton=td(on)+tr )
tf
L
VNO
CIN
N-Side IGBT
N-Side Input Signal
( toff=td(off)+tf )
Fig.2-2 Switching time definition
Fig.2-3 Evaluation circuit (inductive load)
Short A for N-side IGBT, and short B for P-side IGBT evaluation
Turn on
t:200ns/div
t:200ns/div
Turn off
VCE(100V/div)
Ic(20A/div)
VCE(100V/div)
Ic(20A/div)
Fig.2-4 Typical switching waveform (PS21A7A)
Conditions: VCC=300V, VD=VDB=15V, Tj=125°C, Ic=75A, Inductive load half-bridge circuit
2.1.4 Electric Characteristics (Control Part)
Table 2-4 Control (Protection) characteristics of PS21A7A
CONTROL (PROTECTION) PART
Symbol
Parameter
ID
Circuit current
IDB
Circuit current
ISC
Short circuit trip level
UVDBt
UVDBr
UVDt
UVDr
Control supply under-voltage
protection
VFOH
VFOL
tFO
IIN
Vth(on)
Vth(off)
VOT
Fault output voltage
Fault output pulse width
Input current
ON threshold voltage
OFF threshold voltage
Temperature output
Condition
Min.
-
Limits
Typ.
-
Max.
5.50
5.50
0.55
0.55
Unit
VD = 15V, VIN = 0V
VD = 15V, VIN = 5V
VD = VDB = 15V, VIN = 0V
VUFB-VUFS, VVFB-VVFS,
VWFB-VWFS
VD = VDB = 15V, VIN = 5V
-20°C≤Tj≤125°C, Rs= 23.2Ω (±1%),
Not connecting outer shunt resistors to
(Note 3)
NU,NV,NW terminals
Trip level
P-side
Reset level
Tj ≤125°C
Trip level
N-side
Reset level
127
-
-
A
10.0
10.5
10.3
10.8
-
12.0
12.5
12.5
13.0
V
V
V
V
VSC = 0V, FO terminal pull-up to 5V by 10kΩ
4.9
-
-
V
VSC = 1V, IFO = 1mA
CFO=22nF
VIN = 5V
1.6
0.7
2.1
0.8
3.57
2.4
1.0
2.3
1.4
3.63
0.95
1.5
2.6
2.1
3.69
V
ms
mA
V
V
V
Total of VP1-VPC, VN1-VNC
(Note 4)
Applied between UP, VP, WP-VPC, UN, VN, WN-VNC
LVIC temperature = 85°C
(Note 5)
mA
Note 3 : Short circuit protection can work for N-side IGBTs only. Isc level can change by sense resistance. For details, please refer the application note for this
DIPIPM or contact us. And in that case, it should be for sense resistor to be larger resistance than the value mentioned above.
Note 4 : Fault signal is output when short circuit or N-side control supply under-voltage protective functions operate. The fault output pulse-width tFO depends on the
capacitance value of CFO. (CFO (typ.) = tFO x (9.1 x 10-6) [F])
Note 5 : DIPIPM don't shutdown IGBTs and output fault signal automatically when temperature rises excessively. When temperature exceeds the protective level that
user defined, controller (MCU) should stop the DIPIPM. And this output might exceed 5V when temperature rises excessively, so it is recommended for
protection of control part like MCU to insert a clamp Di between supply (e.g. 5V) for control part and this output.
Publication Date : October 2012
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600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
2.1.5 Recommended Operating Conditions
The recommended operating conditions of PS21A7A are given in Table 2-5.Although these conditions are the
recommended but not the necessary ones, it is highly recommended to operate the modules within these
conditions so as to ensure DIPIPM safe operation.
Table 2-5 Recommended operating conditions of PS21A7A
RECOMMENDED OPERATION CONDITIONS
Symbol
Parameter
VCC
VD
VDB
ΔVD, ΔVDB
tdead
fPWM
Supply voltage
Control supply voltage
Control supply voltage
Control supply variation
Arm shoot-through blocking time
PWM input frequency
IO
Allowable r.m.s. current
PWIN(on)
PWIN(off)
VNC
Tj
Minimum input pulse width
VNC variation
Junction temperature
Min.
0
13.5
13.0
-1
2.7
-
Limits
Typ.
300
15.0
15.0
-
Max.
400
16.5
18.5
+1
20
fPWM= 5kHz
-
-
35.0
fPWM= 15kHz
-
-
17.0
1.3
3.0
-
-
5.0
-
-
-5.0
-20
-
+5.0
+125
Condition
Applied between P-NU, NV, NW
Applied between VP1-VPC, VN1-VNC
Applied between VUFB-VUFS, VVFB-VVFS, VWFB-VWFS
For each input signal, TC ≤ 100°C
TC ≤ 100°C, Tj ≤ 125°C
VCC = 300V, VD = 15V, P.F = 0.8,
Sinusoidal PWM
TC ≤ 100°C, Tj ≤ 125°C
(Note 7)
(Note 8)
200≤ VCC ≤ 350V, 13.5≤ VD ≤ 16.5V,
IC≤75A
13.0≤ VDB ≤ 18.5V, -20°C ≤ TC ≤ 100°C,
N line wiring inductance less than 10nH 75<IC≤127.5A
(Note 9)
Between VNC-NU, NV, NW (including surge)
P Side Control Input
Internal IGBT Gate
Output Current Ic
t2
t1
Real line: off pulse width>PWIN(off); turn on time t1
Broken line: off pulse width<PWIN(off); turn on time t2
(t1:Normal switching time)
Publication Date : October 2012
7
V
V
V
V/μs
μs
kHz
Arms
Note 7: The allowable r.m.s. current value depends on the actual application conditions.
8: DIPIPM might not make response to the input on signal with pulse width less than PWIN (on).
9: DIPIPM might make no response or delayed response (P-side IGBT only) for the input signal with off pulse width less than PWIN(off).
Refer below about delayed response.
Delayed Response Against Shorter Input Off Signal Than PWIN(off) (P-side only)
Unit
μs
V
°C
<Dual-In-Line Package Intelligent Power Module>
600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
2.1.6 Mechanical Characteristics and Ratings
The mechanical characteristics and ratings are shown in Table 2-6
Please refer to Section 2.4 for the detailed mounting instruction.
Table 2-6
Mechanical characteristics and ratings of PS21A7A
MECHANICAL CHARACTERISTICS AND RATINGS
Parameter
Mounting torque
Terminal pulling strength
Terminal bending strength
Condition
Mounting screw : M4
Load 19.6N
Load 9.8N, 90deg. bend
Recommended 1.18N·m
EIAJ-ED-4701
EIAJ-ED-4701
Weight
Heat-sink flatness
Measurement point of heat-sink flatness
Publication Date : October 2012
8
Min.
0.98
10
2
Limits
Typ.
1.18
-
-
46
-
g
-50
-
100
μm
Max.
1.47
-
Unit
N·m
s
times
<Dual-In-Line Package Intelligent Power Module>
600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
2.2 Protective Functions and Operating Sequence
There are SC protection, UV protection and outputting LVIC temperature function in the large DIPIPM Ver.4.
The detailed information are described below.
2.2.1 Short Circuit Protection
In large DIPIPM Ver.4 series, the method of SC protection is different from DIPIPM Ver.3 series, which detects
main current by shunt resistor inserted into main current path. It detects much smaller sense current, which is split
at N-side IGBT, by measuring the potential of sense resistor connected to Vsc terminal. So high wattage type shunt
resistor isn't necessary for SC protection, and the loss at shunt resistor can be reduced. (Fig.2-5)
IGBT4
Di4
VN1
NU
IGBT5
LVIC
UN
Di5
NV
IGBT6
Di6
VN
WN
NW
FO
VOT
Sense
current
Main
current
VNC
CFO
CIN
Capacitor for setting
FO pulse width
Vsc
Sense
Resistor Rs
RC filter for noise cancelling
Recommended time constant: 1.5-2.0μs
Wattage: over 1/8W and tolerance:
within 1% are recommended.
*) This wattage of sense resistor is described as a guide, so it is recommended to evaluate on your real system well.
Fig.2-5 SC protection circuit
SC protection works by inputting the potential, which is generated by sense current flowing into the sense resistor,
to the CIN terminal. When SC ptotection works, DIPIPM shuts down all N-side IGBTs hardly and outputs Fo signal.
-6
(Its pulse width(tFo) is set by CFO capacitor. CFO = tFO x 9.1 x 10 [F]) Tabel 2-7 describes specified sense resistance
and minimum SC protection current in that case for each products.
To prvent malfunction, it is recommended to insert RC filter before inputting to CIN terminal and set the time constant
to shut down withiin 2μs when short circuit occurs. ( Time constant 1.5μ-2.0μs is recommended.) Also it is necessary
to set the resistance of RC filter to ten or more times of the sense resistor Rs.(Hundred times is recommended.)
Table 2-7 SC protection trip level (Condition: Tj=-20°C~125°C, Not connecting outer shunt resistors to NU,NV,NW terminals.)
Rs
Min.
PS21A7A
23.2Ω
127A
PS21A79
40.2Ω
85A
Sense resistance is set to 23.2Ω for PS21A7A and 40.2Ωfor PS21A79 without outer shut resistors into main current
path. For sense resistor, its large fluctuation leads to large fluctuation of SC trip level. So it is necessary to select small
variation in the resistance (within +/-1% is recommended)
Wattage of the sense resistor can be estimated in view of the fact that the maximum split ratio between the main and
sense currents is about 3000:1 for PS21A7A and PS21A79. (In this case maximum sense current flows.)
The estimation example for PS21A7A is described as below.
Publication Date : October 2012
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<Dual-In-Line Package Intelligent Power Module>
600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
[Estimation example]
(1) Normal operation state
It is assumed that the maximum main current for normal operation is 150A (rated current x 2, for keeping a margin)
and the sense resistance is 23.2Ω.
In this case, The maximum sense current flows through the sense resistor is calculated as below.
150A / 3000 = 50mA
And the loss at the sense resistor is
2
2
P=I ･R･t=(50mA) x 23.2Ω x 1s = 58mW
(2) Short circuit state
When short circuit occures, its current depends on the condition, but up to IGBT saturation current (about 10 times
of the rated current =750A) flows. So the sense current is
750A / 3000 = 250mA
But this current shut down within 2μs by SC protection. And the average loss at the sense resistor is
2
2
P=I ･R･t= (250mA) x 23.2Ω x 2μs / 1s =0.0029mW
As explained above, over 1/8W wattage resistor will be suitable, but it is necessary to confirm on your real system
finally.
[Remarks]
It takes more time (Table 2-8) from inputting over threshold voltage to CIN terminal to shutting down IGBTs.
(Because of IC’s transfer delay)
Table 2-8 Internal time delay of IC
Item
min
IC transfer delay time
0.3
typ
0.5
max
1.0
Unit
μs
Therefore, the total delay time from short circuit occurring to shutting down IGBTs is the sum of the delay by the
outer RC filter and this IC delay.
[SC protection (N-side only)]
a1. Normal operation: IGBT ON and outputs current.
a2. Short circuit current detection (SC trigger) (It is recommended to set RC time constant 1.5~2.0μs so that IGBT shut down
within 2.0μs when SC.)
a3. All N-side IGBTs' gates are hard interrupted.
a4. All N-side IGBTs turn OFF.
a5. Fo outputs with a fixed pulse width determined by the external capacitance CFO.
a6. Input “L”: IGBT off.
a7. Fo finishes output, but IGBTs don't turn on until inputting next ON signal (LH).
(IGBT of each phase can return to normal state by inputting ON signal to each phase.)
a8. Normal operation: IGBT ON and outputs current.
Lower-side control
input
a6
SET
RESET
Protection circuit state
a3
Internal IGBT gate
a4
SC trip current level
a8
Output current Ic
a1
a7
a2
SC reference voltage
Sense voltage of
the sense resistor
Delay by RC filtering
Error output Fo
a5
Fig.2-6 SC protection timing chart
Publication Date : October 2012
10
<Dual-In-Line Package Intelligent Power Module>
600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
[About Short Circuit Protection by Sense IGBT]
This function aims to protect from Short Circuit like arm short or load short. If high accuracy of protection current level
(e.g. demagnetizing current of motor) is necessary, it is recommended to adopt the method by detecting the voltage at
outer shunt resistors into main current path. In that case, the current split ratio between main and sense currents varies,
thus minimum SC protection trip level changes from the value in Table 2-7. Therefore, adjustment of the sense
resistance will be needed. The example of minimum SC trip level with outer shunt resistor is described in Table 2-9.
(PS21A79, at sense resistance 40.2Ω) Please contact us about selecting sense resistance in the case of inserting
outer shunt resistors.
It is recommended to set outer shunt resistance 7mΩ or less for PS21A79 and 4.5mΩ or less for PS21A7A because
too large shunt resistance causes a decrease of IGBT saturation current by decreasing gate voltage at large current.
(Large current makes large voltage drop at shunt resistor.) For shunt resistor, select the low parasitic inductance
resistor like surface mounted device type and pattern the wiring from the N-side emitter (NU, NV, NW) terminals as
short as possible because of reducing surge by shutdown at large short circuit current.
Table 2-9 SC protection trip level (PS21A79, sense resistance 40.2Ω)
Outer shunt resistance
Minimum SC trip level
Nothing
85A
3mΩ
57A
5mΩ
48A
As a method that combines short circuit and over current protection function, there is a method which doesn't use
sense resistor too. It is the same method as former DIPIPM Ver.3 and the example of the protection circuit is described
in Fig.2-7.
The SC protection trip level is needed to set to double the rated current or less. And it is recommended to set the
reference voltage of comparators to about 0.5V and select the shunt resistance in order that the SC trip level may be
double the rated current or less. (E.g. for PS21A79 (rated current 50A), R=0.5V/100A=5mΩ or more)
When this protection method is applied, the rated sense resistor should be connected between Vsc terminal and
GND for protecting from surge too. (Don't leave it open.)
DIPIPM
Drive circuit
P
P-side IGBTs
U
V
W
N-side IGBTs
Outer Protection Circuit
Rf
C
NW
NV
NU
B
-
Vref
+
Cf
Rf
D
Drive circuit
VNC
Rf
Vsc
Shunt
resistors
Rs
A
The sense resistor
should be connected
when not detecting
sense currents.
N1
when SC protection
works, Input signal
to CIN (OR output)
needs to be over
1V .
-
Cf
Vref
Protection circuit
CIN
5V
+
OR output
-
Cf
Vref
+
Comparators
(Open collector output type)
Fig.2-7 Example of SC protection circuit without detecting sense current.
Note:
• It is necessary to set the time constant RfCf of external comparator input so that IGBT can stop within 2μs when short circuit occurs.
SC interrupting time might vary with the wiring pattern, comparator speed and so on. If additional RC filter is inserted into OR
output, it is necessary to consider its delay too.
• The threshold voltage Vref is recommended to set about 0.5V.
• Select the shunt resistance so that SC trip-level is less than double the rated current.
• To avoid malfunction, the wiring A, B, C should be as short as possible.
• The point D at which the wiring to comparator is divided should be near the terminal of shunt resistor.
• OR output high level should be over 1V.
Publication Date : October 2012
11
<Dual-In-Line Package Intelligent Power Module>
600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
2.2.2 Control Supply UV Protection
The UV protection is designed for preventing unexpected operating behavior as described in Table 2-10.
Both P-side and N-side have UV protecting function. However, fault signal (Fo) output only corresponds to
N-side UV protection. Fo output continuously during UV state.
In addition, there is a noise filter (typ. 10μs) integrated in the UV protection circuit to prevent instantaneous UV
erroneous trip. Therefore, the control signals are still transferred in the initial 10μs after UV happened.
Table 2-10 DIPIPM operating behavior versus control supply voltage
Control supply voltage
Operating behavior
Equivalent to zero power supply.
UV function is inactive, no Fo output.
Normally IGBT does not work. But, external noise may cause DIPIPM
0-4.0V (P, N)
malfunction (turns ON), so DC-link voltage need to turn on after control
supply turning on. (Avoid inputting ON-signals to DIPIPM before the
control supply coming up to 13.5V)
UV function becomes active and output Fo (N-side only).
4.0-UV trip level (P, N)
Even if control signals are applied, IGBT does not work
IGBT can work. However, conducting loss and switching loss will
UV trip level-13.5V(N),13.0V(P)
increase, and result extra temperature rise at this state,.
Recommended conditions. (Normal operation)
13.5-16.5V (N), 13.0-18.5V (P)
IGBT works. However, switching speed becomes fast and saturation
16.5-20.0V (N),18.5-20.0V (P)
current becomes large at this state, increasing SC broken risk.
Over maximum voltage rating. The control circuit will be destroyed.
20.0V- (P, N)
Ripple Voltage Limitation of Control Supply
If high frequency precipitous noise is superimposed to the control supply line, IC malfunction might happen and
cause DIPIPM erroneous operation. To avoid such problem happens, line ripple voltage should meet the following
specifications:
dV/dt ≤ +/-1V/μs, Vripple≤2Vp-p
N-side UV Protection Sequence
a1. Control supply voltage VD exceeds under voltage reset level (UVDr), but IGBT turns ON when inputting next ON
signal (LH).(IGBT of each phase can return to normal state by inputting ON signal to each phase.)
a2. Normal operation: IGBT turn on and carry current.
a3. VD level drops to under voltage trip level. (UVDt).
a4. All N-side IGBTs turn OFF in spite of control input condition.
a5. Fo outputs for the period determined by the capacitance CFO, but output is extended during VD keeps below UVDr.
a6. VD level reaches UVDr.
a7. Normal operation: IGBT ON and carry current.
Control input
RESET
Protection circuit state
Control supply voltage VD
UVDr
SET
a1
UVDt
a3
a4
a2
RESET
a6
a7
Output current Ic
a5
Error output Fo
Fig.2-8 Timing chart of N-side UV protection
Publication Date : October 2012
12
<Dual-In-Line Package Intelligent Power Module>
600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
P-side UV Protection Sequence
b1. Control supply voltage VDB rises. After the voltage reaches under voltage reset level UVDBr, IGBT can turn on
when inputting next ON signal (LH).
b2. Normal operation: IGBT ON and outputs current.
b3. VDB level drops to under voltage trip level (UVDBt).
b4. IGBT of corresponding phase only turns OFF in spite of control input signal level, but there is no FO signal output.
b5. VDB level reaches UVDBr.
b6. Normal operation: IGBT ON and carry current.
Control input
RESET
SET
RESET
Protection circuit state
UVDBr
Control supply voltage VDB
b1
UVDBt
b2
b5
b3
b6
b4
Output current Ic
Error output Fo
Keep High-level (no fault output)
Fig.2-9 Timing Chart of P-side UV protection
2.2.3 Temperature analog output
(1) Purpose of this function
This function measures the temperature of control LVIC by built in temperature detecting circuit on LVIC.
The heat generated at IGBT and FWDi transfers to LVIC through mold package and inner and outer heat sink. So
that LVIC temperature cannot respond to rapid temperature change of those power chips effectively. (e.g. motor
lock, short current) It is recommended to use this function for protecting from excessive temperature rise by such
cooling system down and continuance of overload operation. （Replacement from the thermistor which was set on
outer heat sink currently）
[Note]
DIPIPM cannot shutdown IGBT and output fault signal automatically when temperature rises excessively. When
temperature exceeds the defined protect level, controller (MCU) should stop the DIPIPM.
(2) VOT characteristics
Inner circuit of VOT terminal is the output of OP amplifier circuit and is described as Fig.2-10
If the resistor is inserted between VOT and VNC(control supply GND) terminals, then the current (calculated by
VOT output ÷ resistance of inserted resistor) always flows as circuit current of LVIC.
The current capability of VOT output is described as Table 2-11.
DIPIPM
Table 2-11 Output capability (Tc=-20℃~100°C)
min.
Source
1.7mA
Sink
0.1mA
Source : the current flow from VOT to outside.
Sink
: the current flow from outside to VOT.
Temperature
Signal
VOT
Ref
MCU
VNC
Fig.2-10 Inner circuit of VOT terminal
This output might exceed 5V when temperature rises excessively, so it is recommended for protection of control
part like MCU to insert a clamp Di between supply (e.g. 5V) for control part and this output.
Publication Date : October 2012
13
<Dual-In-Line Package Intelligent Power Module>
600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
The characteristics of VOT output vs. LVIC temperature is described as Fig.2-11.
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.69
3.6
VOT Output (V)
3.57
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
Max.
1.2
1.0
-30
Typ.
-20
-10
Min.
0
10
20
30
Output might be saturated under1V
40
50
60
70
80
90
100
110
120
130
LVIC Temperature (°C)
Fig.2-11 VOT output vs. LVIC temperature
As mentioned above, the heat of power chips transfers to LVIC through the package and heat sink, and the
relationship between LVIC temperature: Tic(=VOT output), case temperature: Tc(measuring point is defined on
datasheet), and junction temperature: Tj depend on the system cooling condition, heat sink, control strategy, etc.
For example, the evaluation results in the case of using different size heat sink (Table 2-12) are described as
Fig.2-12. As the result of evaluations, it is clear that two cases have different relationships between LVIC
temperature Tic and case temperature Tc.
So when setting the threshold temperature for protection, it is necessary to measure the relationship between them
on your real system. And when setting threshold temperature Tic, it is important to consider the protection
temperature is at Tc≤100°C and Tj ≤150°C.
Publication Date : October 2012
14
<Dual-In-Line Package Intelligent Power Module>
600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
Measuring each temperatures @ only 1 IGBT chip turns on (DC current, Ta=25°C)
Table 2-12 Outer heat sink
Thermal resistance
Rth(f-a)
A
2.20K/W
B
1.35K/W
L
Heat sink size
(LxDxH)
100 x 88 x 40 mm
200 x 88 x 40 mm
H
Tj
120
100
120
Tc
80
Tj，Tc，Tic [°C]
Tj，Tc，Tic [°C]
D
Tic
60
∆T(j-c)
40
20
Tj
100
80
Tc
Tic
∆T(j-c)
60
40
20
0
0
25
20
30
35
40
50
45
55
20
25
30
35
40
45
50
55
IGBT loss [W]
IGBT loss [W]
(a) Heat sink A
(b) Heat sink B
Fig.2-12 IGBT loss vs. Tj, Tc, Tic(Ta=25°C, Typical)
The procedure example of setting protection temperature is described below.
Fig.2-13 indicates the example of the relationship between LVIC temperature Tic, case temperature Tc and
junction temperature Tj, and Fig.2-14 is the relationship between VOT and Tc, which is obtained by combining
Fig.2-11 and Fig.2-13.
If the protection level is set to Tj=125°C (Tc=100°C), then VOT threshold level should be set 3.75V which is the
maximum value @ Tc=100°C in Fig.2-14.
In this case the variation of real Tc may become from 100°C to 115°C. But even if the real Tc will be maximum
variation value 115°C, Tj becomes under 150°C (125°C+15°C=140°C<150°C).
150
3.9
130
3.8
VOTmax (Tc=100°C)
3.75V
120
3.7
Tc
110
VOT [V]
Tj，Ｔc，Ｔｉｃ[℃]
4.0
Tj
140
100
90
Tic
80
3.6
Variation +15°C
3.5
3.4
3.3
70
3.2
60
3.1
50
3.0
0
5
10
15
20
25
30
35
40
45
IGBT損失
[W]
IGBT
loss (W)
80
85
90
95
100
105
110
115
120
Tc[℃]
Fig.2-13 IGBT loss vs. Tj, Tc, Tic(Typical) (Ta=80°C)
Fig.2-14 VOT vs. Tc (Typical)
As mentioned above, the relationship between Tic, Tc and Tj depends on the system cooling condition and
control strategy, and so on. So please evaluate about these temperature relationship on your real system when
considering the protection level.
If necessary, it is possible to ship the sample with the individual data of VOT vs. LVIC temperature.
Publication Date : October 2012
15
<Dual-In-Line Package Intelligent Power Module>
600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
2.3 Package Outlines
Dimensions in mm
2.3.1 Outline Drawing
Fig.2-15 Outline drawing
Publication Date : October 2012
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<Dual-In-Line Package Intelligent Power Module>
600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
2.3.2 Power Chip Position
Fig.2-16 indicates the center position of the each power chips.
(This figure is the view from laser marked side.)
IGBT (CSTBT)
FWDi
UP
VP
WP
UN
VN
WN
(Unit：mm)
Fig.2-16 Power chip position
2.3.3 Laser Marking Position
The laser marking specification is described in Fig.2-17.
Mitsubishi Corporation mark, Type name (A), Lot number (B), and QR code mark are marked in the upper side of
module.
QR Code is registered trademark of DENSO WAVE INCORPORATED in JAPAN and other countries.
Fig.2-17 Laser marking view
Publication Date : October 2012
17
<Dual-In-Line Package Intelligent Power Module>
600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
2.3.4 Terminal Description
Table 2-13 Terminal description
No.
Name
Description
1
UP
U-phase P-side control input terminal
3
VP1
U-phase P-side control supply positive terminal
4
VUFB
U-phase P-side drive supply positive terminal
6
VUFS
U-phase P-side drive supply GND terminal
7
VP
V-phase P-side control input terminal
9
VP1
V-phase P-side control supply positive terminal
10
VVFB
V-phase P-side drive supply positive terminal
12
VVFS
V-phase P-side drive supply GND terminal
13
WP
W-phase P-side control input terminal
14
VP1
W-phase P-side control supply positive terminal
15
VPC
P-side control supply GND terminal
16
VWFB
W-phase P-side drive supply positive terminal
18
VWFS
W-phase P-side drive supply GND terminal
19
VSC
Sense current detecting terminal
21
VN1
N-side control supply positive terminal
22
VNC
N-side control supply GND terminal
23
VOT
LVIC temperature output terminal
24
CIN
SC trip voltage detect terminal
25
CFO
Fault pulse output width set terminal
26
FO
Fault signal output terminal
27
UN
U-phase N-side control input terminal
28
VN
V-phase N-side control input terminal
29
WN
W-phase N-side control input terminal
34
NW
W-phase N-side IGBT emitter terminal
35
NV
V-phase N-side IGBT emitter terminal
36
NU
U-phase N-side IGBT emitter terminal
37
W
W-phase output terminal
38
V
V-phase output terminal
39
U
U-phase output terminal
40
P
Inverter DC-link positive terminal
Publication Date : October 2012
18
No.
2
5
8
11
17
20
30
31
32
33
41
42
Name
Description
VPC
UPG
VPC
VPG
W PG
UNG
VNC
W NG
VNG
W
U
V
Internal use (Dummy pin)
Don’t connect all dummy
pins to any other terminals
or PCB pattern.
(Leave no connect)
<Dual-In-Line Package Intelligent Power Module>
600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
Table 2-14 Detailed description of input and output terminals
Item
Symbol
Description
• Drive supply terminals for P-side IGBTs.
• By virtue of applying the bootstrap circuit scheme, individual isolated power
supplies are not needed for the DIPIPM P-side IGBT drive. Each bootstrap
P-side drive supply
capacitor is charged by the N-side VD supply during ON-state of the
positive terminal
corresponding
N-side IGBT in the loop.
VUFB- VUFS
• Abnormal operation might happen if the VD supply is not aptly stabilized or has
VVFB- VVFS
insufficient current capability. In order to prevent malfunction caused by such
V
WFB- VWFS
unstability as well as noise and ripple in supply voltage, a bypass capacitor with
P-side drive supply
favorable frequency and temperature characteristics should be mounted very
GND terminal
closely to each pair of these terminals.
• Inserting a Zener diode (24V/1W) between each pair of control supply terminals
is helpful to prevent control IC from surge destruction.
• Control supply terminals for the built-in HVIC and LVIC.
P-side control
• In order to prevent malfunction caused by noise and ripple in the supply voltage,
supply terminal
a bypass capacitor with favorable frequency characteristics should be mounted
very closely to these terminals.
VP1
• Carefully design the supply so that the voltage ripple caused by noise or by
VN1
system operation is within the specified minimum limitation.
N-side control
• It is recommended to insert a Zener diode (24V/1W) between each pair of control
supply terminal
supply terminals to prevent surge destruction.
• Control ground terminal for the built-in HVIC and LVIC.
N-side control GND
VPC
• Ensure that line current of the power circuit does not flow through this terminal in
terminal
VNC
order to avoid noise influences.
• Control signal input terminals.
• Voltage input type. These are internally connected to Schmitt trigger circuit..
Control input
UP,VP,W P • The wiring of each input should be as short as possible to protect the DIPIPM
from noise interference.
UN,VN,W N
terminal
• Use RC coupling in case of signal oscillation.(Pay attention to threshold voltage
of input terminal, because input circuit has pull down resistor (min 3.3kΩ))
• The sense current split at N-side IGBT flows out from this terminal. For SC
Sense current
VSC
protection, connect predefined resistor here.
detect terminal
• Input the potential of Vsc terminal (with sense resisteor) to CIN terminal for SC
Short-circuit trip
protection through RC filter (for the noise immunity).
voltage detecting
CIN
• The time constant of RC filter is recommended to be up to 2μs.
terminal
• Fault signal output terminal for N-side abnormal state(SC or UV).
• This output is open drain type. FO signal line should be pulled up to a 5V logic
Fault signal output
FO
supply with over 5kΩ resistor (for limitting the Fo sink current IFoup to 1mA.)
terminal
Normally 10kΩ is recommended.
• The terminal is for setting the fault pulse output width.
Fault pulse output
• An external capacitor should be connected between this terminal and VNC.
CFO
width setting
• When 22nF capacitor is connected, then the Fo pulse width becomes 2.4ms.
-6
terminal
CFO = tFO x 9.1 x 10 (F)
• LVIC temperature is ouput by analog signal. It is ouput of OP amplifer internally.
Temperature output
VOT
terminal
• DC-link positive power supply terminal.
• Internally connected to the collectors of all P-side IGBTs.
Inverter DC-link
• To suppress surge voltage caused by DC-link wiring or PCB pattern inductance,
P
positive terminal
smoothing capacitor should be inserted very closely to the P and N terminal. It is
also effective to add small film capacitor with good frequency characteristics.
• Open emitter terminal of each N-side IGBT
Inverter DC-link
NU,NV,NW • If usage of common emitter is needed, connect these terminals together at
negative terminal
the point as close from the package as possible.
• Inverter output terminals for connection to inverter load (e.g. AC motor).
Inverter power
• Each terminal is internally connected to the intermidiate point of the
U, V, W
output terminal
corresponding IGBT half bridge arm.
Note: 1) Use oscilloscope to check voltage waveform of each power supply terminals and P&N terminals, the time division of OSC
should be set to about 1μs/div. Please ensure the voltage (including surge) not exceed the specified limitation.
Publication Date : October 2012
19
<Dual-In-Line Package Intelligent Power Module>
600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
2.4 Mounting Method
This section shows the electric spacing and mounting precautions.
2.4.1 Electric Spacing
The electric spacing specification of Large DIPIPM Ver.4 is shown in Table 2-15
Table 2-15 Minimum insulation distance
Clearance (mm)
Creepage (mm)
7.1
7.9
3.3
5.6
3.7
5.6
Between live power terminals
with high potential
Between live control terminals
with high potential
Between terminals and heat sink
2.4.2 Mounting Method and Precautions
When installing the module to the heat sink, excessive or uneven fastening force might apply stress to inside
chips. Then it will lead to a broken or degradation of the device. The recommended fastening procedure is shown
in Fig.2-18. When fastening, it is necessary to use the torque wrench and fasten up to the specified torque. Also,
pay attention not to have any desert remaining on the contact surface between the module and the heat sink.
(2)
Temporary fastening
(1)(2)
(1)
Permanent fastening
(1)(2)
Note: Generally, the temporary fastening
torque is set to 20-30% of the maximum
torque rating.
Not care the order of fastening (1) or (2),
but need to fasten alternately.
Fig.2-18 Recommended screw fastening order
Table 2-16 Mounting torque and heat sink flatness specifications
Item
Condition
Min.
Typ.
Max.
Unit
Mounting torque
Recommended 1.18N·m, Screw : M4
0.98
-
1.47
N·m
Flatness of outer heat sink
Refer Fig.2-19
-50
-
+100
μm
Fig.2-19 Measurement point of heat sink flatness
In order to get effective heat dissipation, it is necessary to keep the contact area as large as possible to minimize
the contact thermal resistance. Regarding the heat sink flatness (warp, concavity and convexity) on the module
installation surface, the surface finishing-treatment should be within Rz12.
Evenly apply thermally conductive grease with 100μ-200μm thickness over the contact surface between the
module and the heat sink, which is also useful for preventing corrosion. The contacting thermal resistance between
DIPIPM case and heat sink Rth(c-f) is determined by the thickness and the thermal conductivity of the applied grease.
For reference, Rth(c-f) is about 0.2°C/W (per 1/6 module, grease thickness: 20μm, thermal conductivity: 1.0W/m·k).
Publication Date : October 2012
20
<Dual-In-Line Package Intelligent Power Module>
600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
2.4.3 Soldering Conditions
The recommended soldering condition is mentioned as below.
(Note: The reflow soldering cannot be recommended for DIPIPM.)
(1) Flow (wave) Soldering
DIPIPM is tested on the condition described in Table 2-17 about the soldering thermostability, so the
recommended conditions for flow (wave) soldering are soldering temperature is up to 265°C and the
immersion time is within 11s.
However, the condition might need some adjustment based on flow condition of solder, the speed of the
conveyer, and the land pattern and the through hole shape on the PCB, etc.
It is necessary to confirm whether it is appropriate or not for your real PCB finally.
Table 2-17 Reliability test specification
Item
Soldering Thermostability
Condition
260±5°C, 10±1s
(2) Hand soldering
Since the temperature impressed upon the DIPIPM may changes based on the soldering iron types
(wattages, shape of soldering tip, etc.) and the land pattern on PCB, we cannot suggest the recommended
temperature condition for hand soldering.
As a general requirement of the temperature profile for hand soldering, the temperature of the root of the
DIPIPM terminal should be kept under 150°C for considering glass transition temperature (Tg) of the package
molding resin and the thermal withstand capability of internal chips. Therefore, it is necessary to check the
DIPIPM terminal root temperature, solderability and so on in your real PCB, when configure the soldering
temperature profile. (It is recommended to set the soldering time as short as possible.)
For reference, the evaluation example of hand soldering with 50W soldering iron is described as below.
[Evaluation method]
a. Sample: Large DIPIPM Ver.4
b. Evaluation procedure
- Put the soldering tip of 50W iron (temperature set to 400°C) on the terminal within 1mm from the toe.
(The lowest heat capacity terminal (=control terminal) is selected.)
- Measure the temperature rise of the terminal root part by the thermocouple installed on the terminal root.
Soldering iron
1mm
Thermocouple
DIPIPM
Terminal root temp. (°C)
180
150
120
90
60
30
0
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Heating time(s)
Fig.2-20 Heating and measuring point
Fig.2-21 Temperature alteration of the terminal root (Example)
[Note]
For soldering iron, it is recommended to select one for semiconductor soldering (12~24Ｖ low voltage type,
and the earthed iron tip) and with temperature adjustment function.
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600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
CHAPTER3 SYSTEM APPLICATION HIGHLIGHT
3.1 Application Guidance
This chapter states usage and interface circuit design hints.
3.1.1 System connection
P-side input (PWM)
C1: Electrolytic type with good temperature and frequency characteristics
Note: the capacitance also depends on the PWM control strategy of the application system
C2: 0.22μ-2μF ceramic capacitor with good temperature, frequency and DC bias characteristics
C3: 0.1μ-0.22μF Film capacitor (for snubber)
D1: Bootstrap diode. High speed type with VRRM: over Vces(=600V), trr: up to 100ns
D2: Zener diode 24V/1W for surge absorber
Input signal
conditioning
Input signal
conditioning
Level shifter
Level shifter
Protection
circuit (UV)
Drive circuit
Protection
circuit (UV)
Drive circuit
C2
C1
D2 Bootstrap circuit
Input signal
conditioning
Level shifter
D1
Protection
circuit (UV)
Drive circuit
Inrush current limiter
circuit
P
AC line input
P-side IGBTs
Noise filter
U
M
V
C3
W
Varistor
C
AC output
GDT
N
N-side IGBTs
VSC
C : AC filter(ceramic capacitor 2.2n -6.5nF)
(Common-mode noise filter)
CIN
Temp. Output
Drive circuit
Input signal
conditioning
VOT
N-side input (PWM)
Protection
circuit
Fo logic
Fo output
CFO
Control supply
Under-Voltage
protection (UV)
VNC
D2
C2
C1
VD 15V
Fig.3-1 Application System block diagram
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600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
3.1.2 Interface Circuit (Direct Coupling Interface example)
Fig.3-2 shows a typical application circuit of connecting with MCU or DSP directly.
P(40)
IGBT1
UP(1)
VP1(3)
R3
C5
C2
Di1
HVIC
VUFB(4)
U(39)
+
D2
VUFS(6)
C1D1C2
R3
VP(7)
C5
VP1(9)
C2
IGBT2
Di2
HVIC
VVFB(10)
V(38)
+
D2
VVFS(12)
C1D1C2
R3
W P(13)
C5
VP1(14)
C2
VPC(15)
IGBT3
Di3
HVIC
MCU
VWFB(16)
W(37)
+
D2
M
+
VWFS(18)
IGBT4
C1D1C2
Di4
C3
R3
UN(27)
C5
R3
VN(28)
C5
R3
W N(29)
C5
5V
CFO(25)
NU (36)
IGBT5
Di5
NV (35)
R2
Fo(26)
LVIC
IGBT6
Di6
VOT(23)
NW(34)
15V
VD
C1
+
D1
VN1(21)
C2
VNC(22)
C
VSC(19)
CIN(24)
B
C4
D
R1
Sense
resistor
Control GND wiring N1 Power GND wiring
Fig.3-2 Interface circuit example (Direct coupling)
Note
1 :If control GND and power GND are patterned by common wiring, it may cause malfunction by fluctuation of power GND level. It is recommended to connect
control GND and power GND at only a N1 point at which NU, NV, NW are connected to power GND line.
2 :It is recommended to insert a Zener diode D1 (24V/1W) between each pair of control supply terminals to prevent surge destruction.
3 :To prevent surge destruction, the wiring between the smoothing capacitor and the P, N1 terminals should be as short as possible. Generally inserting a
0.1μ~0.22μF snubber capacitor C3 between the P-N1 terminals is recommended.
4 :R1, C4 of RC filter for preventing protection circuit malfunction is recommended to select tight tolerance, temp-compensated type. The time constant R1C4
should be set so that SC current is shut down within 2μs. (1.5μs~2μs is general value.) SC interrupting time might vary with the wiring pattern, so the enough
evaluation on the real system is recommended. If R1 is too small, it may leads to delay of protection. So R1 should be min. 10 times larger resistance than Rs.
(100 times is recommended.)
5 :To prevent erroneous operation, the wiring of A, B, C should be as short as possible.
6 :For sense resistor, the variation within 1%(including temperature characteristics), low inductance type is recommended. And the over 1/8W is recommended,
but it is necessary to evaluate in your real system finally.
7 :To prevent erroneous SC protection, the wiring from VSC terminal to CIN filter should be divided at the point D that is close to the terminal of sense resistor. And
the wiring should be patterned as short as possible.
8 :All capacitors should be mounted as close to the terminals of the DIPIPM as possible. (C1: good temperature, frequency characteristic electrolytic type, and C2:
0.22μ~2.0μF, good temperature, frequency and DC bias characteristic ceramic type are recommended.)
9 :Input drive is High-active type. There is a min. 3.3kΩ pull-down resistor in the input circuit of IC. To prevent malfunction, the wiring of each input should be
patterned as short as possible. When using RC filter R3C5, it is necessary to confirm the input signal level to meet the turn-on and turn-off threshold voltage.
Thanks to HVIC inside the module, direct coupling to MCU without any opto-coupler or transformer isolation is possible.
10 :Fo output is open drain type. It should be pulled up to MCU or control power supply (e.g. 5V,15V) by a resistor that makes IFo up to 1mA. (IFO is estimated
roughly by the formula of control power supply voltage divided by pull-up resistance. In the case of pulled up to 5V, 10kΩ (5kΩ or more) is recommended.)
11 :Error signal output width (tFo) can be set by the capacitor connected to CFO terminal. CFO(typ.) = tFo x (9.1 x 10-6) (F)
12 :High voltage (VRRM =600V or more) and fast recovery diode (trr=less than 100ns or less) should be used for D2 in the bootstrap circuit.
13 :If high frequency noise superimposed to the control supply line, IC malfunction might happen and cause erroneous operation. To avoid such problem, voltage
ripple of control supply line should meet dV/dt ≤+/-1V/μs, Vripple≤2Vp-p.
14 :For DIPIPM, it isn't recommended to drive same load by parallel connection with other phase IGBT or other DIPIPM.
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600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
3.1.3 Interface Circuit (Opto-coupler Isolated Interface)
5V
R3
C5
C2
D2
+
C5
C2
+
P(40)
Di1
HVIC
VUFB(4)
U(39)
IGBT2
VP(7)
VP1(9)
Di2
HVIC
VVFB(10)
V(38)
VVFS(12)
C1D1C2
R3
C5
C2
D2
VP1(3)
VUFS(6)
C1D1C2
R3
D2
IGBT1
UP(1)
+
W P(13)
IGBT3
VP1(14)
VPC(15)
M
Di3
HVIC
VWFB(16)
W(37)
+
VWFS(18)
IGBT4
MCU
C1D1C2
Di4
C3
R3
UN(27)
C5
R3
VN(28)
C5
R3
W N(29)
NU (36)
IGBT5
Di5
C5
CFO(25)
NV (35)
Fo(26)
LVIC
IGBT6
Di6
VOT(23)
15V
VD
C1
+
NW (34)
VN1(21)
+
D1
C2
VNC(22)
VSC(19)
CIN(24)
Vref（Temperature protection level）
C4
R1
Sense
resistor
N1
Fig.3-3 Interface circuit example with opto-coupler
Note:
(1) High speed (high CMR) opto-coupler is recommended.
(2) Fo terminal sink current is max.1mA. A buffer circuit will be necessary to drive an opto-coupler.
(3) When RC filter R3C5 is inserted for preventing malfunction, it is necessary to confirm the input signal level to meet the
turn-on and turn-off threshold voltage.
(4) About comparator circuit at VOT output, it is recommended to design the input circuit with hysteresis because of preventing
output chattering.
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600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
3.1.4 Circuits of Signal Input terminals and Fo Terminal
Large DIPIPM Ver.4 is high-active input logic. A 3.3kΩ(min) pull-down resistor is built-in each input circuit of the
DIPIPM as shown in Fig.3-4, so external pull-down resistor is not needed.
When using same PCB for 600V large DIPIPM Ver.4 PS21A7* series and 1200V series PS22A7* which have same
package, it needs to give attention to the difference of input threshold voltage.
DIPIPM
Level Shift
Circuit
UP, VP, W P
Gate Drive
Circuit
3.3kΩ (min)
Gate Drive
Circuit
UN, VN, W N
3.3kΩ (min)
Fig.3-4 Internal structure of control input terminals
Table 3-1 Input threshold voltage ratings (Tj=25°C)
Item
Symbol
Turn-on threshold voltage
Vth(on)
Turn-off threshold voltage
Vth(off)
Condition
UP,VP,W P-VPC
UN,VN,W N-VNC
Min.
Typ.
Max.
2.1
2.3
2.6
0.8
1.4
2.1
Unit
V
The wiring of each input should be patterned as short as possible. And if the pattern is long and the noise is imposed
on the pattern, it may be effective to insert RC filter.
5V
10kΩ
DIPIPM
UP,VP,WP,UN,VN,WN
MCU
Fo
3.3kΩ(min)
VNC(Logic)
Fig.3-5 Control input connection
Note: The RC coupling (parts shown in the dotted line) at each input depends on user’s PWM control strategy and the wiring
impedance of the printed circuit board.
The DIPIPM signal input section integrates a 3.3kΩ(min) pull-down resistor. Therefore, when using an external
filtering resistor, please pay attention to the signal voltage drop at input terminal.
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600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
There are limits for the minimum input pulse width in the DIPIPM. The DIPIPM might make no response or delayed
response, if the input pulse width (both on and off) is shorter than the specified value. (Please refer Table 3-2)
Table 3-2 Allowable minimum input pulse width
On signal
Off signal
Symbol
Condition
PWIN(on)
-
200≤VCC≤350V,
13.5≤VD≤16.5V,
13.5≤VDB≤18.5V,
PWIN(off)
-20≤TC≤100°C,
N line wiring inductance
less than 10nH
PN
Min. value
PS21A79
1.1
PS21A7A
1.3
PS21A79
3.0
PS21A7A
3.0
PS21A79
5.0
PS21A7A
5.0
Up to rated current
From rated current to
1.7 times rated current
Unit
μs
*) Input signal with ON pulse width less than PWIN(on) might make no response.
IPM might make delayed response or no response for the input signal with off pulse width less than PWIN(off).
Please refer Fig.3-6 about delayed response .
P Side Control Input
Internal IGBT Gate
Output Current Ic
t2
t1
Real line: off pulse width>PWIN(off); turn on time t1
Broken line: off pulse width<PWIN(off); turn on time t2
(t1:Normal switching time)
Fig.3-6 Delayed Response with shorter input off (P-side only)
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600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
(2) Internal Circuit of Fo Terminal
FO terminal is an open drain type, it should be pulled up to control supply (e.g. 5V) as shown in Fig.3-5.
Fig.3-7 shows the typical V-I characteristics of Fo terminal. The maximum sink current of Fo terminal is 1mA.
(IFo can be estimated from IFo=control supply voltage / pull up resistance approximately.)
If opto-coupler is applied to this output, please pay attention to the opto-coupler drive ability.
Table 3-3
Electric characteristics of Fo terminal
Item
Symbol
Condition
VFOH
VSC=0V,Fo=10kΩ, 5V pulled-up
Fault output voltage
VFOL
VSC=1V,Fo=1mA
Min.
4.9
-
Typ.
-
Max.
0.95
Unit
V
V
0.50
0.45
0.40
0.35
VFo(V)
0.30
0.25
0.20
0.15
0.10
0.05
0.00
0.0
0.2
0.4
0.6
0.8
1.0
IFo(mA)
Fig.3-7 Fo terminal typical V-I characteristics (VD=15V, Tj=25°C)
3.1.5 Snubber Circuit
In order to prevent DIPIPM from the surge destruction, the wiring length between the smoothing capacitor and
DIPIPM P-N terminals should be as short as possible. Also, a 0.1μ~0.22μF/630V snubber capacitor should be
mounted to the position between P and the connect point of NU, NV and NW terminals as close as possible as
Fig.3-8.
DIPIPM
Wiring Inductance
P
+
Snubber
capacitor
NU
NV
NW
N1
Fig.3-8 Recommended snubber circuit position
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600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
3.1.6 Influence of wiring
Influence of pattern wiring around the sense resistor for SC protection and GND is shown below.
IGBT4
Di4
NU
VN1
IGBT5
Di5
NV
LVIC
UN
IGBT6
Di6
VN
WN
NW
Fo
VOT
VNC
CFO
CIN
B
Vsc
A
Rs
N1
C
RC filter for noise cancelling
Recommended time constant: 1.5-2.0μs
Fig.3-9 External protection circuit
(1) Influence of the part-A wiring
The part-A wiring affects SC protection level. SC protection works by judging the voltage of the CIN terminals. If
part-A wiring is too long, extra surge voltage generated by the wiring inductance will lead to fluctuation of SC
protection level. This wiring should be as short as possible for limiting the surge voltage.
(2) Influence of the part-B wiring pattern
RC filter is added to remove noise influence occurring on the sense resistor. Filter effect will dropdown and noise
will easily superimpose on the wiring, if part-B wiring (=after filtering part) is too long. Please install the RC filter near
CIN, VNC terminals as close as possible.
(3) Influence of the part-D wiring pattern
Part-C wiring pattern gives influence to all the items described above, maximally shorten the GND wiring is
expected. If control GND is connected to power GND by broad pattern, it may cause malfunction by power GND
fluctuation. It is recommended to connect control GND and power GND at only a point at which NU, NV, NW are
connected to power GND line.
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600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
3.1.7 Precaution for wiring on PCB
4
These wire potentials fluctuate between Vcc and GND potential at
switching, so it may cause malfunction if wires for control (e.g. control input
Vin, control supply) are located near by or cross these wires. Particularly
pay attention when using multi layered PCB.
It is recommended to locate wires for control as far from these wires as
ossible.
3
Capacitor and Zener diode
should be located at near
terminals
Bootstrap
diode
Vin
+15V
DIPIPM
VUFS,VUFS,VWFS
Output
(to motor)
P
VUFB,VUFB,VWFB
U
Power supply
UP,VP,WP
V
Snubber
capacitor
VN1,VP1
VNC,VPC
W
Control
GND
Connect CIN filter's
capacitor to control GND
(not to Power GND)
VSC
NU
CIN
NV
UN,VN,WN
NW
N1
Power GND
Locate snubber capacitor
between P and N1 and as
near by terminals as possible
2
NU, NV, NW should be
connected each other as close
to the terminals as possible.
1
It is recommended to connect control GND and
power GND at only a point. (Not connect common
broad pattern)
Fig.3-10 Precaution for wiring on PCB
The case example of trouble due to PCB pattern
Case example
Matter of trouble
•Control GND pattern overlaps The surge, generated by the wiring pattern and di/dt of noncontiguous
1
power GND pattern.
big current flows to power GND, transfers to control GND pattern. it
causes the control GND level fluctuation, so that the input signal based
on the control GND fluctuates too. Finally the arm short occurs.
•Ground loop pattern is
Stray current flows to GND loop pattern, so that the control GND level
existing.
and input signal level (based on the GND) fluctuates. Then the arm
short occurs.
•Long pattern between NU, NV, Long wiring pattern has big parasitic inductance and generates high
2
NW terminals and N1
surge when switching. This surge causes the matter as below.
•HVIC malfunction by VS voltage (output terminal potential) decreasing
excessively.
•LVIC surge destruction
Capacitors or zener diodes are IC surge destruction or malfunction occurs.
3
nothing or located far from the
terminals.
The input lines are located
The cross talk noise might be transferred through the capacitance
4
parallel and close to the
between these floating supply lines and input lines to DIPIPM. Then
floating supply lines for P-side
since the incorrect signals are input to DIPIPM, the arm short circuit
drive.
might occur.
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600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
3.1.8 SOA of DIPIPM
The following describes the SOA (Safety Operating Area) of DIPIPM.
Maximum rating of IGBT collector-emitter voltage
VCES :
Supply voltage applied on P-N terminals
VCC :
VCC(surge): The total amount of VCC and the surge voltage generated by the wiring inductance and the
DC-link capacitor.
VCC(PROT) : DC-link voltage that DIPIPM can protect itself.
Collector
current Ic
≤Vcc(surge)
Short-circuit
current
≤Vcc(surge) ≤VCC
≤VCC(PROT)
VCE=0, IC=0
VCE=0, IC=0
≤2μs
Fig.3-11 SOA at switching mode
Fig.3-12 SOA at short-circuit mode
In Case of switching
VCES represents the maximum voltage rating (600V) of the IGBT. By subtracting the surge voltage (100V or
less ) generated by internal wiring inductance from VCES is VCC(surge), that is 500V. Furthermore, by subtracting
the surge voltage (50V or less) generated by the wiring inductor between DIPIPM and DC-link capacitor from
VCC(surge) derives VCC, that is 450V.
In Case of Short-circuit
VCES represents the maximum voltage rating (600V) of the IGBT . By Subtracting the surge voltage (100V or
less) generated by internal wiring inductor from VCES is VCC(surge), that is, 500V. Furthermore, by subtracting the
surge voltage (100V or less) generated by the wiring inductor between the DIPIPM and the electrolytic
capacitor from VCC(surge) derives VCC, that is, 400V.
3.1.9 SCSOA
Fig.3-13 and Fig.3-14 show the typical SCSOA performance curves of PS21A7A and PS21A79.
Conditions: Vcc=400V, Tj=125°C at initial state, Vcc(surge)≤500V(surge included), non-repetitive,2m load.
The DIPIPM can shutdown safely an SC current that is about 10 times of its current rating under the
conditions only if the IGBT conducting period is less than 4.5μsec.
Since the SCSOA operation area will vary with the control supply voltage, DC-link voltage, and etc, it is
necessary to set time constant of RC filter with a margin.
900
VD=18.5V
800
VD=16.5V
700
600
Ic(Apeak)
VD=15V
↑
Max. Saturation Current≈680A
@VD=16.5V
500
400
300
CSTBT SC operation area
200
100
0
0
1
2
3
4
4.5
5
Input pulse width [μs]
Fig.3-13 PS21A7A typical SCSOA curve
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600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
700
VD=18.5V
VD=16.5V
600
Ic(Apeak)
500
VD=15V
↑
Max. Saturation Current≈520A
@VD=16.5V
400
300
200
CSTBT SC operation area
100
0
0
1
2
3
4
4.5 5
Input pulse width [μs]
Fig.3-14 PS21A79 typical SCSOA curve
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600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
3.1.10 Power Life Cycles
When DIPIPM is in operation, repetitive temperature variation will happens on the IGBT junctions (ΔTj). The
amplitude and the times of the junction temperature variation affect the device lifetime.
Fig.3-15 shows the IGBT power cycle curve as a function of average junction temperature variation (ΔTj).
(The curve is a regression curve based on 3 points of ΔTj=46, 88, 98K with regarding to failure rate of 0.1%, 1% and
10%. These data are obtained from the reliability test of intermittent conducting operation)
10000000
1%
10%
0.1%
Power Cycles
1000000
100000
10000
1000
10
100
Average junction temperature variation ΔTj(K)
Fig.3-15 Power cycle curve
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600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
3.2 Power Loss and Thermal Dissipation Calculation
3.2.1 Power Loss Calculation
Simple expressions for calculating average power loss are given below:
● Scope
The power loss calculation intends to provide users a way of selecting a matched power device for their
VVVF inverter application. However, it is not expected to use for limit thermal dissipation design.
● Assumptions
(a) PWM controlled VVVF inverter with sinusoidal output;
(b) PWM signals are generated by the comparison of sine waveform and triangular waveform.
(c) Duty amplitude of PWM signals varies between
1− D 1+ D
(%/100), (D: modulation depth).
～
2
2
(d) Output current various with Icp·sinx and it does not include ripple.
(e) Power factor of load output current is cosθ, ideal inductive load is used for switching.
● Expressions Derivation
PWM signal duty is a function of phase angle x as
1 + D × sin x
which is equivalent to the output voltage
2
variation. From the power factor cosθ, the output current and its corresponding PWM duty at any phase angle
x can be obtained as below:
Output current = Icp × sin x
1 + D × sin( x + θ )
PWM Duty =
2
Then, VCE(sat) and VEC at the phase x can be calculated by using a linear approximation:
Vce( sat ) = Vce( sat )(@ Icp × sin x)
Vec = (−1) × Vec(@ Iecp(= Icp) × sin x)
Thus, the static loss of IGBT is given by:
1
2π
∫
π
0
( Icp × sin x) ×Vce( sat )(@ Icp × sin x) ×
1 + D sin( x + θ )
• dx
2
Similarly, the static loss of free-wheeling diode is given by:
1
2π
2π
∫π
((−1) × Icp × sin x)((−1) × Vec(@ Icp × sin x) ×
1 + D sin( x + θ )
• dx
2
On the other hand, the dynamic loss of IGBT, which does not depend on PWM duty, is given by:
1
2π
∫
π
0
( Psw(on)(@ Icp × sin x) + Psw(off )(@ Icp × sin x)) × fc • dx
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600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
FWDi recovery characteristics can be approximated by the ideal curve shown in Fig.3-16, and its dynamic
loss can be calculated by the following expression:
trr
IEC
VEC
t
Irr
Vcc
Fig.3-16 Ideal FWDi recovery characteristics curve
Psw =
Irr × Vcc × trr
4
Recovery occurs only in the half cycle of the output current, thus the dynamic loss is calculated by:
1 2π Irr (@ Icp × sin x) × Vcc × trr (@ Icp × sin x)
× fc • dx
2 ∫π
4
1 2π
= ∫ Irr (@ Icp × sin x) × Vcc × trr (@ Icp × sin x) × fc • dx
8 ρ

Attention of applying the power loss simulation for inverter designs
・ Divide the output current period into fine-steps and calculate the losses at each step based on the
actual values of PWM duty, output current, VCE(sat), VEC, and Psw corresponding to the output current.
The worst condition is most important.
・ PWM duty depends on the signal generating way.
・ The relationship between output current waveform or output current and PWM duty changes with the
way of signal generating, load, and other various factors. Thus, calculation should be carried out on the
basis of actual waveform data.
・ VCE(sat),VEC and Psw(on, off) should be the values at Tj=125°C.
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600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
3.2.2 Temperature Rise Considerations and Calculation Example
Fig.3-17 shows the typical characteristics of allowable motor rms current versus carrier frequency under the
following inverter operating conditions based on power loss simulation results.
Conditions: VCC=300V, VD=VDB=15V, VCE(sat)=Typ., P.F=0.8, Switching loss=Typ., Tj=125°C, Tc=100°C,
Rth(j-c)=Max., 3-phase PWM modulation, 60Hz sine waveform output
60
50
Io(Arms)
40
PS21A7A
30
PS21A79
20
10
0
0
5
10
15
20
fc(kHz)
Fig.3-17 Effective current-carrier frequency characteristic
Fig.3-17 shows an example of estimating allowable inverter output rms current under different carrier frequency
and permissible maximum operating temperature condition (Tc=100°C and Tj=125°C). The results may change
for different control strategy and motor types. Anyway please ensure that there is no large current over device
rating flowing continuously.
The allowable motor current can also be obtained from the free power loss simulation software provided by
Mitsubishi electric on its web site (URL: http://www.mitsubishielectric.com/semiconductors/).
Publication Date : October 2012
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<Dual-In-Line Package Intelligent Power Module>
600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
3.3 Noise Withstand Capability
3.3.1 Evaluation Circuit
DIPIPM have been confirmed to be with over +/-2.0kV noise withstand capability by the noise evaluation under the
conditions shown in Fig.3-18. However, noise withstand capability greatly depends on the test environment, the wiring
patterns of control substrate, parts layout, and other factors; therefore an additional confirmation on prototype is
necessary.
C
R
Breaker
U
V
W
DIPIPM
S
T
AC input
M
Fo
Voltage slider
Control supply
(15V single power source)
I/F
Isolation
transformer
Heat sink
Inverter
DC supply
Noise simulator
AC100V
Fig.3-18 Noise withstand capability evaluation circuit
Note:
C1: AC line common-mode filter 4700pF, PWM signals are input from microcomputer by using opto-couplers
15V single power supply, Test is performed with IM
Test conditions
VCC=300V, VD=15V, Ta=25°C, no load
Scheme of applying noise: From AC line (R, S, T), Period T=16ms, Pulse width tw=0.05-1μs, input in random.
3.3.2 Countermeasures and Precautions
DIPIPM improves noise withstand capabilities by means of reducing parts quantity, lowering internal wiring
parasitic inductance, and reducing leakage current. But when the noise affects on the control terminals of DIPIPM (due
to no good wiring pattern on PCB), the short circuit or malfunction of SC protection may occur. In that case, the
countermeasures are recommended.
UP
P
VP1
C2
Insert the RC filter
HVIC
C2
+
VUFB
U
VUFS
VP
VP1
Increase the capacitance of
C2 and locate it as close to
the terminal as possible
C2
C2
+
HVIC
VVFB
V
VVFS
WP
C2
MCU
+
C2
VP1
VPC
M
HVIC
VWFB
W
+
VWFS
C3
UN
NU
VN
WN
CFO
NV
LVIC
Fo
VOT
NW
15V
Increase the capacitance of
C4 with keeping the same
time constant R1·C4, and
locate the C4 as close to the
terminal as possible.
VN1
+
C2
VNC
CIN
C4
VSC
R1
Sense
resistor
N1
Fig.3-19 Example of countermeasures
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<Dual-In-Line Package Intelligent Power Module>
600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
3.3.3 Static Electricity Withstand Capability
DIPIPM has been confirmed to be with +/-200V or more withstand capability against static electricity from the
following tests shown in Fig.3-20 and Fig.3-21. The results (typical data) are described in Table 3-4
R=0Ω
LVIC
R=0Ω
VN1
UN
VN
WN
HVIC
VP1
VUFB
UP
Ho
VNC
VPC
VUFS
Fig.3-20 VN1 terminal Surge Test circuit(VN1 terminal)
Fig.3-21 VP1 terminal Surge Test circuit(VP1 terminal)
C=200pF
C=200pF
Conditions: Surge voltage increases by degree and only one-shot surge pulse is impressed at each surge voltage.
(Limit voltage of surge simulator: ±4.0kV, Judgment method; change in V-I characteristic)
Table 3-4 Typical ESD capability for PS21A7A and PS21A79
[Control terminal part]
For control part, since both have same circuit in the control IC, they have same capability.
Terminals
UP, VP, WP-VPC
VP1 - VNC
VUFB-VUFS, VVFB-VVFS,VWFB-VWFS
UN, VN, WN-VNC
VN1-VNC
CIN-VNC
Fo-VNC
CFO-VNC
VOT-VNC
+
1.6
3.6
4.0 or more
0.7
4.0 or more
0.8
1.5
1.3
0.9
1.7
3.7
4.0 or more
1.6
4.0 or more
1.0
2.4
1.7
2.5
[Power terminal part for PS21A7A]
Terminals
VSC-VNC*
P-NU, NV, NW
U-NU, V-NV, W-NW
+
0.4
4.0 or more
4.0 or more
0.5
4.0 or more
4.0 or more
[Power terminal part for PS21A79]
Terminals
+
VSC-VNC*
0.5
1.1
P-NU, NV, NW
4.0 or more
4.0 or more
U-NU, V-NV, W-NW
4.0 or more
4.0 or more
* VSC terminal (IGBT sense) is connected to the power chip inside the module.
Publication Date : October 2012
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<Dual-In-Line Package Intelligent Power Module>
600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
CHAPTER 4 Bootstrap Circuit Operation
4.1 Bootstrap Circuit Operation
For three phase inverter circuit driving, normally four isolated control supplies (three for P-side driving and one for
N-side driving) are necessary. But using floating control supply with bootstrap circuit can reduce the number of
isolated control supplies from four to one (N-side control supply).
Bootstrap circuit consists of a bootstrap diode(BSD), a bootstrap capacitor(BSC) and a current limiting resistor.
It uses the BSC as a control supply for driving P-side IGBT. The BSC supplies gate charge when P-side IGBT
turning ON and circuit current of logic circuit on P-side driving IC. (Fig.4-2) Since a capacitor is used as substitute
for isolated supply, its supply capability is limited. This floating supply driving with bootstrap circuit is suitable for
small supply current products like DIPIPM.
Charge consumed by driving circuit is re-charged from N-side 15V control supply to BSC via current limiting
resistor and BSD when voltage of output terminal (U, V or W) goes down to GND potential in inverter operation. But
there is the possibility that enough charge doesn't perform due to the conditions such as switching sequence,
capacitance of BSC, limiting resistance and so on. Deficient charge leads to low voltage of BSC and might work
under voltage protection (UV). This situation makes the loss of P-side IGBT increase by low gate voltage or stop
switching. So it is necessary to consider and evaluate enough for designing bootstrap circuit. For more detail
information about driving by the bootstrap circuit, refer the DIPIPM application note "Bootstrap Circuit Design
Manual"
The circuit current characteristics in switching situation of P-side IGBT are described below.
Current limiting
resistor
Bootstrap diode
(BSD)
BSC
+
P-side
IGBT
VP1
VD=15V
N-side
IGBT
VN1
LVIC
N-side
FWDi
VPC
P(Vcc)
+
Gate Drive
U,V,W
VFS
↑High voltage area
VFB
Logic & UV
protection
P-side
FWDi
Level Shift
Low voltage area
Level Shift
VPC
VFB
BSD
15V
P(Vcc)
HVIC
VP1
Bootstrap capacitor
(BSC)
P-side
IGBT
P-side
FWDi
VFS
U,V,W
Voltage of VFS that is reference voltage of BSC swings between
VCC and GND level. If voltage of BSC is lower than 15V when
VFS becomes to GND potential, BSC is charged from 15V N-side
control supply.
VNC
N(GND)
Fig.4-1 Bootstrap Circuit Diagram
Fig.4-2 Bootstrap Circuit Diagram
Publication Date : October 2012
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<Dual-In-Line Package Intelligent Power Module>
600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
4.2 Bootstrap Supply Circuit Current at Switching State
Bootstrap supply circuit current IDB at steady state is maximum 0.55mA for 600V Large DIPIPM Ver.4 series. But
at switching state, because gate charge and discharge are repeated by switching, the circuit current will exceed
0.55mA and increases proportional to carrier frequency. For reference, Fig.4-3~4-4 show the circuit current IDB for
P-side IGBT driving supply - carrier frequency fc typical characteristics for each products. (Conditions:
VD=VDB=15V, Tj=125°C, IGBT ON Duty=10, 30, 50, 70, 90%)
Circuit current (μA)
6000
5000
4000
10%
30%
50%
70%
90%
3000
2000
1000
0
0
5
10
15
20
Carrier frequency (kHz)
Fig.4-3 IDB vs. Carrier frequency for PS21A7A
Circuit current (μA)
4000
3500
3000
2500
10%
30%
50%
70%
90%
2000
1500
1000
500
0
0
10
5
15
20
Carrier frequency (kHz)
Fig.4-4 IDB vs. Carrier frequency for PS21A79
4.3 Note for designing the bootstrap circuit
When each device for bootstrap circuit is designed, it is necessary to consider various conditions such as
temperature characteristics, change by lifetime, variation and so on. Note for designing these devices are listed as
below. For more detail information about driving by the bootstrap circuit, refer the DIPIPM application note "Bootstrap
Circuit Design Manual"
(1) Bootstrap capacitor
Electrolytic capacitors are used for BSC generally. And recently ceramic capacitors with large capacitance are also
applied. But DC bias characteristic of the ceramic capacitor when applying DC voltage is considerably different from
that of electrolytic capacitor. (Especially large capacitance type) Some differences of capacitance characteristics
between electrolytic and ceramic capacitors are listed in Table 4-1.
Publication Date : October 2012
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<Dual-In-Line Package Intelligent Power Module>
600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
Table 4-1 Differences of capacitance characteristics between electrolytic and ceramic capacitors
Ceramic capacitor
Electrolytic capacitor
(large capacitance type)
• Aluminum type:
Different due to temp. characteristics rank
Temperature
Low temp.: -10% High temp: +10%
Low temp.: -5%~0%
characteristics
• Conductive polymer aluminum solid type:
High temp.: -5%~-10%
(Ta:-20~ 85°C)
Low temp.: -5% High temp: +10%
(in the case of B,X5R,X7R ranks)
DC bias
characteristics
(Applying DC15V)
Different due to temp. characteristics,
rating voltage, package size and so on
-70%~-15%
Nothing within rating voltage
DC bias characteristic of electrolytic capacitor is not matter. But it is necessary to note ripple capability by repetitive
charge and discharge, life time which is greatly affected by ambient temperature and so on. Above characteristics
are just example data which are obtained from the WEB, please refer to the capacitor manufacturers about detailed
characteristics.
(2) Bootstrap diode
It is recommended for BSD to have same or higher blocking voltage with collector-emitter voltage VCES of IGBT in
DIPIPM. (i.e. 600V or more is needed in the case of 600V DIPIPM.) And its recovery time trr should be less than
100ns. (Fast recovery type)
Also it is highly recommended to apply the high quality product such as small variations of blocking
voltage. If BSD broke by impressed overvoltage and shorted, it leads to the control ICs over voltage destruction
because DC-link voltage (Vcc) is impressed upon low voltage area of control ICs. Then DIPIPM will lose various
functions like protection and gate driving and it may lead to serious system destruction.
(3) Current limiting resistor
When designing limiting resistor, it is important to note its power rating, surge withstand capability (there is the
possibility that surge may be impressed on the resistor when switching ON or OFF timing) and so on.
Especially if small chip type resistor is applied, it is recommended to select anti-surge designed type. For detailed
information, please refer to the resistor manufacturer.
Publication Date : October 2012
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<Dual-In-Line Package Intelligent Power Module>
600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
CHAPTER5 PACKAGE HANDLING
5.1 Packaging Specification
(44)
(22)
Quantity:
6pcs per 1 tube
Plastic Tube
DIPIPM
(520)
5 columns
Total amount in one box (max):
Tube Quantity: 5 × 6=30pcs
IPM Quantity: 30 × 6=180pcs
6 stages
When it isn't fully filled by tubes at
top stage, cardboard spacers or
empty tubes are inserted for filling
the space of top stage.
(230)
(175)
Weight (max):
About 46g per 1pcs
About 380g per 1tube
About 13kg per 1box
(545)
Packaging box
Spacers are inserted into the top and bottom of the box. If there is some space on top of the box, additional buffer
materials are also inserted.
Fig.5-1 Packaging Specification
Publication Date : October 2012
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<Dual-In-Line Package Intelligent Power Module>
600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
5.2 Handling Precautions
！
Cautions
Transportation
·Put package boxes in the correct direction. Putting them upside down, leaning them or giving
them uneven stress might cause electrode terminals to be deformed or resin case to be
damaged.
·Throwing or dropping the packaging boxes might cause the devices to be damaged.
·Wetting the packaging boxes might cause the breakdown of devices when operating. Pay
attention not to wet them when transporting on a rainy or a snowy day.
Storage
·We recommend temperature and humidity in the ranges 5-35°C and 45-75%, respectively, for
the storage of modules. The quality or reliability of the modules might decline if the storage
conditions are much different from the above.
Long storage
·When storing modules for a long time (more than one year), keep them dry. Also, when using
them after long storage, make sure that there is no visible flaw, stain or rust, etc. on their
exterior.
Surroundings
·Keep modules away from places where water or organic solvent may attach to them directly
or where corrosive gas, explosive gas, fine dust or salt, etc. may exist. They might cause
serious problems.
Flame
resistance
·The epoxy resin of case material is flame-resistant type (UL standard 94V-0), but they are not
noninflammable.
Static electricity
·ICs and power chips with MOS gate structure are used for the DIPIPM power modules.
Please keep the following notices to prevent modules from being damaged by static
electricity.
(1)Precautions against the device destruction caused by the ESD
The ESD of human bodies and packaging and/or excessive voltage applied across the gate to
emitter may damage and destroy devices. The basis of anti-electrostatic is to inhibit
generating static electricity possibly and quick dissipation of the charged electricity.
*Containers that charge static electricity easily should not be used for transit and for storage.
*Terminals should be always shorted with a carbon cloth or the like until just before using the
module. Never touch terminals with bare hands.
*Should not be taking out DIPIPM from tubes until just before using DIPIPM and never touch
terminals with bare hands.
*During assembly and after taking out DIPIPM from tubes, always earth the equipment and
your body. It is recommended to cover the work bench and its surrounding floor with earthed
conductive mats.
*When the terminals are open on the printed circuit board with mounted modules, the modules
might be damaged by static electricity on the printed circuit board.
*If using a soldering iron, earth its tip.
(2)Notice when the control terminals are open
*When the control terminals are open, do not apply voltage between the collector and emitter.
It might cause malfunction.
*Short the terminals before taking a module off.
Publication Date : October 2012
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<Dual-In-Line Package Intelligent Power Module>
600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
Revision Record
Rev.
Date
1
08/31/2011
2
10/15/2012
Revised Points
New
P.14 Fig.2-11
VOT output vs. LVIC temperature
P.19 Table 2-14
Detailed description of input and output terminals
P.23 Section 3.1.2 Interface Circuit (Direct Coupling Interface example)
P.24 Section 3.1.3 Interface Circuit (Opto-coupler Isolated Interface)
P.38 Chapter 4
Bootstrap Circuit operation
Publication Date : October 2012
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<Dual-In-Line Package Intelligent Power Module>
600V LARGE DIPIPM Ver.4 Series APPLICATION NOTE
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more
reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead
to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit
designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of
non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
•These materials are intended as a reference to assist our customers in the selection of the Mitsubishi
semiconductor product best suited to the customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
•Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s
rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application
examples contained in these materials.
•All information contained in these materials, including product data, diagrams, charts, programs and algorithms
represents information on products at the time of publication of these materials, and are subject to change by
Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore
recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric
Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or
errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including
the Mitsubishi Semiconductor home page (http://www.MitsubishiElectric.com/).
•When using any or all of the information contained in these materials, including product data, diagrams, charts,
programs, and algorithms, please be sure to evaluate all information as a total system before making a final
decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no
responsibility for any damage, liability or other loss resulting from the information contained herein.
•Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system
that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric
Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product
contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical,
aerospace, nuclear, or undersea repeater use.
•The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part
these materials.
•If these products or technologies are subject to the Japanese export control restrictions, they must be exported
under a license from the Japanese government and cannot be imported into a country other than the approved
destination.
Any diversion or re-export contrary to the export control laws and regulations of Japan and/or the country of
destination is prohibited.
•Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for
further details on these materials or the products contained therein.
© 2012 MITSUBISHI ELECTRIC CORPORATION. ALL RIGHTS RESERVED.
DIPIPM and CSTBT are registered trademarks of MITSUBISHI ELECTRIC CORPORATION.
Publication Date : October 2012
44