MITSUBISHI PS22A73

< Dual-In-Line Package Intelligent Power Module >
PS22A73
TRANSFER MOLDING TYPE
INSULATED TYPE
OUTLINE
MAIN FEATURES AND RATINGS
● 3 phase DC/AC inverter
● 1200V / 10A
● Built-in LPT-CSTBT (5th generation IGBT)
● Insulated transfer molding package
● N-side IGBT open emitter
APPLICATION
● AC 400V class motor control
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS
● For P-side
: Drive circuit, High voltage high-speed level shifting, Control supply under-voltage (UV) protection
● For N-side
: Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC)
● Fault signaling : Corresponding to SC fault (N-side IGBT), UV fault (N-side supply)
● Temperature output : Outputting LVIC temperature by analog signal
● Input interface : 5V line, Schmitt trigger receiver circuit (High Active)
● UL Recognized : UL1557 File E80276
INTERNAL CIRCUIT
VUFB
VUFS
P
HVIC1
IGBT1
VP1
U
Di1
Ho
U
VVFB
VVFS
HVIC2
IGBT2
VP1
VP
Di2
Ho
V
VWFB
VWFS
HVIC3
VP1
WP
IGBT3
Di3
Ho
W
VPC
LVIC
IGBT4
Di4
UOUT
NU
VN1
IGBT5
Di5
VOUT
NV
UN
VN
WN
IGBT6
Di6
WOUT
NW
Fo
VOT
VNC
CFO
CIN Vsc
Publication Date : January 2012
1
< Dual-In-Line Package Intelligent Power Module >
PS22A73
TRANSFER MOLDING TYPE
INSULATED TYPE
MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted)
INVERTER PART
Symbol
VCC
VCC(surge)
VCES
±IC
±ICP
PC
Tj
Parameter
Supply voltage
Supply voltage (surge)
Collector-emitter voltage
Each IGBT collector current
Each IGBT collector current (peak)
Collector dissipation
Junction temperature
Condition
Applied between P-NU,NV,NW
Applied between P-NU,NV,NW
TC= 25°C
TC= 25°C, up to 1ms
TC= 25°C, per 1 chip
Ratings
900
1000
1200
10
20
66.2
-20~+150
Unit
V
V
V
A
A
W
°C
Ratings
20
20
-0.5~VD+0.5
-0.5~VD+0.5
1
-0.5~VD+0.5
Unit
V
V
V
V
mA
V
Ratings
Unit
800
V
-20~+100
-40~+125
°C
°C
2500
Vrms
CONTROL (PROTECTION) PART
Symbol
VD
VDB
VIN
VFO
IFO
VSC
Parameter
Control supply voltage
Control supply voltage
Input voltage
Fault output supply voltage
Fault output current
Current sensing input voltage
Condition
Applied between VP1-VPC, VN1-VNC
Applied between VUFB-VUFS, VVFB-VVFS, VWFB-VWFS
Applied between UP, VP, WP-VPC, UN, VN, WN-VNC
Applied between FO-VNC
Sink current at FO terminal
Applied between CIN-VNC
TOTAL SYSTEM
Symbol
TC
Tstg
Parameter
Self protection supply voltage limit
(Short circuit protection capability)
Module case operation temperature
Storage temperature
Viso
Isolation voltage
VCC(PROT)
Condition
VD = 13.5~16.5V, Inverter Part
Tj = 125°C, non-repetitive, up to 2μs
(Note 1)
60Hz, Sinusoidal, AC 1min, between connected all pins
and heat sink plate
Note 1: Tc measurement point is described in Fig.1.
Fig. 1: TC MEASUREMENT POINT
Measurement point for Tc
THERMAL RESISTANCE
Symbol
Rth(j-c)Q
Rth(j-c)F
Parameter
Junction to case thermal
resistance
(Note 2)
Condition
Inverter IGBT part (per 1/6 module)
Inverter FWDi part (per 1/6 module)
Min.
-
Limits
Typ.
-
Max.
1.51
1.78
Unit
K/W
K/W
Note 2: Grease with good thermal conductivity and long-term endurance should be applied evenly with about +100μm~+200μm on the contacting surface of
DIPIPM and heat sink. The contacting thermal resistance between DIPIPM case and heat sink Rth(c-f) is determined by the thickness and the thermal
conductivity of the applied grease. For reference, Rth(c-f) is about 0.2K/W (per 1/6 module, grease thickness: 20μm, thermal conductivity: 1.0W/m•k).
Publication Date : January 2012
2
< Dual-In-Line Package Intelligent Power Module >
PS22A73
TRANSFER MOLDING TYPE
INSULATED TYPE
ELECTRICAL CHARACTERISTICS (Tj = 25°C, unless otherwise noted)
INVERTER PART
Symbol
VCE(sat)
VEC
ton
tC(on)
toff
tC(off)
trr
ICES
Parameter
Condition
Collector-emitter saturation
voltage
VD=VDB = 15V, VIN= 5V, IC= 10A
FWDi forward voltage
VIN= 0V, -IC= 10A
Switching times
VCC= 600V, VD= VDB= 15V
IC= 10A, Tj= 125°C, VIN= 0↔5V
Inductive Load (upper-lower arm)
Collector-emitter cut-off
current
VCE=VCES
Tj= 25°C
Tj= 125°C
Tj= 25°C
Tj= 125°C
Min.
0.50
-
Limits
Typ.
1.90
2.00
2.20
1.20
0.60
2.40
0.60
0.50
-
Max.
2.60
2.70
2.80
1.90
0.90
3.50
0.90
1
10
Min.
-
Limits
Typ.
-
Max.
5.60
5.60
1.10
1.10
17
-
-
Unit
V
V
μs
μs
μs
μs
μs
mA
CONTROL (PROTECTION) PART
Symbol
Parameter
ID
Circuit current
ISC
Short circuit trip level
UVDBt
P-side Control supply
under-voltage
protection(UV)
N-side Control supply
under-voltage
protection(UV)
UVDt
UVDr
VFOH
VFOL
tFO
IIN
Vth(on)
Vth(off)
VOT
VD=15V, VIN=0V
VD=15V, VIN=5V
VD=VDB=15V, VIN=0V
Each part of VUFB-VUFS,
VVFB-VVFS, VWFB-VWFS
VD=VDB=15V, VIN=5V
-20°C≤Tj≤125°C, Rs= 107Ω (±1%),
Not connecting outer shunt resistors to
NU,NV,NW terminals
Trip level
Tj ≤125°C
Reset level
Total of VP1-VPC, VN1-VNC
IDB
UVDBr
Condition
Fault output voltage
Fault output pulse width
Input current
ON threshold voltage
OFF threshold voltage
Temperature output
Tj ≤125°C
(Note 3)
Unit
mA
A
10.0
-
12.0
V
10.5
-
12.5
V
Trip level
10.3
-
12.5
V
Reset level
10.8
-
13.0
V
4.9
1.6
0.70
0.8
3.57
2.4
1.00
3.63
0.95
1.50
3.5
3.69
V
V
ms
mA
VSC = 0V, FO terminal pulled up to 5V by 10kΩ
VSC = 1V, IFO = 1mA
CFO=22nF
VIN = 5V
(Note 4)
Applied between UP, VP, WP, UN, VN, WN-VNC
(Note 5)
LVIC temperature = 85°C
V
V
Note 3: Short circuit protection detects sense current divided from main current at N-side IGBT and works for N-side IGBT only. In the case that outer shunt resistor is
inserted into main current path, protection current level ISC changes. For details, please refer the application note for this DIPIPM.
Note 4: Fault signal is output when short circuit or N-side control supply under-voltage protection works. The fault output pulse-width tFO depends on the capacitance of
CFO. (CFO (typ.) = tFO x (9.1 x 10-6) [F])
Note 5: DIPIPM doesn't shut down IGBTs and output fault signal automatically when temperature rises excessively. When temperature exceeds the protective level that
user defined, controller (MCU) should stop the DIPIPM immediately. This output might exceed 5V when temperature rises excessively, so it is recommended to
insert a clamp Di between controller supply (e.g. 5V) and VOT output for overvoltage protection. Temperature of LVIC vs. VOT output characteristics is described in
Fig.2
Publication Date : January 2012
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< Dual-In-Line Package Intelligent Power Module >
PS22A73
TRANSFER MOLDING TYPE
INSULATED TYPE
Fig. 2 Temperature of LVIC vs. VOT Output Characteristics
5.0
Max.
Typ.
4.5
Min.
V OT output (V)
4.0
3.69
3.63
3.57
3.5
3.0
2.5
40
45
50
55
60
65
70
75
80
85
90
LVIC temperature (°C)
Please refer the application note about the usage of VOT too.
Publication Date : January 2012
4
95
100
105
110
115
120
125
130
< Dual-In-Line Package Intelligent Power Module >
PS22A73
TRANSFER MOLDING TYPE
INSULATED TYPE
MECHANICAL CHARACTERISTICS AND RATINGS
Parameter
Condition
Mounting torque
Terminal pulling strength
Terminal bending strength
Mounting screw : M4
Load 19.6N
Load 9.8N, 90deg. bend
Recommended 1.18N·m
EIAJ-ED-4701
EIAJ-ED-4701
Min.
0.98
10
2
Limits
Typ.
1.18
-
-
46
-
g
-50
-
100
μm
Weight
Heat-sink flatness
(Note 6)
Unit
Max.
1.47
-
N·m
s
times
Note 6: Measurement point of heat-sink flatness
RECOMMENDED OPERATION CONDITIONS
Symbol
Parameter
VCC
VD
VDB
ΔVD, ΔVDB
tdead
fPWM
Supply voltage
Control supply voltage
Control supply voltage
Control supply variation
Arm shoot-through blocking time
PWM input frequency
IO
Allowable r.m.s. current
Min.
350
13.5
13.0
-1
3.0
-
Limits
Typ.
600
15.0
15.0
-
Max.
800
16.5
18.5
+1
20
fPWM= 5kHz
-
-
5.3
fPWM= 15kHz
-
-
3.6
2.0
-
-
IC≤10A
2.5
-
-
10A<IC≤17A
2.9
-
-
-5.0
-20
-
+5.0
+125
Condition
Applied between P-NU, NV, NW
Applied between VP1-VPC, VN1-VNC
Applied between VUFB-VUFS, VVFB-VVFS, VWFB-VWFS
For each input signal
TC ≤ 100°C, Tj ≤ 125°C
VCC = 600V, VD = 15V, P.F = 0.8,
Sinusoidal PWM
TC ≤ 100°C, Tj ≤ 125°C
(Note 7)
PWIN(on)
PWIN(off)
(Note 8)
Minimum input pulse width
350≤ VCC ≤ 800V, 13.5≤ VD ≤ 16.5V,
13.0≤ VDB ≤ 18.5V, -20°C ≤ TC ≤ 100°C,
N line wiring inductance less than 10nH
(Note 9)
VNC
Tj
VNC variation
Junction temperature
Between VNC-NU, NV, NW (including surge)
Unit
V
V
V
V/μs
μs
kHz
Arms
μs
V
°C
Note 7: The allowable r.m.s. current value depends on the actual application conditions.
8: DIPIPM might not make response to the input on signal with pulse width less than PWIN (on).
9: IPM might make no response or delayed response (P-side IGBT only) for the input signal with off pulse width less than PWIN(off).
Please refer Fig. 3 about delayed response.
Fig. 3 About Delayed Response Against Shorter Input Off Signal Than PWIN(off) (P-side only)
P-side Control Input
Solid line
Internal IGBT Gate
Output Current Ic
Broken line
t2
t1
Publication Date : January 2012
5
…Off pulse width ≥ PWIN(off);
Turn on time t1 (Normal delay)
…Off pulse width < PWIN(off);
Turn on time t2 (Longer delay in some cases)
< Dual-In-Line Package Intelligent Power Module >
PS22A73
TRANSFER MOLDING TYPE
INSULATED TYPE
Fig. 4 Timing Charts of DIPIPM Protective Functions
[A] Short-Circuit Protection (N-side only with the external sense resistor and RC filter)
a1. Normal operation: IGBT ON and outputs current.
a2. Short circuit current detection (SC trigger)
(It is recommended to set RC time constant 1.5~2.0μs so that IGBT shut down within 2.0μs when SC occurs.)
a3. All N-side IGBT's gates are hard interrupted.
a4. All N-side IGBTs turn OFF.
a5. FO outputs with a fixed pulse width determined by the external capacitor CFO.
a6. Input = “L”: IGBT OFF
a7. Fo finishes output, but IGBTs don't turn on until inputting next ON signal (LH).
(IGBT of each phase can return to normal state by inputting ON signal to each phase.)
a8. Normal operation: IGBT ON and outputs current.
Lower-side control
input
a6
SET
RESET
Protection circuit state
a3
Internal IGBT gate
a4
SC trip current level
Output current Ic
a8
a1
a7
a2
Sense voltage of
the sense resistor
SC reference voltage
Delay by RC filtering
Error output Fo
a5
[B] Under-Voltage Protection (N-side, UVD)
b1. Control supply voltage VD exceeds under voltage reset level (UVDr), but IGBT turns ON by next ON signal (LH).
(IGBT of each phase can return to normal state by inputting ON signal to each phase.)
b2. Normal operation: IGBT ON and outputs current.
b3. VD level drops to under voltage trip level. (UVDt).
b4. All N-side IGBTs turn OFF in spite of control input condition.
b5. Fo outputs for the period determined by the capacitance CFO, but output is extended during VD keeps below UVDr.
b6. VD level reaches UVDr.
b7. Normal operation: IGBT ON and outputs current by next ON signal (LH).
Control input
RESET
Protection circuit state
Control supply voltage VD
UVDr
SET
b1
UVDt
b2
b3
b4
Output current Ic
Error output Fo
b5
Publication Date : January 2012
6
RESET
b6
b7
< Dual-In-Line Package Intelligent Power Module >
PS22A73
TRANSFER MOLDING TYPE
INSULATED TYPE
[C] Under-Voltage Protection (P-side, UVDB)
c1. Control supply voltage VDB rises. After the voltage reaches under voltage reset level UVDBr, IGBT turns on by next ON signal (LH).
c2. Normal operation: IGBT ON and outputs current.
c3. VDB level drops to under voltage trip level (UVDBt).
c4. IGBT of corresponding phase only turns OFF in spite of control input signal level, but there is no FO signal output.
c5. VDB level reaches UVDBr.
c6. Normal operation: IGBT ON and outputs current by next ON signal (LH).
Control input
RESET
SET
RESET
Protection circuit state
UVDBr
c1
Control supply voltage VDB
UVDBt
c5
c3
c2
c6
c4
Output current Ic
Error output Fo
Keep High-level (no fault output)
Fig. 5 MCU I/O Interface Circuit
5V line
10kΩ
DIPIPM
UP,VP,WP,UN,VN,WN
MCU
3.3kΩ(min)
Fo
VNC(Logic)
Note)
Design for input RC filter depends on the PWM control scheme used in the
application and the wiring impedance of the printed circuit board.
But because noisier in the application for 1200V, it is strongly recommended to
insert RC filter. (Time constant: over 100ns. e.g. 100Ω, 1000pF)
The DIPIPM input signal interface integrates a min. 3.3kΩ pull-down resistor.
Therefore, when using RC filter, be careful to satisfy turn-on threshold voltage
requirement.
Fo output is open drain type. It should be pulled up to the positive side of 5V or
15V power supply with the resistor that limits Fo sink current IFo under 1mA. In
the case of pulling up to 5V supply, over 5.1kΩ is needed. (10kΩ is
recommended.)
Fig. 6 Wiring Pattern around the Shunt Resistor in the Case of Inserting into Main Current Path
DIPIPM
Each wiring Inductance should be less than 10nH.
Inductance of a copper pattern with
length=17mm, width=3mm is about 10nH.
VNC
NU
NV
NW
N1
Shunt
resistors
GND wiring from VNC should
be connected close to the
terminal of shunt resistor.
Low inductance shunt resistor like surface mounted (SMD) type is recommended.
Protection current level ISC changes by inserting shunt resistor.
Publication Date : January 2012
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< Dual-In-Line Package Intelligent Power Module >
PS22A73
TRANSFER MOLDING TYPE
INSULATED TYPE
Fig. 7 Example of Application Circuit
UP(1)
R3
C5
IGBT1
VP1(3)
C2
P(40)
Di1
HVIC
VUFB(4)
D2
+
U(39)
VUFS(6)
C1 D1 C2
R3
C5
VP(7)
IGBT2
VP1(9)
C2
Di2
HVIC
VVFB(10)
D2
+
V(38)
VVFS(12)
C1 D1 C2
R3
C5
C2
WP(13)
VP1(14)
VPC(15)
IGBT3
Di3
HVIC
VWFB(16)
MCU
D2
+
M
W(37)
+
VWFS(18)
IGBT4
C1 D1 C2
Di4
C3
UN(27)
R3
C5
NU(36)
VN(28)
R3
C5
WN(29)
R3
IGBT5
Di5
C5
5V
CFO(25)
NV(35)
R2
Fo(26)
LVIC
IGBT6
Di6
VOT(23)
NW(34)
15V
VD
C1
VN1(21)
+ D1
C2
VNC(22)
C
VSC(19)
CIN(24)
B
C4
D
R1
Rs Sense
resistor
A
Control GND wiring
Note
N1 Power GND wiring
1 :If control GND and power GND are patterned by common wiring, it may cause malfunction by fluctuation of power GND level. It is recommended to connect
control GND and power GND at only a N1 point at which NU, NV, NW are connected to power GND line.
2 :It is recommended to insert a Zener diode D1 (24V/1W) between each pair of control supply terminals to prevent surge destruction.
3 :To prevent surge destruction, the wiring between the smoothing capacitor and the P, N1 terminals should be as short as possible. Generally inserting a
0.1μ~0.22μF snubber capacitor C3 between the P-N1 terminals is recommended.
4 :R1, C4 of RC filter for preventing protection circuit malfunction is recommended to select tight tolerance, temp-compensated type. The time constant R1C4
should be set so that SC current is shut down within 2μs. (1.5μs~2μs is general value.) SC interrupting time might vary with the wiring pattern, so the enough
evaluation on the real system is recommended. If R1 is too small, it may leads to delay of protection. So R1 should be min. 10 times larger resistance than Rs.
(100 times is recommended.)
5 :To prevent erroneous operation, the wiring of A, B, C should be as short as possible.
6 :For sense resistor, the variation within 1%(including temperature characteristics), low inductance type is recommended. And the over 1/8W is recommended,
but it is necessary to evaluate in your real system finally.
7 :To prevent erroneous SC protection, the wiring from VSC terminal to CIN filter should be divided at the point D that is close to the terminal of sense resistor.
And the wiring should be patterned as short as possible.
8 :All capacitors should be mounted as close to the terminals of the DIPIPM as possible. (C1: good temperature, frequency characteristic electrolytic type, and
C2: 0.22μ~2.0μF, good temperature, frequency and DC bias characteristic ceramic type are recommended.)
9 :Input drive is High-active type. There is a min. 3.3kΩ pull-down resistor in the input circuit of IC. To prevent malfunction, the wiring of each input should be as
short as possible. And it is strongly recommended to insert RC filter (e.g. R3=100Ω and C5=1000pF) and confirm the input signal level to meet the turn-on
and turn-off threshold voltage. Thanks to HVIC inside the module, direct coupling to MCU without any opto-coupler or transformer isolation is possible.
10 :Fo output is open drain type. It should be pulled up to MCU or control power supply (e.g. 5V,15V) by a resistor that makes IFo up to 1mA. (IFO is estimated
roughly by the formula of control power supply voltage divided by pull-up resistance. In the case of pulled up to 5V, 10kΩ (5kΩ or more) is recommended.)
11 :Error signal output width (tFo) can be set by the capacitor connected to CFO terminal. CFO(typ.) = tFo x (9.1 x 10-6) (F)
12 :High voltage (VRRM =1200V or more) and fast recovery diode (trr=less than 100ns or less) should be used for D2 in the bootstrap circuit.
13 :If high frequency noise superimposed to the control supply line, IC malfunction might happen and cause erroneous operation. To avoid such problem, voltage
ripple of control supply line should meet dV/dt ≤+/-1V/μs, Vripple≤2Vp-p.
14 :For DIPIPM, it isn't recommended to drive same load by parallel connection with other phase IGBT or other DIPIPM.
Publication Date : January 2012
8
< Dual-In-Line Package Intelligent Power Module >
PS22A73
TRANSFER MOLDING TYPE
INSULATED TYPE
Fig. 8 Package Outlines
Dimensions in mm
Publication Date : January 2012
9
< Dual-In-Line Package Intelligent Power Module >
PS22A73
TRANSFER MOLDING TYPE
INSULATED TYPE
Revision Record
Rev.
Date
Page
Revised contents
1
3/15/2011
-
2
1/31/2012
-
Change document format
7
Add Fig.6.
8
Revise notes.
New
Publication Date : January 2012
10
< Dual-In-Line Package Intelligent Power Module >
PS22A73
TRANSFER MOLDING TYPE
INSULATED TYPE
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Publication Date : January 2012
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