DS07-13749-3E

The following document contains information on Cypress products.
FUJITSU MICROELECTRONICS
DATA SHEET
DS07-13749-3E
16-bit Microcontroller
CMOS
F2MC-16LX MB90960 Series
MB90F962(S),
MB90V340E-101/102
■ DESCRIPTION
The MB90960-series is a 16-bit general-purpose microcontroller. Fujitsu Microelectronics now offers on-chip
Flash-ROM program memory up to 64 Kbytes.
The power supply (3 V) is supplied to the internal MCU core from an internal regulator circuit. This creates
a major advantage in terms of EMI and power consumption.
The unit features a 4 channel input capture unit, 1 channel 16-bit free-run timer, 2-channel LIN-UART, and
16-channel 8/10-bit A/D converter as the peripheral resource.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURES
• Clock
• Built-in PLL clock frequency multiplying circuit
• Machine clock (PLL clock) selectable from frequency division by 2 of oscillation clock or 1 to 6-multiplied
oscillation clock (4 MHz to 24 MHz when oscillation clock is 4 MHz) .
• Sub clock operation : Up to 50 kHz (devices without S-suffix only)
• Minimum instruction execution time : 41.7 ns (4 MHz oscillation clock and 6-multiplied PLL clock) .
(Continued)
For the information for microcontroller supports, see the following web site.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2007-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2009.11
MB90960 Series
• Instruction system optimized controllers
• 16 Mbytes CPU memory space : Internal 24-bit addressing
• Various data types (bit, byte, word, and long word)
• Various addressing modes (23 types)
• Enhanced signed instructions of multiplication/division and RETI
• Enhanced high-accuracy operations by 32-bit accumulator
• Instruction system for high-level language (C language) / multitask
• System stack pointer
• Enhanced pointer indirect instructions
• Barrel shift instructions
• Higher execution speed
• 4-byte instruction queue
• Powerful interrupt function
• Powerful interrupt function with 8 levels and 34 factors
• Corresponds to 8-channel external interrupt
• CPU-independent automatic data transfer function
• Expanded intelligent I/O service function (EI2OS) : 16 channels
• Low-power consumption mode
• Clock mode
PLL clock mode (a PLL clock that is a multiple of the oscillation clock is used to operate the CPU and peripheral
functions.)
Main clock mode (the main clock, with the oscillation clock frequency divided by 2 is used to operate the CPU
and peripheral functions.)
Sub clock mode (the sub clock is used to operate the CPU and peripheral functions.)
• Standby mode
Sleep mode (stops the operation clock to the CPU.)
Watch mode (operates the sub clock and watch timer only.)
Time-base timer mode (operates the oscillation clock, sub clock, time-base timer and watch timer only.)
Stop mode (stops the operates the oscillation clock and sub clock.)
• CPU intermittent operation mode
• I/O port
• General-purpose input/output ports (CMOS output)
- 34 ports (products without S-suffix)
- 36 ports (products with S-suffix)
• Sub clock pin (X0A, X1A)
• Yes : (external oscillator used), products without S-suffix
• No : products with S-suffix
• Timer
• Time-base timer, watch timer (products without S-suffix), watchdog timer : 1 channel
• 8/16-bit PPG timer : 8-bit × 4 channels or 16-bit × 2 channels
• 16-bit reload timer : 2 channels
• 16- bit input/output timer
- 16-bit free-run timer : 1 channel
- 16-bit input capture (ICU) : 4 channels
(Continued)
2
DS07-13749-3E
MB90960 Series
(Continued)
• LIN-UART : 2 channels
• Full-duplex double buffer
• Clock-asynchronous or clock-synchronous serial transfer
• DTP/External interrupt : 8 channels
• Module for activation of expanded intelligent I/O service (EI2OS) and generation of external interrupt by external
input.
• Delayed interrupt generator module
• Generates interrupt request for task switching.
• 8/10-bit A/D converter : 16 channels
• 8-bit and 10-bit resolution.
• Start by external trigger input.
• Conversion time : 3 μs (frequency, including sampling time at 24 MHz machine clock)
• Address match detection (program patch) function
• Detects address match for 6 address pointers.
• Changeable port input voltage level
• Automotive input level/CMOS Schmitt input level (initial value in single-chip mode is Automotive level).
DS07-13749-3E
3
MB90960 Series
■ PRODUCT LINEUP
Part number
MB90F962
MB90F962S
MB90V340E-101
MB90V340E-102
Parameter
Type
Flash memory product
Evaluation product
F2MC-16LX CPU
CPU
System clock
Sub clock pin
(X0A, X1A)
PLL clock multiplier ( × 1, × 2, × 3, × 4, × 6, 1/2 when PLL stops)
Minimum instruction execution time : 41.7 ns (4 MHz oscillation clock, PLL × 6)
Yes
No
Clock supervisor
ROM
RAM capacitance
Package
Power supply for
emulator*1
Operating
voltage range
Operating
temperature range
LIN-UART
8/10-bit
A/D Converter
Yes
No
Flash memory
64 Kbytes (60 Kbytes + 4 Kbytes Sectors)
External
3 Kbytes
30 Kbytes
LQFP-48P
PGA-299C
⎯
Yes
3.5 V to 5.5 V : at normal operation
(not using A/D converter and not doing
flash programming)
4.0 V to 5.5 V : at normal operation
5 V ± 10%
− 40 °C to + 125°C *2
⎯
2 channels
5 channels
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
16 channels
24 channels
10-bit or 8-bit resolution
Conversion time: Min. 3 μs includes sample time (per one channel)
2 channels
16-bit Reload Timer
5
2 channels
Signals an interrupt when overflowing.
Operating clock frequency: fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys = Machine clock frequency)
4 channels
16-bit Input Capture
3
Operation clock frequency: fsys/2 , fsys/2 , fsys/2 (fsys = Machine clock frequency)
Supports External Event Count function
1 channel
16-bit Free-run Timer
4 channels
1
8 channels
Maintains 16-bit free-run timer value by pin input (rising edge, falling edge, or both
edge), and generates interrupt
(Continued)
4
DS07-13749-3E
MB90960 Series
(Continued)
Part number
Parameter
8/16-bit
PPG timer
MB90F962
MB90F962S
2 channels (16-bit) / 4 channels (8-bit)
8-bit reload counters × 4
8-bit reload registers for
“L” pulse width × 4
8-bit reload registers for
“H” pulse width × 4
Corresponding
evaluation
product
MB90V340E-102
8 channels (16-bit) /
16 channels (8-bit)
8-bit reload counters × 16
8-bit reload registers for
“L” pulse width × 16
8-bit reload registers for
“H” pulse width × 16
Supports 8-bit and 16-bit operation modes.
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8bit prescaler + 8-bit reload counter.
Operating clock frequency: fsys, fsys/21, fsys/22, fsys/23, fsys/24, or 128 μs
@ fosc = 4 MHz
(fsys = Machine clock frequency, fosc = Oscillation clock frequency)
8 channels
External Interrupts
MB90V340E-101
16 channels
Can be used rising edge, falling edge, starting up by “H”/“L” level input, external
input,extended intelligent I/O services (EI2OS) .
MB90V340E-102
MB90V340E-101
⎯
*1 : It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01-E) is used. Please refer to the Emulator
operation manual for the details.
*2 : There is limited reliability if the product is used exceeding TA = +105°C. Contact the sales or support
representative for this case.
DS07-13749-3E
5
MB90960 Series
■ PIN ASSIGNMENT
• MB90F962 (S)
AVss
X1A/P41 *
X0A/P40 *
P44/FRCK0
P82/SIN0/INT14R/TIN2
P84/SCK0/INT15R
P83/SOT0/TOT2
P42/INT9R
P43
P86/SOT1
P87/SCK1
P85/SIN1
48
47
46
45
44
43
42
41
40
39
38
37
(TOP VIEW)
(LQFP-48P)
AVcc
1
36
P20
AVR
2
35
P21
P60/AN0
3
34
P22/PPGD(C)
P61/AN1
4
33
P23/PPGF(E)
P62/AN2
5
32
P24/IN0
P63/AN3
6
31
P25/IN1
P64/AN4
7
30
P26/IN2
P65/AN5
8
29
P27/IN3
P66/AN6/PPGC(D)
9
28
X1
16
17
18
19
20
21
22
23
24
P56/AN14/INT11
P57/AN15/INT13
MD2
MD1
MD0
RST
Vcc
Vss
P55/AN13/INT10
25
P54/AN12/TOT3/INT8
12
15
P50/AN8
P53/AN11/TIN3
C
14
X0
26
P52/AN10
27
11
13
10
P51/AN9
P67/AN7/PPGE(F)
P80/ADTG/INT12R
(FPT-48P-M26)
* : MB90F962: X0A, X1A
MB90F962S: P40, P41
6
DS07-13749-3E
MB90960 Series
■ PIN DESCRIPTION
Pin No.
Pin name
Circuit type
1
AVCC
I
2
AVR
⎯
LQFP-48P*
3 to 8
P60 to P65
AN0 to AN5
H
P66, P67
9, 10
AN6, AN7
H
12 to 14
F
H
16
Trigger input pin for A/D converter.
General-purpose I/O ports (I/O circuit type of P50 is different
from that of MB90V340E) .
General-purpose I/O port.
H
Analog input pin for A/D converter.
TIN3
Event input pin for reload timer 3.
P54
General-purpose I/O port.
AN12
TOT3
H
INT8
AN13 to AN15
Analog input pin for A/D converter.
Output pin for reload timer 3.
External interrupt request input pin for INT8.
P55 to P57
17 to 19
Analog input pins for A/D converter.
Analog input pins for A/D converter.
P53
AN11
Analog input pins for A/D converter.
External interrupt request input pin for INT12R.
AN8 to AN10
15
General-purpose I/O ports.
General-purpose I/O port.
INT12R
P50 to P52
Power (Vref+) input pin for A/D converter.
AVR should not exceed VCC.
Output pins for PPG.
P80
ADTG
VCC power input pin for analog circuit.
General-purpose I/O ports.
PPGC (D) ,
PPGE (F)
11
Function
General-purpose I/O ports.
H
INT10, INT11,
INT13
Analog input pins for A/D converter.
External interrupt request input pins for INT10, INT11, INT13.
20
MD2
D
Input pin for selecting operation mode.
21, 22
MD1, MD0
C
Input pins for selecting operation mode.
23
RST
E
Reset input pin.
24
VCC
⎯
Power input pin (3.5 V to 5.5 V) .
25
VSS
⎯
Power input pin (0 V) .
26
C
I
27
X0
28
X1
A
Capacity pin for stabilizing power supply. It should be connected to a higher than or equal to 0.1 μF ceramic capacitor.
Oscillation input pin.
Oscillation output pin.
(Continued)
DS07-13749-3E
7
MB90960 Series
Pin No.
LQFP-48P*
29 to 32
Pin name
P27 to P24
Circuit type
Function
G
General-purpose I/O ports.
The register can be set to select whether to use a pull-up resistor.
This function is enabled in single-chip mode.
IN3 to IN0
Event input pins for input capture 0 to 3.
P23, P22
General-purpose I/O ports.
The register can be set to select whether to use a pull-up resistor.
This function is enabled in single-chip mode.
33, 34
G
PPGF (E) ,
PPGD (C)
35, 36
37
38
39
40
41
P21, P20
P85
SIN1
P87
SCK1
P86
SOT1
P43
P42
INT9R
Output pins for PPG.
G
K
F
F
F
F
P83
42
SOT0
F
F
45
INT14R
Clock I/O pin for LIN-UART1.
General-purpose I/O port.
Serial data output pin for LIN-UART1.
General-purpose I/O port.
General-purpose I/O port.
External interrupt request input pin for INT9R.
Serial data output pin for LIN-UART0.
Clock I/O pin for LIN-UART0.
External interrupt request input pin for INT15R.
P82
SIN0
General-purpose I/O port.
General-purpose I/O port.
INT15R
44
Serial data input pin for LIN-UART1.
Output pin for reload timer 2.
P84
SCK0
General-purpose I/O port.
General-purpose I/O port.
TOT2
43
General-purpose I/O ports.
The register can be set to select whether to use a pull-up resistor.
This function is enabled in single-chip mode.
General-purpose I/O port.
K
Serial data input pin for LIN-UART0.
External interrupt request input pin for INT14R.
TIN2
Event input pin for reload timer 2.
P44
General-purpose I/O port (I/O circuit type of P44 is different from
that of MB90V340E) .
FRCK0
F
Free-run timer 0 clock input pin.
(Continued)
8
DS07-13749-3E
MB90960 Series
(Continued)
Pin No.
Pin name
Circuit type
Function
P40, P41
F
General-purpose I/O ports.
(products with S-suffix and MB90V340E-101)
X0A, X1A
B
X0A: Oscillation input pin for sub clock
X1A: Oscillation output pin for sub clock
(products without S-suffix and MB90V340E-102)
AVSS
I
VSS power input pin for analog circuit.
LQFP-48P*
46, 47
48
* : FPT-48P-M26
DS07-13749-3E
9
MB90960 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
X1
Oscillation circuit
High-speed oscillation feedback
resistor = approx. 1 MΩ
Xout
X0
Standby control signal
B
X1A
Oscillation circuit
Low-speed oscillation feedback
resistor = approx. 10 MΩ
Xout
X0A
Standby control signal
C
CMOS input
R
CMOS Hysteresis
inputs
D
• CMOS input
• No Pull-down
R
CMOS Hysteresis
inputs
Pull-down
resistor
E
CMOS hysteresis input
Pull-up resistor value : approx. 50 kΩ
Pull-up
resistor
R
CMOS Hysteresis
inputs
(Continued)
10
DS07-13749-3E
MB90960 Series
Type
Circuit
F
P-ch
Pout
N-ch
Nout
Remarks
• CMOS level output (IOL = 4 mA,
IOH = − 4 mA)
• CMOS hysteresis input (With the
standby-time input shutdown function)
• Automotive input (With the standbytime input shutdown function)
R
CMOS hysteresis input
Automotive input
Standby control for
input shutdown
G
Pull-up control
Pull-up
resistor
P-ch
P-ch
Pout
N-ch
Nout
• CMOS level output (IOL = 4 mA,
IOH = − 4 mA)
• CMOS hysteresis input (With the
standby-time input shutdown function)
• Automotive input (With the standbytime input shutdown function)
• Programmable pull-up resistor :
approx. 50 kΩ
R
CMOS hysteresis input
Automotive input
Standby control for
input shutdown
H
P-ch
Pout
N-ch
Nout
R
• CMOS level output (IOL = 4 mA,
IOH = − 4 mA)
• CMOS hysteresis input (With the
standby-time input shutdown function)
• Automotive input (With the standbytime input shutdown function)
• A/D analog input
CMOS hysteresis input
Automotive input
Standby control for
input shutdown
A/D analog input
(Continued)
DS07-13749-3E
11
MB90960 Series
(Continued)
Type
Circuit
I
Remarks
Power supply input protection circuit
P-ch
N-ch
K
P-ch
Pout
N-ch
Nout
• CMOS level output (IOL = 4 mA,
IOH = − 4 mA)
• CMOS input (With standby-time input
shutdown function)
• Automotive input (With the standbytime input shutdown function)
R
CMOS input
Automotive input
Standby control for
input shutdown
12
DS07-13749-3E
MB90960 Series
■ HANDLING DEVICES
Special care is required for the following when handling the device :
• Preventing latch-up
• Treatment of unused pins
• Using external clock
• Notes on during operation of PLL clock mode
• Power supply pins (VCC/VSS)
• Pull-up/down resistors
• Crystal oscillator circuit
• Turning-on sequence of power supply to A/D converter and analog inputs
• Connection of unused pins of A/D converter
• Notes on energization
• Stabilization of power supply voltage
• Initialization
• Correspondence with +105 °C or more
1. Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions :
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC and VSS.
• The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
When used, note that maximum rated voltage is not exceeded.
For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVR) exceed the digital
power-supply voltage.
2. Treatment of unused pins
Leaving unused input pins open may result in misbehavior or latch-up and possible permanent damage of the
device. Therefore, they must be pulled up or pulled down through resistors. In this case, those resistors should
be more than 2 kΩ .
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above
described connection.
3. Using external clock
To use external clock, drive the X0 (X0A) pin and leave X1 (X1A) pin open.
MB90960 Series
X0 (X0A)
Open
DS07-13749-3E
X1 (X1A)
13
MB90960 Series
4. Notes on during operation of PLL clock mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while
the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its
self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs.
5. Power supply pins (VCC/VSS)
If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential
are connected the inside of the device to prevent such malfunctioning as latch-up.
To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and
to keep the recommended DC characteristics specified as the total output current, be sure to connect the VCC
and VSS pins to the power supply and ground externally.
Connect VCC and VSS to the device from the power supply source with lowest possible impedance.
It is recommended to connect a capacitor of about 0.1 μF as a bypass capacitor between VCC and VSS in the
vicinity of VCC and VSS pins of the device.
VCC
VSS
VCC
VSS
VSS
VCC
MB90960
Series
VCC
VSS
VSS
VCC
6. Pull-up/down resistors
The MB90960 series does not support internal pull-up/down resistors (except Port 2 : programmable pull-up
resistors) . Use pull-up/down handling where needed.
7. Crystal oscillator circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and
make sure, to the utmost effort, that lines of oscillation circuit do not cross the lines of other circuits. It is highly
recommended to provide a printed circuit board artwork surrounding X0 and X1 pins with a ground area for
stabilizing the operation.
8. Turning-on sequence of power supply to A/D converter and analog inputs
Make sure to turn on the A/D converter power supply (AVCC, AVR) and analog inputs (AN0 to AN15) after turningon the digital power supply (VCC) . Turn-off the digital power supply after turning off the A/D converter power
supply and analog inputs. In this case, make sure that the voltage does not exceed AVR or AVCC (turning on/off
the analog and digital power supplies simultaneously is acceptable) .
14
DS07-13749-3E
MB90960 Series
9. Connection of unused pins of A/D converter if A/D converter is not used
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVR = VSS.
10. Notes on energization
To prevent malfunction of the internal voltage regulator , supply voltage profile while turning on the power supply
should be slower than 50 μs (0.2 V to 2.7 V) .
11. Stabilization of power supply voltage
If the power supply voltage varies acutely even within the operation assurance range of the VCC power supply
voltage, a malfunction may occur. The VCC power supply voltage must therefore be stabilized. As stabilization
guide lines, stabilize the power supply voltage so that VCC ripple fluctuations (peak to peak value) in the
commercial frequencies (50 Hz/60 Hz) fall within 10% of the standard VCC power supply voltage and the transient
fluctuation rate becomes 0.1 V/ms or less in instantaneous fluctuation for power supply switching.
12. Serial communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a board so as to avoid noise.
Retransmit the data if an error occurs because of applying the checksum to the last data in consideration of
receiving wrong data due to the noise.
13. Initialization
In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers,
turn on the power again.
14. Correspondence with +105 °C or more
There is limited reliability if the product is used exceeding TA = +105°C. Contact the sales or support
representative for this case.
DS07-13749-3E
15
MB90960 Series
■ BLOCK DIAGRAMS
• MB90F962(S)
X0
X1
RST
X0A*
X1A*
Clock
controller
F2MC-16LX
core
Input
capture
4 channels
16-bit
free-run
timer 0
IN0 to IN3
FRCK0
RAM
3 Kbytes
Baud rate
generator
(2 channels)
SOT0, SOT1
SCK0, SCK1
SIN0, SIN1
AVCC
AVSS
AN15 to AN0
AVR
LIN-UART
2 channels
Internal data bus
ROM
64 Kbytes
16-bit
reload
timer
2 channels
TIN2, TIN3
TOT2, TOT3
8/10-bit
A/D
converter
16 channels
ADTG
PPGF(E), PPGD(C),
PPGC(D), PPGE(F)
8/16-bit
PPG timer
4/2 channels
DTP/
External
interrupt
INT8, INT9R,
INT10, INT11,
INT12R, INT13,
INT14R, INT15R
* : Only for MB90F962
16
DS07-13749-3E
MB90960 Series
• MB90V340E-101/102
X0
X1
RST
X0A*
X1A*
Clock
controller
F2MC-16LX
core
16-bit
free-run
timer 0
RAM
30 Kbytes
baud rate
generator
AVCC
AVSS
AN23 to AN0
AVRH
AVRL
ADTG
Input
capture
8 channels
IN7 to IN0
Output
compare
8 channels
OUT7 to OUT0
(5 channels)
16-bit
free-run
timer 1
LIN-UART
5 channels
CAN
controller
3 channels
8/10-bit
A/D
converter
24 channels
Internal data bus
SOT4 to SOT0
SCK4 to SCK0
SIN4 to SIN0
FRCK0
16-bit
reload Timer
4 channels
FRCK1
RX2 to RX0
TX2 to TX0
TIN3 to TIN0
TOT3 to TOT0
AD15 to AD00
A23 to A16
ALE
DA01, DA00
10-bit
D/A converter
2 channels
PPGF to PPG0
8/16-bit
PPG timer
16/8 channels
SDA1, SDA0
SCL1, SCL0
I2C
interface
2 channels
DMA
External
bus
RD
WRL
WRH
HRQ
HAK
RDY
CLK
DTP/
External
interrupt
INT15 to INT8
(INT15R to INT8R)
INT7 to INT0
Clock
monitor
CKOT
* : Only for MB90V340E-102
DS07-13749-3E
17
MB90960 Series
■ MEMORY MAP
MB90V340E-101/102
MB90F962(S)
FFFFFFH
FFFFFFH
ROM (FF bank)
FF0000H
FEFFFFH
FF0000H
FEFFFFH
ROM (FF bank)
ROM (FE bank)
FE0000H
FDFFFFH
ROM (FD bank)
FD0000H
FCFFFFH
ROM (FC bank)
FC0000H
FBFFFFH
ROM (FB bank)
FB0000H
FAFFFFH
ROM (FA bank)
FA0000H
F9FFFFH
ROM (F9 bank)
F90000H
F8FFFFH
ROM (F8 bank)
F80000H
00FFFFH
008000H
007FFFH
007900H
0078FFH
010000H
00FFFFH
ROM (image
of FF bank)
Peripheral
008000H
007FFFH
007900H
ROM (image
of FF bank)
Peripheral
RAM 30 Kbytes
000100H
0000EFH
000000H
Peripheral
000CFFH
000100H
0000FFH
0000F0H
0000EFH
000000H
RAM 3 Kbytes
Peripheral
: Access prohibited
Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C
compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referred without using
the far specification in the pointer declaration.
For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.
The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00.
The image between FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and
FF7FFFH is visible only in bank FF.
18
DS07-13749-3E
MB90960 Series
■ I/O MAP
Address
Register
000000H,
000001H
000002H
Abbreviation
Access
Resource name
Initial value
R/W
Port 2
XXXXXXXXB
Reserved
Port 2 Data Register
000003H
PDR2
Reserved
000004H
Port 4 Data Register
PDR4
R/W
Port 4
XXXXXXXXB
000005H
Port 5 Data Register
PDR5
R/W
Port 5
XXXXXXXXB
000006H
Port 6 Data Register
PDR6
R/W
Port 6
XXXXXXXXB
R/W
Port 8
XXXXXXXXB
000007H
000008H
Reserved
Port 8 Data Register
000009H,
00000AH
PDR8
Reserved
00000BH Port 5 Analog Input Enable Register
ADER5
R/W
Port 5, A/D
11111111B
00000CH Port 6 Analog Input Enable Register
ADER6
R/W
Port 6, A/D
11111111B
00000DH
Reserved
00000EH Input Level Select Register 0
ILSR0
R/W
Port 2, 4, 5, 6
X000X0XXB
00000FH Input Level Select Register 1
ILSR1
R/W
Port 8
XXXXXXX0B
R/W
Port 2
00000000B
000010H,
000011H
000012H
Reserved
Port 2 Direction Register
000013H
DDR2
Reserved
000014H
Port 4 Direction Register
DDR4
R/W
Port 4
XXX00000B
000015H
Port 5 Direction Register
DDR5
R/W
Port 5
00000000B
000016H
Port 6 Direction Register
DDR6
R/W
Port 6
00000000B
R/W
Port 8
000000X0B
W
Port A
XXX00XXXB
R/W
Port 2
00000000B
000017H
000018H
Reserved
Port 8 Direction Register
000019H
00001AH Port A Direction Register
00001BH
to
00001DH
00001EH Port 2 Pull-up Control Register
00001FH
DDR8
Reserved
DDRA
Reserved
PUCR2
Reserved
(Continued)
DS07-13749-3E
19
MB90960 Series
Address
Register
Abbreviation
Access
Resource name Initial value
000020H Serial Mode Register 0
SMR0
W, R/W
00000000B
000021H Serial Control Register 0
SCR0
W, R/W
00000000B
RDR0/TDR0
R/W
00000000B
SSR0
R, R/W
00001000B
ECCR0
R, W,
R/W
000025H Extended Status Control Register 0
ESCR0
R/W
00000100B
000026H Baud Rate Generator Register 00
BGR00
R/W, R
00000000B
000027H Baud Rate Generator Register 01
BGR01
R/W, R
00000000B
000028H Serial Mode Register 1
SMR1
W, R/W
00000000B
000029H Serial Control Register 1
SCR1
W, R/W
00000000B
RDR1/TDR1
R/W
00000000B
SSR1
R, R/W
00001000B
ECCR1
R, W,
R/W
00002DH Extended Status Control Register 1
ESCR1
R/W
00000100B
00002EH Baud Rate Generator Register 10
BGR10
R/W, R
00000000B
00002FH Baud Rate Generator Register 11
BGR11
R/W, R
00000000B
000030H
to
00003AH
Reserved
000022H Reception/Transmission Data Register 0
000023H Serial Status Register 0
000024H
Extended Communication Control
Register 0
00002AH Reception/Transmission Data Register 1
00002BH Serial Status Register 1
00002CH
Extended Communication Control
Register 1
00003BH Address Detect Control Register 1
PACSR1
R/W
LIN-UART0
LIN-UART1
Address Match
Detection 1
000000XXB
000000XXB
00000000B
00003CH
to
000047H
Reserved
000048H PPGC Operation Mode Control Register
PPGCC
W, R/W
000049H PPGD Operation Mode Control Register
PPGCD
W, R/W
PPGCD
R/W
000000X0B
0X000XX1B
00004AH
PPGC/PPGD Count Clock Select
Register
00004BH
Reserved
00004CH PPGE Operation Mode Control Register
PPGCE
W, R/W
00004DH PPGF Operation Mode Control Register
PPGCF
W, R/W
PPGEF
R/W
00004EH
00004FH
PPGE/PPGF Count Clock Select
Register
0X000XX1B
16-bit PPG C/D
16-bit PPG E/F
0X000001B
0X000001B
000000X0B
Reserved
(Continued)
20
DS07-13749-3E
MB90960 Series
Address
Register
Abbreviation
Access
000050H Input Capture Control Status 0/1
ICS01
R/W
000051H Input Capture Edge 0/1
ICE01
R/W, R
000052H Input Capture Control Status 2/3
ICS23
R/W
000053H Input Capture Edge 2/3
ICE23
R
000054H
to
000063H
Resource name
Input Capture 0/1
Input Capture 2/3
Initial value
00000000B
XXX0X0XXB
00000000B
XXXXXXXXB
Reserved
000064H Timer Control Status 2
TMCSR2
R/W
000065H Timer Control Status 2
TMCSR2
R/W
000066H Timer Control Status 3
TMCSR3
R/W
000067H Timer Control Status 3
TMCSR3
R/W
000068H A/D Control Status 0
ADCS0
R/W
000XXXX0B
000069H A/D Control Status 1
ADCS1
R/W, W
0000000XB
00006AH A/D Data Register 0
ADCR0
R
00006BH A/D Data Register 1
ADCR1
R
00006CH A/D Converter Setting 0
ADSR0
R/W
00000000B
00006DH A/D Converter Setting 1
ADSR1
R/W
00000000B
00006EH
16-bit Reload Timer 2
16-bit Reload Timer 3
A/D Converter
00000000B
XXXX0000B
00000000B
XXXX0000B
00000000B
XXXXXX00B
Reserved
00006FH ROM Mirror Function Select
000070H
to
00009DH
ROMM
W
ROM Mirror
XXXXXXX1B
Reserved
00009EH Address Detect Control Register 0
PACSR0
R/W
Address Match
Detection 0
00000000B
00009FH Delayed Interrupt/Release Register
DIRR
R/W
Delayed Interrupt
generation module
XXXXXXX0B
LPMCR
W, R/W
Low-Power
consumption
Control Circuit
00011000B
CKSCR
R, R/W
Low-Power
consumption
Control Circuit
11111100B
0000A0H
Low-power Consumption Mode
Control Register
0000A1H Clock Selection Register
0000A2H
to
0000A7H
Reserved
0000A8H Watchdog Timer Control Register
WDTC
R, W
Watchdog Timer
XXXXX111B
0000A9H Time-base Timer Control Register
TBTC
W, R/W
Time-base Timer
1XX00100B
(Continued)
DS07-13749-3E
21
MB90960 Series
Address
Register
0000AAH Watch Timer Control Register
0000ABH
to
0000ADH
0000AEH Flash Control Status
0000AFH
Abbreviation
Access
Resource name
Initial value
WTC
R, R/W
Watch Timer
1X001000B
Flash Memory
000X0000B
Reserved
FMCS
R, R/W
Reserved
0000B0H Interrupt Control Register 00
ICR00
W, R/W
00000111B
0000B1H Interrupt Control Register 01
ICR01
W, R/W
00000111B
0000B2H Interrupt Control Register 02
ICR02
W, R/W
00000111B
0000B3H Interrupt Control Register 03
ICR03
W, R/W
00000111B
0000B4H Interrupt Control Register 04
ICR04
W, R/W
00000111B
0000B5H Interrupt Control Register 05
ICR05
W, R/W
00000111B
0000B6H Interrupt Control Register 06
ICR06
W, R/W
00000111B
0000B7H Interrupt Control Register 07
ICR07
W, R/W
0000B8H Interrupt Control Register 08
ICR08
W, R/W
0000B9H Interrupt Control Register 09
ICR09
W, R/W
00000111B
0000BAH Interrupt Control Register 10
ICR10
W, R/W
00000111B
0000BBH Interrupt Control Register 11
ICR11
W, R/W
00000111B
0000BCH Interrupt Control Register 12
ICR12
W, R/W
00000111B
0000BDH Interrupt Control Register 13
ICR13
W, R/W
00000111B
0000BEH Interrupt Control Register 14
ICR14
W, R/W
00000111B
0000BFH Interrupt Control Register 15
ICR15
W, R/W
00000111B
0000C0H
to
0000C9H
Interrupt Control
00000111B
00000111B
Reserved
0000CAH DTP/External Interrupt Enable 1
ENIR1
R/W
00000000B
0000CBH DTP/External Interrupt Source 1
EIRR1
R/W
XXXXXXXXB
0000CCH Detection Level Setting 1
ELVR1
R/W
0000CDH Detection Level Setting 1
ELVR1
R/W
00000000B
0000CEH External Interrupt factor Select
EISSR
R/W
00000000B
0000CFH PLL/Sub clock Control Register
PSCCR
W
0000D0H
to
0000FFH
External Interrupt 1
PLL
00000000B
XXXX0000B
Reserved
(Continued)
22
DS07-13749-3E
MB90960 Series
Address
Register
007900H
to
007917H
Abbreviation
Access
Resource name
Initial value
Reserved
007918H Reload Register LC
PRLLC
R/W
007919H Reload Register HC
PRLHC
R/W
00791AH Reload Register LD
PRLLD
R/W
00791BH Reload Register HD
PRLHD
R/W
XXXXXXXXB
00791CH Reload Register LE
PRLLE
R/W
XXXXXXXXB
00791DH Reload Register HE
PRLHE
R/W
00791EH Reload Register LF
PRLLF
R/W
00791FH Reload Register HF
PRLHF
R/W
XXXXXXXXB
007920H Input Capture 0
IPCP0
R
XXXXXXXXB
007921H Input Capture 0
IPCP0
R
007922H Input Capture 1
IPCP1
R
007923H Input Capture 1
IPCP1
R
XXXXXXXXB
007924H Input Capture 2
IPCP2
R
XXXXXXXXB
007925H Input Capture 2
IPCP2
R
007926H Input Capture 3
IPCP3
R
007927H Input Capture 3
IPCP3
R
XXXXXXXXB
00000000B
007928H
to
00793FH
TCDT0
R/W
007941H Timer Data 0
TCDT0
R/W
007942H Timer Control Status 0
TCCSL0
R/W
007943H Timer Control Status 0
TCCSH0
R/W
007944H
to
00794BH
00794DH
00794EH
00794FH
16-bit PPG C/D
16-bit PPG E/F
Input Capture 0/1
Input Capture 2/3
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Reserved
007940H Timer Data 0
00794CH
XXXXXXXXB
16-bit Free-run Timer
0
00000000B
00000000B
0XXXXXXXB
Reserved
Timer 2/Reload 2
TMR2/TMRLR2
Timer 3/Reload 3
TMR3/TMRLR3
007950H
to
0079DFH
R/W
R/W
R/W
R/W
16-bit Reload
Timer 2
XXXXXXXXB
16-bit Reload
Timer 3
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Reserved
(Continued)
DS07-13749-3E
23
MB90960 Series
(Continued)
Address
Register
Abbreviation
Access
Resource name
Initial value
0079E0H Detect Address Setting 0
PADR0
R/W
XXXXXXXXB
0079E1H Detect Address Setting 0
PADR0
R/W
XXXXXXXXB
0079E2H Detect Address Setting 0
PADR0
R/W
XXXXXXXXB
0079E3H Detect Address Setting 1
PADR1
R/W
XXXXXXXXB
Address Match
Detection 0
0079E4H Detect Address Setting 1
PADR1
R/W
0079E5H Detect Address Setting 1
PADR1
R/W
XXXXXXXXB
0079E6H Detect Address Setting 2
PADR2
R/W
XXXXXXXXB
0079E7H Detect Address Setting 2
PADR2
R/W
XXXXXXXXB
0079E8H Detect Address Setting 2
PADR2
R/W
XXXXXXXXB
0079E9H
to
0079EFH
XXXXXXXXB
Reserved
0079F0H Detect Address Setting 3
PADR3
R/W
XXXXXXXXB
0079F1H Detect Address Setting 3
PADR3
R/W
XXXXXXXXB
0079F2H Detect Address Setting 3
PADR3
R/W
XXXXXXXXB
0079F3H Detect Address Setting 4
PADR4
R/W
XXXXXXXXB
Address Match
Detection 1
0079F4H Detect Address Setting 4
PADR4
R/W
0079F5H Detect Address Setting 4
PADR4
R/W
XXXXXXXXB
0079F6H Detect Address Setting 5
PADR5
R/W
XXXXXXXXB
0079F7H Detect Address Setting 5
PADR5
R/W
XXXXXXXXB
0079F8H Detect Address Setting 5
PADR5
R/W
XXXXXXXXB
0079F9H
to
007FFFH
XXXXXXXXB
Reserved
Notes : • Initial value of “X” represents unknown value.
• Any write access to reserved addresses in I/O map should not be performed. A read access to reserved
addresses results in reading “X”.
24
DS07-13749-3E
MB90960 Series
■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt cause
EI2OS
corresponding
Interrupt vector
Interrupt control
register
Number
Address
Number
Address
Reset
N
#08
FFFFDCH
⎯
⎯
INT9 instruction
N
#09
FFFFD8H
⎯
⎯
Exception processing
N
#10
FFFFD4H
⎯
⎯
Reserved
N
#11
FFFFD0H
Reserved
N
#12
FFFFCCH
ICR00
0000B0H
Reserved
N
#13
FFFFC8H
Reserved
N
#14
FFFFC4H
ICR01
0000B1H
Reserved
N
#15
FFFFC0H
Reserved
N
#16
FFFFBCH
ICR02
0000B2H
Reserved
N
#17
FFFFB8H
Reserved
N
#18
FFFFB4H
ICR03
0000B3H
16-bit reload timer 2
Y1
#19
FFFFB0H
16-bit reload timer 3
Y1
#20
FFFFACH
ICR04
0000B4H
Reserved
N
#21
FFFFA8H
Reserved
N
#22
FFFFA4H
ICR05
0000B5H
PPG C/D
N
#23
FFFFA0H
PPG E/F
N
#24
FFFF9CH
ICR06
0000B6H
Time-base timer
N
#25
FFFF98H
External interrupt 8 to 11
Y1
#26
FFFF94H
ICR07
0000B7H
Watch timer
N
#27
FFFF90H
External interrupt 12 to 15
Y1
#28
FFFF8CH
ICR08
0000B8H
A/D converter
Y1
#29
FFFF88H
16-bit free-run timer 0
N
#30
FFFF84H
ICR09
0000B9H
Reserved
N
#31
FFFF80H
Reserved
N
#32
FFFF7CH
ICR10
0000BAH
Input capture 0 to 3
Y1
#33
FFFF78H
Reserved
N
#34
FFFF74H
ICR11
0000BBH
LIN-UART 0 reception
Y2
#35
FFFF70H
LIN-UART 0 transmission
Y1
#36
FFFF6CH
ICR12
0000BCH
LIN-UART 1 reception
Y2
#37
FFFF68H
LIN-UART 1 transmission
Y1
#38
FFFF64H
ICR13
0000BDH
(Continued)
DS07-13749-3E
25
MB90960 Series
(Continued)
Interrupt cause
EI2OS
corresponding
Interrupt vector
Number
Address
Reserved
N
#39
FFFF60H
Reserved
N
#40
FFFF5CH
Flash memory
N
#41
FFFF58H
Delayed interrupt generation module
N
#42
FFFF54H
Interrupt control
register
Number
Address
ICR14
0000BEH
ICR15
0000BFH
Y1 : Usable
Y2 : Usable, with EI2OS stop function
N : Unusable
Notes : • The peripheral resources sharing the ICR register have the same interrupt level.
• When 2 peripheral resources share the ICR register, only one can use extended intelligent I/O service
at a time.
• When either of the 2 peripheral resources sharing the ICR register specifies extended intelligent I/O
service, the other one cannot use interrupts.
26
DS07-13749-3E
MB90960 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Remarks
Min
Max
VCC
VSS − 0.3
VSS + 6.0
V
AVCC
VSS − 0.3
VSS + 6.0
V
VCC = AVCC*2
AVR
VSS − 0.3
VSS + 6.0
V
AVCC ≥ AVR*2
Input voltage*1
VI
VSS − 0.3
VSS + 6.0
V
*3
Output voltage*1
VO
VSS − 0.3
VSS + 6.0
V
*3
ICLAMP
−2.0
+2.0
mA
*4
Σ|ICLAMP|
⎯
40
mA
*4
IOL
⎯
15
mA
*4
“L” level average output current
IOLAV
⎯
4
mA
*4
“L” level maximum overall output current
ΣIOL
⎯
125
mA
*4
“L” level average overall output current
ΣIOLAV
⎯
40
mA
*4
IOH
⎯
−15
mA
*4
“H” level average output current
IOHAV
⎯
−4
mA
*4
“H” level maximum overall output current
ΣIOH
⎯
−125
mA
*4
“H” level average overall output current
ΣIOHAV
⎯
−40
mA
*4
Power consumption
PD
⎯
300
mW
Operating temperature
TA
−40
+105
°C
−40
+125
°C
−55
+150
°C
Power supply voltage*1
Maximum clamp current
Total Maximum clamp current
“L” level maximum output current
“H” level maximum output current
Storage temperature
TSTG
*5
(Continued)
DS07-13749-3E
27
MB90960 Series
(Continued)
*1 : This parameter is based on VSS = AVSS = 0 V.
*2 : Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the
analog inputs does not exceed AVCC when the power is switched on.
*3 : VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However, if the maximum
current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the
VI rating.
*4 : Applicable to pins : P20 to P27, P40 to P44, P50 to P57, P60 to P67, P80, P82 to P87
• Use within recommended operating conditions.
• Use at DC voltage (current) .
• The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is inputted when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting power supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Sample recommended circuits :
• Input/output equivalent circuits
Protective diode
VCC
Limiting
resistance
P-ch
+B input (0 V to 16 V)
N-ch
R
*5 : There is limited reliability if the product is used exceeding TA = +105°C. Contact the sales or support
representative for this case.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
28
DS07-13749-3E
MB90960 Series
2. Recommended Conditions
(VSS = AVSS = 0 V)
Parameter
Power supply voltage
Symbol
VCC,
AVCC
Smooth capacitor
CS
Operating temperature
TA
Value
Unit
Remarks
Min
Typ
Max
4.0
5.0
5.5
V
Under normal operation
3.5
5.0
5.5
V
Under normal operation when not using
the A/D converter and not Flash
programming.
3.0
⎯
5.5
V
Maintains RAM data in stop mode
Use a ceramic capacitor or capacitor of
better AC characteristics for the C pin.
Bypass capacitor at the VCC pin should
be greater than this capacitor.
0.1
⎯
1.0
μF
−40
⎯
+105
°C
−40
⎯
+125
°C
*
* : There is limited reliability if the product is used exceeding TA = +105°C. Contact the sales or support
representative for this case.
• C Pin Connection Diagram
C
CS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
DS07-13749-3E
29
MB90960 Series
3. DC Characteristics
(TA = −40 °C to +125 °C*1, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Parameter
Symbol
Pin
Condition
Value
Min
Typ
Max
Unit
Remarks
⎯
⎯
0.8 VCC
⎯
VCC + 0.3
V
Pin inputs if CMOS
hysteresis levels are
selected (except P82,
P85)
⎯
⎯
0.7 VCC
⎯
VCC + 0.3
V
P82, P85 inputs if
CMOS input levels are
selected
VIHA
⎯
⎯
0.8 VCC
⎯
VCC + 0.3
V
Pin inputs if
Automotive input
levels are selected
VIHR
⎯
⎯
0.8 VCC
⎯
VCC + 0.3
V
RST input pin (CMOS
hysteresis)
VIHM
⎯
⎯
VCC − 0.3
⎯
VCC + 0.3
V
MD input pin
VIHS
Input “H”
voltage
⎯
⎯
VSS − 0.3
⎯
0.2 VCC
V
Pin inputs if CMOS
hysteresis input levels
are selected (except
P82, P85)
⎯
⎯
VSS − 0.3
⎯
0.3 VCC
V
P82, P85 inputs if
CMOS input levels are
selected
VILA
⎯
⎯
VSS − 0.3
⎯
0.5 VCC
V
Pin inputs if
Automotive input
levels are selected
VILR
⎯
⎯
VSS − 0.3
⎯
0.2 VCC
V
RST input pin (CMOS
hysteresis)
VILM
⎯
⎯
VSS − 0.3
⎯
VSS + 0.3
V
MD input pin
Output “H”
voltage
VOH
⎯
VCC = 4.5 V,
IOH = −4.0 mA
VCC − 0.5
⎯
⎯
V
Output “L”
voltage
VOL
⎯
VCC = 4.5 V,
IOL = 4.0 mA
⎯
⎯
0.4
V
Input leak
current
IIL
⎯
VCC = 5.5 V,
VSS < VI < VCC
−1
⎯
+1
μA
Pull-up
resistance
RUP
P20 to P27,
RST
⎯
25
50
100
kΩ
Pull-down
resistance
RDOWN
MD2
⎯
25
50
100
kΩ
VILS
Input “L”
voltage
Except Flash memory
devices
(Continued)
30
DS07-13749-3E
MB90960 Series
(Continued)
Parameter
(TA = −40 °C to +125 °C*1, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Symbol
Pin
Input capacity
Value
Unit
Remarks
Min
Typ
Max
VCC = 5.0 V,
Internal frequency : 24 MHz,
At normal operation.
⎯
35
45
mA MB90F962(S)
VCC = 5.0 V,
Internal frequency : 24 MHz,
At writing Flash memory.
⎯
50
60
mA MB90F962(S)
VCC = 5.0 V,
Internal frequency : 24 MHz,
At erasing Flash memory.
⎯
50
60
mA MB90F962(S)
ICCS
VCC = 5.0 V,
Internal frequency : 24 MHz,
At sleep mode.
⎯
12
20
mA MB90F962(S)
ICTS
VCC = 5.0 V,
Internal frequency : 2 MHz,
At main timer mode
⎯
0.3
0.8
mA MB90F962(S)
VCC = 5.0 V,
Internal frequency : 24 MHz,
At PLL timer mode,
External frequency = 4 MHz
⎯
4
7
mA MB90F962(S)
ICCL
VCC = 5.0 V,
Internal frequency : 8 kHz,
At sub clock operation mode,
TA = + 25°C
⎯
40
100
μA
MB90F962 (S)
ICCLS
VCC = 5.0 V,
Internal frequency : 8 kHz,
At sub clock sleep mode,
TA = + 25°C
⎯
10
50
μA
MB90F962 (S)
ICCT
VCC = 5.0 V,
Internal frequency : 8 kHz,
At watch mode,
TA = + 25°C
⎯
8
30
μA
MB90F962 (S)
ICCH
VCC = 5.0 V,
At stop mode, TA = + 25°C
⎯
5
25
μA
MB90F962(S)
⎯
5
15
pF
ICC
Power supply
current*2
Condition
ICTSPLL6
CIN
VCC
Other than
AVCC,
AVSS, AVR,
VCC, VSS, C
⎯
*1 : There is limited reliability if the product is used exceeding TA = +105°C. Contact the sales or support
representative for this case.
*2 : The power supply current is measured with an external clock.
DS07-13749-3E
31
MB90960 Series
4. AC Characteristics
(1) Clock Timing
(TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Parameter
Symbol
Pin
Value
Min
Input clock rise and fall
time
Internal operating clock
frequency (machine clock)
Internal operating clock
cycle time (machine clock)
Remarks
1/2 when PLL stops,
When using an oscillation circuit
4
16
PLL × 1,
When using an oscillation circuit
4
12
PLL × 2,
When using an oscillation circuit
⎯
MHz
4
8
PLL × 3,
When using an oscillation circuit
4
6
PLL × 4,
When using an oscillation circuit
4
4
PLL × 6,
When using an oscillation circuit
3
24
1/2 when PLL stops,
When using an external clock
4
20
PLL × 1,
When using an external clock
4
12
PLL × 2,
When using an external clock
fC
⎯
MHz
4
8
PLL × 3,
When using an external clock
4
6
PLL × 4,
When using an external clock
4
4
PLL × 6,
When using an external clock
X0A, X1A
⎯
32.768
100
kHz
X0, X1
62.5
⎯
333
ns
When using an oscillation circuit
X0, X1
41.67
⎯
333
ns
When using an external clock
tCYLL
X0A, X1A
10
30.5
⎯
μs
When using sub clock
PWH, PWL
X0
10
⎯
⎯
ns
PWHL, PWLL
X0A
5
15.2
⎯
μs
tCR, tCF
X0
⎯
⎯
5
ns
fCP
⎯
1.5
⎯
24
MHz When using main clock
fCPL
⎯
⎯
8.192
50
kHz
When using sub clock
tCP
⎯
41.67
⎯
666
ns
When using main clock
tCPL
⎯
20
122.1
⎯
μs
When using sub clock
fCL
Input clock pulse width
Unit
16
X0, X1
Clock cycle time
Max
3
X0, X1
Clock frequency
Typ
tCYL
Duty ratio is about 30% to 70%.
When using external clock
*: There is limited reliability if the product is used exceeding TA = +105°C. Contact the sales or support
representative for this case.
32
DS07-13749-3E
MB90960 Series
• Clock Timing
tCYL
0.8 VCC
X0
0.2 VCC
PWH
PWL
tCF
tCR
tCYLL
0.8 VCC
X0A
0.2 VCC
PWHL
PWLL
tCF
DS07-13749-3E
tCR
33
MB90960 Series
• Guaranteed PLL Operation Range
Guaranteed operation range
Guaranteed PLL operation range (CS2=1)
Power supply voltage VCC (V)
5.5
Guaranteed A/D converter
operation range
4.5
3.5
Guaranteed PLL operation range (CS2=0)
1.5
4
8
20
24
Machine clock fCP (MHz)
Guaranteed operation range of MB90960 series
Machine clock fCP (MHz)
• CS2 (bit 0 in PSCCR register) = 0
x4 (CS=011)
x3 (CS=010)
x2 (CS=001)
20
Guaranteed oscillation frequency range
x1 (CS=000)
16
x1/2 (PLL off)
12
8
6
4
1.5
34
6
8 10 12
16
20
24
External clock fC (MHz)*
• CS2 (bit 0 in PSCCR register) = 1
x6 (CS=110)
x4 (CS=101)
Machine clock fCP (MHz)
24
x2 (CS=100)
Guaranteed oscillation frequency range
16
x1/2 (PLL off)
12
8
4
1.5
34
6
8 10 12
16
20
24
External clock fC (MHz)*
* : When using a crystal oscillator or a ceramic oscillator, the maximum oscillation clock frequency is 16 MHz.
External clock frequency and Machine clock frequency
34
DS07-13749-3E
MB90960 Series
(2) Reset Standby Input
(TA = −40 °C to +125 °C*1, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Parameter
Reset input
time
Symbol
tRSTL
Pin
Value
Unit
Remarks
Min
Max
500
⎯
ns
Under normal operation
⎯
μs
In stop mode
⎯
μs
In time-base timer mode
RST Oscillation time of oscillator*2 + 100 μs
100
*1: There is limited reliability if the product is used exceeding TA = +105°C. Contact the sales or support
representative for this case.
*2 : Oscillation time of oscillator is the time that the amplitude reaches 90%.
In the crystal oscillator, the oscillation time is between several ms and tens of ms. In ceramic oscillators,
the oscillation time is between hundreds of μs and several ms. With an external clock, the oscillation time is 0 ms.
• Under normal operation :
tRSTL
RST
0.2 VCC
0.2 VCC
• In stop mode :
tRSTL
RST
0.2 VCC
X0
0.2 VCC
90% of
amplitude
Internal operation
clock
100 µs
Oscillation time
of oscillator
Oscillation stabilization
waiting time
Instruction execution
Internal reset
DS07-13749-3E
35
MB90960 Series
(3) Power-on Reset
(TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Parameter
Symbol
Pin
Power on rise time
tR
VCC
tOFF
VCC
Power off time
Condition
⎯
Value
Unit
Min
Max
0.05
30
ms
1
⎯
ms
Remarks
Due to repetitive operation
*: There is limited reliability if the product is used exceeding TA = +105°C. Contact the sales or support
representative for this case.
tR
VCC
2.7 V
0.2 V
0.2 V
0.2 V
tOFF
Note : If you change the power supply voltage too rapidly, a power-on reset may occur. We recommend that you
start up smoothly by restraining voltages when changing the power supply voltage during operation, as
shown in the figure below. Perform while not using the PLL clock. However, if voltage drops are within
1 V/s, you can operate while using the PLL clock.
VCC
We recommend a rise of
50 mV/ms maximum.
3V
VSS
36
Holds RAM data
DS07-13749-3E
MB90960 Series
(4) LIN-UART0/1
• Bit setting: ESCR:SCES = 0, ECCR:SCDE = 0
(TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
5 tCP
⎯
ns
−50
+50
ns
tCP + 80
⎯
ns
SCK0, SCK1,
SIN0, SIN1
0
⎯
ns
tSHSL
SCK0, SCK1
3 tCP - tR
⎯
ns
Serial clock “H” pulse width
tSLSH
SCK0, SCK1
tCP + 10
⎯
ns
SCK ↓ → SOT delay time
tSLOVE
SCK0, SCK1,
SOT0, SOT1
⎯
2 tCP + 60
ns
Valid SIN → SCK ↑
tIVSHE
SCK0, SCK1,
SIN0, SIN1
30
⎯
ns
SCK ↑ → Valid SIN hold time
tSHIXE
SCK0, SCK1,
SIN0, SIN1
tCP + 30
⎯
ns
SCK fall time
tF
SCK0, SCK1
⎯
10
ns
SCK rise time
tR
SCK0, SCK1
⎯
10
ns
Serial clock cycle time
tSCYC
SCK0, SCK1
SCK ↓ → SOT delay time
tSLOVI
SCK0, SCK1,
SOT0, SOT1
Valid SIN → SCK ↑
tIVSHI
SCK0, SCK1,
SIN0, SIN1
SCK ↑ → Valid SIN hold time
tSHIXI
Serial clock “L” pulse width
Internal shift clock
mode output pins are
CL = 80 pF + 1 TTL.
External shift clock
mode output pins are
CL = 80 pF + 1 TTL.
*: There is limited reliability if the product is used exceeding TA = +105°C. Contact the sales or support
representative for this case.
Notes : • AC characteristic in CLK synchronized mode.
• CL is load capacity value of pins when testing.
• tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock Timing”.
• Internal Shift Clock Mode
tSCYC
SCK0, SCK1
2.4 V
0.8 V
0.8 V
tSLOVI
SOT0, SOT1
2.4 V
0.8 V
tIVSHI
SIN0, SIN1
DS07-13749-3E
tSHIXI
VIH
VIH
VIL
VIL
37
MB90960 Series
• External Shift Clock Mode
tSLSH
tSHSL
VIH
VIH
SCK0, SCK1
VIL
VIL
tSLOVE
tF
tR
2.4 V
SOT0, SOT1
0.8 V
tIVSHE
SIN0, SIN1
tSHIXE
VIH
VIH
VIL
VIL
• Bit setting: ESCR:SCES = 1, ECCR:SCDE = 0
(TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
5 tCP
⎯
ns
−50
+50
ns
tCP + 80
⎯
ns
SCK0, SCK1,
SIN0, SIN1
0
⎯
ns
tSHSL
SCK0, SCK1
3 tCP - tR
⎯
ns
Serial clock “L” pulse width
tSLSH
SCK0, SCK1
tCP + 10
⎯
ns
SCK ↑ → SOT delay time
tSHOVE
SCK0, SCK1,
SOT0, SOT1
⎯
2 tCP + 60
ns
Valid SIN → SCK ↓
tIVSLE
SCK0, SCK1,
SIN0, SIN1
30
⎯
ns
SCK ↓ → Valid SIN hold time
tSLIXE
SCK0, SCK1,
SIN0, SIN1
tCP + 30
⎯
ns
SCK fall time
tF
SCK0, SCK1
⎯
10
ns
SCK rise time
tR
SCK0, SCK1
⎯
10
ns
Serial clock cycle time
tSCYC
SCK0, SCK1
SCK ↑ → SOT delay time
tSHOVI
SCK0, SCK1,
SOT0, SOT1
Valid SIN → SCK ↓
tIVSLI
SCK0, SCK1,
SIN0, SIN1
SCK ↓ → Valid SIN hold time
tSLIXI
Serial clock “H” pulse width
Internal shift clock
mode output pins are
CL = 80 pF + 1 TTL.
External shift clock
mode output pins are
CL = 80 pF + 1 TTL.
* : There is limited reliability if the product is used exceeding TA = +105°C. Contact the sales or support
representative for this case.
Notes : • CL is load capacity value of pins when testing.
• tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock Timing”.
38
DS07-13749-3E
MB90960 Series
• Internal Shift Clock Mode
tSCYC
SCK0, SCK1
2.4 V
0.8 V
tSHOVI
2.4 V
SOT0, SOT1
0.8 V
tIVSLI
SIN0, SIN1
tSLIXI
VIH
VIH
VIL
VIL
• External Shift Clock Mode
tSHSL
VIL
tR
SOT0, SOT1
VIH
VIH
SCK0, SCK1
tSLSH
tSHOVE
VIL
tF
2.4 V
0.8 V
tIVSLE
SIN0, SIN1
DS07-13749-3E
tSLIXE
VIH
VIH
VIL
VIL
39
MB90960 Series
• Bit setting: ESCR:SCES = 0, ECCR:SCDE = 1
(TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)
Parameter
Symbol
Pin
Serial clock cycle time
tSCYC
SCK ↑ → SOT delay time
tSHOVI
Valid SIN → SCK ↓
tIVSLI
SCK ↓ → Valid SIN hold time
tSLIXI
SOT → SCK ↓ delay time
tSOVLI
Condition
Value
Unit
Min
Max
SCK0,SCK1
5 tCP
⎯
ns
SCK0,SCK1
SOT0,SOT1
−50
+50
ns
tCP + 80
⎯
ns
0
⎯
ns
3 tCP − 70
⎯
ns
SCK0,SCK1 Internal clock operation
SIN0,SIN1 output pins are
SCK0,SCK1 CL = 80 pF + 1 TTL.
SIN0,SIN1
SCK0,SCK1
SOT0,SOT1
* : There is limited reliability if the product is used exceeding TA = +105°C. Contact the sales or support
representative for this case.
Notes : • CL is load capacity value of pins when testing.
• tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock Timing” rating for tCP.
tSCYC
2.4 V
SCK0, SCK1
0.8 V
0.8 V
tSHOVI
tSOVLI
SOT0, SOT1
2.4 V
2.4 V
0.8 V
0.8 V
tIVSLI
SIN0, SIN1
40
VIH
VIL
tSLIXI
VIH
VIL
DS07-13749-3E
MB90960 Series
• Bit setting: ESCR:SCES = 1, ECCR:SCDE = 1
(TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)
Parameter
Symbol
Pin
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOVI
Valid SIN → SCK ↑
tIVSHI
SCK ↑ → Valid SIN hold time
tSHIXI
SOT → SCK ↑ delay time
tSOVHI
Condition
Value
Unit
Min
Max
SCK0,SCK1
5 tCP
⎯
ns
SCK0,SCK1
SOT0,SOT1
−50
+50
ns
tCP + 80
⎯
ns
0
⎯
ns
3 tCP − 70
⎯
ns
SCK0,SCK1 Internal clock operation
SIN0,SIN1 output pins are
SCK0,SCK1 CL = 80 pF + 1 TTL.
SIN0,SIN1
SCK0,SCK1
SOT0,SOT1
* : There is limited reliability if the product is used exceeding TA = +105°C. Contact the sales or support
representative for this case.
Notes : • CL is load capacity value of pins when testing.
• tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock Timing” rating for tCP.
tSCYC
2.4 V
2.4 V
SCK0, SCK1
0.8 V
tSLOVI
tSOVHI
SOT0, SOT1
2.4 V
2.4 V
0.8 V
0.8 V
tIVSHI
SIN0, SIN1
DS07-13749-3E
tSHIXI
VIH
VIH
VIL
VIL
41
MB90960 Series
(5) Trigger Input Timing
Parameter
Input pulse width
(TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Pin
Condition
Unit
Min
Max
Symbol
tTRGH
tTRGL
INT8, INT9R
INT10, INT11
INT12R, INT13
INT14R, INT15R
⎯
200
⎯
ns
ADTG
⎯
tCP + 200
⎯
ns
* : IThere is limited reliability if the product is used exceeding TA = +105°C. Contact the sales or support
representative for this case.
Note : tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock Timing”.
INT8, INT9R
INT10, INT11
INT12R, INT13
INT14R, INT15R
ADTG
42
VIH
VIH
VIL
VIL
tTRGH
tTRGL
DS07-13749-3E
MB90960 Series
(6) Timer Related Resource Input Timing
(TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
tTIWH
Input pulse width
tTIWL
TIN2, TIN3
IN0 to IN3
⎯
⎯
4 tCP
ns
* : There is limited reliability if the product is used exceeding TA = +105°C. Contact the sales or support
representative for this case.
Note : tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock Timing”.
VIH
VIH
TIN2, TIN3
IN0 to IN3
VIL
VIL
tTIWH
tTIWL
(7) Timer Related Resource Output Timing
(TA = –40°C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
CLK ↑ → TOUT change time
TOT2, TOT3
PPGC to PPGF
tTO
⎯
30
⎯
ns
* : There is limited reliability if the product is used exceeding TA = +105°C. Contact the sales or support
representative for this case.
CLK
2.4 V
2.4 V
TOT2, TOT3
PPGC to PPGF
0.8 V
tTO
DS07-13749-3E
43
MB90960 Series
5. A/D Converter
(TA = −40 °C to +125 °C*1, 3.0 V ≤ AVR − AVSS, VCC = AVCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Parameter
Symbol
Pin
Resolution
⎯
Total error
Value
Unit
Min
Typ
Max
⎯
⎯
⎯
10
bit
⎯
⎯
⎯
⎯
±3.0
LSB
Nonlinearity error
⎯
⎯
⎯
⎯
±2.5
LSB
Differential
nonlinearity error
⎯
⎯
⎯
⎯
±1.9
LSB
Zero reading voltage
VOT
AN0 to AN15
AVSS − 1.5 AVSS + 0.5 AVSS + 2.5
× LSB
× LSB
× LSB
V
Full scale reading
voltage
VFST
AN0 to AN15
AVR − 3.5
× LSB
V
Compare time
⎯
⎯
Sampling time
⎯
⎯
Analog port input
current
IAIN
AN0 to AN15
Analog input
voltage
VAIN
Reference
voltage
Power supply current
1.0
AVR − 1.5 AVR + 0.5
× LSB
× LSB
⎯
16500
μs
⎯
∞
μs
−0.3
⎯
+0.3
μA
AN0 to AN15
AVSS
⎯
AVR
V
⎯
AVR
AVSS + 2.7
⎯
AVCC
V
IA
AVCC
⎯
3.5
7.5
mA
IAH
AVCC
⎯
⎯
5
μA
2.0
0.5
1.2
Reference
voltage supply current
IR
AVR
⎯
600
900
μA
IRH
AVR
⎯
⎯
5
μA
Offset between
input channels
⎯
AN0 to AN15
⎯
⎯
4
LSB
Remarks
4.5 V ≤ AVCC ≤ 5.5 V
4.0 V ≤ AVCC < 4.5 V
4.5 V ≤ AVCC ≤ 5.5 V
4.0 V ≤ AVCC < 4.5 V
*2
*2
*1 : There is limited reliability if the product is used exceeding TA = +105°C. Contact the sales or support
representative for this case.
*2 : If A/D converter is not operating, a current when CPU is stopped is applicable (VCC = AVCC = AVR = 5.0 V) .
(Continued)
44
DS07-13749-3E
MB90960 Series
• About the external impedance of analog input and its sampling time
• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage changed to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision.
• Analog input circuit model
R
Comparator
Analog input
C
During sampling : ON
Part number
MB90F962(S)
MB90V340E-101/102
Analog input
R
C
4.5 V ≤ AVCC ≤ 5.5 V
2.0 kΩ (Max)
16.0 pF (Max)
4.0 V ≤ AVCC < 4.5 V
8.2 kΩ (Max)
16.0 pF (Max)
4.5 V ≤ AVCC ≤ 5.5 V
2.0 kΩ (Max)
14.4 pF (Max)
4.0 V ≤ AVCC < 4.5 V
8.2 kΩ (Max)
14.4 pF (Max)
Note : The values are reference values.
Use the device with external circuits of the following output impedance for analog inputs:
• Recommended output impedance of external circuits are : Approx. 1.5 kΩ or lower (4.0 V ≤ AVCC ≤ 5.5 V,
sampling period = 0.5 μs)
• If an external capacitor is used, in consideration of the effect by tap capacitance caused by external capacitors
an on-chip capacitors, capacitance of the external one is recommended to be several thousand times as high
as internal capacitor.
• If the output impedance of an external circuit is too high, the sampling period for the analog voltage may be
insufficient.
• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 μF to the analog input pin.
• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance
and minimum sampling time and either adjust the resistor value and operating frequency or decrease the
external impedance so that the sampling time is longer than the minimum value.
(Continued)
DS07-13749-3E
45
MB90960 Series
(Continued)
• The relationship between external impedance and minimum sampling time
• At 4.5 V ≤ AVCC ≤ 5.5 V
(External impedance = 0 kΩ to 20 kΩ)
(External impedance = 0 kΩ to 100 kΩ)
MB90F340E-101/102
80
70
60
50
40
30
20
External impedance [kΩ]
External impedance [kΩ]
MB90F340E-101/102
100
90
MB90F962(S)
10
0
0
5
10
15
20
25
30
20
18
16
14
12
10
MB90F962(S)
8
6
4
2
0
0
35
Minimum sampling time [μs]
1
2
3
4
5
6
7
8
Minimum sampling time [μs]
• At 4.0 V ≤ AVCC < 4.5 V
(External impedance = 0 kΩ to 20 kΩ)
100
90
80
70
60
50
40
30
20
MB90F340E-101/102
External impedance [kΩ]
External impedance [kΩ]
(External impedance = 0 kΩ to 100 kΩ)
MB90F962(S)
10
0
0
5
10
15
20
25
30
Minimum sampling time [μs]
35
MB90F340E-101/102
20
18
16
14
12
10
8
6
4
MB90F962(S)
2
0
0
1
2
3
4
5
6
7
8
Minimum sampling time [μs]
• About errors
As | AVR − AVSS | becomes smaller, values of relative errors grow larger.
46
DS07-13749-3E
MB90960 Series
6. Definition of A/D Converter Terms
Resolution
Non linearity
error
Differential
linearity error
Total error
: Analog variation that is recognized by an A/D converter.
: Deviation between a line across zero-transition line ( “00 0000 0000B” ← → “00 0000 0001B” )
and full-scale transition line ( “11 1111 1110B” ← → “11 1111 1111B” ) and actual conversion
characteristics.
: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal
value.
: Difference between an actual value and an theoretical value. A total error includes zero
transition error, full-scale transition error, and linear error.
Total error
3FFH
3FEH
1.5 LSB
Actual conversion
characteristics
Digital output
3FDH
{1 LSB × (N − 1) + 0.5 LSB}
004H
VNT
(Actually-measured value)
003H
Actual conversion
characteristics
Ideal characteristics
002H
001H
0.5 LSB
AVSS
AVR
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}
1 LSB
AVR − AVSS
1 LSB (Ideal value) =
[V]
1024
VOT (Ideal value) = AVSS + 0.5 LSB [V]
Total error of digital output “N” =
[LSB]
VFST (Ideal value) = AVR − 1.5 LSB [V]
VNT : A voltage at which digital output transits from (N − 1) to N.
(Continued)
DS07-13749-3E
47
MB90960 Series
(Continued)
Non linearity error
Differential linearity error
Ideal
characteristics
3FFH
Digital output
3FDH
Actual conversion
characteristics
{1 LSB × (N − 1)
+ VOT }
N+1
VFST (actual
measurement
value)
VNT (actual
measurement value)
004H
003H
Actual conversion
characteristics
Digital output
3FEH
Actual conversion
characteristics
N
V (N + 1) T
(actual measurement
value)
VNT
(actual measurement value)
N−1
002H
Ideal characteristics
Actual conversion
characteristics
N−2
001H
VOT (actual measurement value)
AVSS
AVR
AVSS
AVR
Analog input
Analog input
Non linearity error of digital output N =
Differential linearity error of digital output N =
1 LSB =
VNT − {1 LSB × (N − 1) + VOT}
1 LSB
V (N+1) T − VNT
1 LSB
VFST − VOT
1022
[LSB]
−1 LSB [LSB]
[V]
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
48
DS07-13749-3E
MB90960 Series
7. Flash Memory Program/Erase Characteristics
Parameter
Conditions
Program/Erase cycle
Flash memory data
retention time
Remarks
Typ
Max
⎯
1
15
s
Excludes programming
prior to erasure
⎯
0.2
0.5
s
Excludes programming
prior to erasure
⎯
21
6100
μs
Except for the overhead
time of the system level
VCC = 5.0 V
⎯
⎯
24
MHz
⎯
10000
⎯
⎯
cycle
Average
TA = +85 °C
20
⎯
⎯
Year
TA = +25 °C
VCC = 5.0 V
Byte programming time
Machine clock frequency fCP at
Flash programming/erasing
Unit
Min
Sector erase time (60 Kbytes)
Sector erase time (4 Kbytes)
Value
*
* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at +85 °C) .
DS07-13749-3E
49
MB90960 Series
■ ORDERING INFORMATION
Part number
MB90F962PMT
MB90F962SPMT
MB90V340E-101CR
MB90V340E-102CR
50
Package
Remarks
48-pin plastic LQFP
FPT-48P-M26
7 mm ❑, 0.50 mm pitch
Flash Memory Product
(64Kbytes)
299-pin ceramic PGA
PGA-299C-A01
Evaluation product
DS07-13749-3E
MB90960 Series
■ PACKAGE DIMENSION
48-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
7 × 7 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.17 g
Code
(Reference)
P-LFQFP48-7×7-0.50
(FPT-48P-M26)
48-pin plastic LQFP
(FPT-48P-M26)
Note 1) * : These dimensions include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
9.00±0.20(.354±.008)SQ
+0.40
+.016
* 7.00 –0.10 .276 –.004 SQ
36
0.145±0.055
(.006±.002)
25
37
24
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
48
13
"A"
0˚~8˚
LEAD No.
0.50(.020)
1
(Mounting height)
.059 –.004
INDEX
0.10±0.10
(.004±.004)
(Stand off)
12
0.20±0.05
(.008±.002)
0.08(.003)
0.25(.010)
M
0.60±0.15
(.024±.006)
©2003-2008
FUJITSU
LIMITED F48040S-c-2-3
C
2003 FUJITSU
LIMITEDMICROELECTRONICS
F48040S-c-2-2
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
DS07-13749-3E
51
MB90960 Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
Change Results
⎯
⎯
Deleted the following part numbers.
MB90F967, MB90F967S, MB90V340E-103/104
⎯
⎯
Deleted the description of Clock supervisor.
1
■ FEATURES
Corrected minimum instruction execution time.
42 ns → 41.7 ns
4
■ PRODUCT LINEUP
Corrected minimum instruction execution time for system clock.
42 ns → 41.7 ns
The vertical lines marked in the left side of the page show the changes.
52
DS07-13749-3E
MB90960 Series
MEMO
DS07-13749-3E
53
MB90960 Series
MEMO
54
DS07-13749-3E
MB90960 Series
MEMO
DS07-13749-3E
55
MB90960 Series
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