To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Renesas Technology Home Page: http://www.renesas.com Renesas Technology Corp. Customer Support Dept. April 1, 2003 Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. 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Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein. HM62V16512I Series Wide Temperature Range Version 8 M SRAM (512-kword × 16-bit) ADE-203-1279A (Z) Rev. 1.0 Mar. 12, 2002 Description The Hitachi HM62V16512I Series is 8-Mbit static RAM organized 524,288-word × 16-bit. HM62V16512I Series has realized higher density, higher performance and low power consumption by employing Hi-CMOS process technology. It offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It is packaged in 48 bumps chip size package with 0.75 mm bump pitch for high density surface mounting. Features • • • • • • • • Single 3.0 V supply: 2.7 V to 3.6 V Fast access time: 55 ns (Max) Power dissipation: Active: 6.0 mW/MHz (Typ) Standby: 1.5 µW (Typ) Completely static memory. No clock or timing strobe required Equal access and cycle times Common data input and output. Three state output Battery backup operation. 2 chip selection for battery backup Temperature range: –40 to +85°C HM62V16512I Series Ordering Information Type No. Access time HM62V16512LBPI-5 55 ns HM62V16512LBPI-5SL 55 ns 2 Package 48-bumps CSP with 0.75 mm bump pitch (TBP-48A) HM62V16512I Series Pin Arrangement 48-bumps CSP 1 2 3 4 5 6 A LB OE A0 A1 A2 CS2 B I/O8 UB A3 A4 CS1 I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D VSS I/O11 A17 A7 I/O3 VCC E VCC I/O12 VSS A16 I/O4 VSS F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H A18 A8 A9 A10 A11 NC (Top view) Pin Description Pin name Function A0 to A18 Address input I/O0 to I/O15 Data input/output CS1 Chip select 1 CS2 Chip select 2 WE Write enable OE Output enable LB Lower byte select UB Upper byte select VCC Power supply VSS Ground NC No connection 3 HM62V16512I Series Block Diagram LSB A6 A15 A11 A16 A7 A13 A10 A2 A4 A1 MSB A3 V CC V SS • • • • • Row decoder I/O0 Memory matrix 2,048 x 4,096 Column I/O • • Input data control Column decoder I/O15 LSBA12A9A18 A8A14A17A5 A0 MSB • • CS2 CS1 LB UB WE OE 4 Control logic • • HM62V16512I Series Operation Table CS1 CS2 WE OE UB LB I/O0 to I/O7 I/O8 to I/O15 Operation H × × × × × High-Z High-Z Standby × L × × × × High-Z High-Z Standby × × × × H H High-Z High-Z Standby L H H L L L Dout Dout Read L H H L H L Dout High-Z Lower byte read L H H L L H High-Z Dout Upper byte read L H L × L L Din Din Write L H L × H L Din High-Z Lower byte write L H L × L H High-Z Din Upper byte write L H H H × × High-Z High-Z Output disable Note: H: V IH, L: VIL, ×: VIH or VIL Absolute Maximum Ratings Parameter Symbol Value Unit Power supply voltage relative to V SS VCC –0.5 to + 4.6 1 V 2 Terminal voltage on any pin relative to V SS VT –0.5* to V CC + 0.3* V Power dissipation PT 1.0 W Storage temperature range Tstg –55 to +125 °C Storage temperature range under bias Tbias –40 to +85 °C Notes: 1. VT min: –3.0 V for pulse half-width ≤ 30 ns. 2. Maximum voltage is +4.0 V. DC Operating Conditions Parameter Symbol Min Typ Max Unit Supply voltage VCC 2.7 3.0 3.6 V VSS 0 0 0 V Input high voltage VIH 2.2 — VCC + 0.3 V Input low voltage VIL –0.3 — 0.6 V Ambient temperature range Ta –40 — 85 °C Note: Note 1 1. VIL min: –3.0 V for pulse half-width ≤ 30 ns. 5 HM62V16512I Series DC Characteristics Parameter Symbol Min Typ* 1 Max Unit Test conditions Input leakage current |ILI| — — 1 µA Vin = VSS to V CC Output leakage current |ILO | — — 1 µA CS1 = VIH or CS2 = VIL or OE = VIH or WE = VIL, or LB = UB =VIH VI/O = VSS to V CC Operating current I CC — 10 20 mA CS1 = VIL, CS2 = VIH, Others = VIH/VIL, I I/O = 0 mA Average operating current I CC1 — 16 30 mA Min. cycle, duty = 100%, I I/O = 0 mA, CS1 = VIL, CS2 = VIH, Others = VIH/VIL I CC2 — 2 5 mA Cycle time = 1 µs, duty = 100%, I I/O = 0 mA, CS1 ≤ 0.2 V, CS2 ≥ V CC – 0.2 V VIH ≥ V CC – 0.2 V, VIL ≤ 0.2 V Standby current I SB — 0.1 0.3 mA CS2 = VIL 2 — 0.5 25 µA 0 V ≤ Vin (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS1 ≥ V CC – 0.2 V, CS2 ≥ V CC – 0.2 V I SB1*3 — 0.5 10 µA Output high voltage VOH 2.2 — — V I OH = –1 mA Output low voltage VOL — — 0.4 V I OL = 2 mA Standby current Note: I SB1* 1. Typical values are at VCC = 2.5 V/3.0 V, Ta = +25°C and not guaranteed. 2. This characteristic is guaranteed only for L version. 3. This characteristic is guaranteed only for L-SL version. Capacitance (Ta = +25°C, f = 1.0 MHz) Parameter Symbol Min Typ Max Unit Test conditions Note Input capacitance Cin — — 8 pF Vin = 0 V 1 Input/output capacitance CI/O — — 10 pF VI/O = 0 V 1 Note: 6 1. This parameter is sampled and not 100% tested. HM62V16512I Series AC Characteristics (Ta = –40 to +85°C, VCC = 2.7 V to 3.6 V, unless otherwise noted.) Test Conditions • • • • Input pulse levels: VIL = 0.4 V, VIH = 2.2 V Input rise and fall time: 5 ns Input and output timing reference levels: 1.5 V Output load: See figures (Including scope and jig) VTM R1 Dout R1 = 3070 Ω 30pF R2 R2 = 3150 Ω VTM = 2.8 V 7 HM62V16512I Series Read Cycle HM62V16512I -5 Parameter Symbol Min Max Unit Read cycle time t RC 55 — ns Address access time t AA — 55 ns Chip select access time t ACS1 — 55 ns t ACS2 — 55 ns Output enable to output valid t OE — 35 ns Output hold from address change t OH 10 — ns LB, UB access time t BA — 55 ns Chip select to output in low-Z t CLZ1 10 — ns 2, 3 t CLZ2 10 — ns 2, 3 LB, UB enable to low-z t BLZ 5 — ns 2, 3 Output enable to output in low-Z t OLZ 5 — ns 2, 3 Chip deselect to output in high-Z t CHZ1 0 20 ns 1, 2, 3 t CHZ2 0 20 ns 1, 2, 3 LB, UB disable to high-Z t BHZ 0 20 ns 1, 2, 3 Output disable to output in high-Z t OHZ 0 20 ns 1, 2, 3 8 Notes HM62V16512I Series Write Cycle HM62V16512I -5 Parameter Symbol Min Max Unit Notes Write cycle time t WC 55 — ns Address valid to end of write t AW 50 — ns Chip selection to end of write t CW 50 — ns 5 Write pulse width t WP 40 — ns 4 LB, UB valid to end of write t BW 50 — ns Address setup time t AS 0 — ns 6 Write recovery time t WR 0 — ns 7 Data to write time overlap t DW 25 — ns Data hold from write time t DH 0 — ns Output active from end of write t OW 5 — ns 2 Output disable to output in High-Z t OHZ 0 20 ns 1, 2 Write to output in high-Z t WHZ 0 20 ns 1, 2 Notes: 1. t CHZ, tOHZ , t WHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, t HZ max is less than tLZ min both for a given device and from device to device. 4. A write occures during the overlap of a low CS1, a high CS2, a low WE and a low LB or a low UB. A write begins at the latest transition among CS1 going low, CS2 going high, WE going low and LB going low or UB going low. A write ends at the earliest transition among CS1 going high, CS2 going low, WE going high and LB going high or UB going high. tWP is measured from the beginning of write to the end of write. 5. t CW is measured from the later of CS1 going low or CS2 going high to the end of write. 6. t AS is measured from the address valid to the beginning of write. 7. t WR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write cycle. 9 HM62V16512I Series Timing Waveform Read Cycle t RC Address Valid address tAA tACS1 CS1 tCLZ1*2, 3 CS2 tCHZ1*1, 2, 3 tACS2 tCLZ2*2, 3 tCHZ2*1, 2, 3 tBHZ*1, 2, 3 tBA LB, UB tBLZ*2, 3 tOHZ*1, 2, 3 tOE OE tOLZ*2, 3 Dout 10 High impedance tOH Valid data HM62V16512I Series Write Cycle (1) (WE Clock) tWC Valid address Address tWR*7 tCW*5 CS1 tCW*5 CS2 tBW LB, UB tAW tWP*4 WE tAS*6 tDW tDH Valid data Din tWHZ*1, 2 tOW*2 High impedance Dout 11 HM62V16512I Series Write Cycle (2) (CS Clock, OE = VIH) tWC Valid address Address tAW tAS*6 tWR*7 tCW*5 CS1 tCW*5 CS2 tBW LB, UB tWP*4 WE tDW Valid data Din High impedance Dout 12 tDH HM62V16512I Series Write Cycle (3) (LB, UB Clock, OE = VIH) tWC Valid address Address tAW tCW*5 tWR*7 CS1 tCW*5 CS2 tAS*6 tBW LB, UB tWP*4 WE tDW tDH Valid data Din High impedance Dout 13 HM62V16512I Series Low VCC Data Retention Characteristics (Ta = –40 to +85°C) Parameter Symbol Min Typ* 4 Max Unit Test conditions*3 VCC for data retention VDR 2 — 3.6 V Vin ≥ 0V (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS2 ≥ V CC – 0.2 V CS1 ≥ V CC – 0.2 V or (3) LB = UB ≥ V CC – 0.2 V CS2 ≥ V CC – 0.2 V CS1 ≤ 0.2 V Data retention current I CCDR*1 — 0.5 25 µA VCC = 3.0 V, Vin ≥ 0V (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS2 ≥ V CC – 0.2 V, CS1 ≥ V CC – 0.2 V or (3) LB = UB ≥ V CC – 0.2 V CS2 ≥ V CC – 0.2 V CS1 ≤ 0.2 V I CCDR*2 — 0.5 10 µA — — ns — — ns Chip deselect to data retention time t CDR Operation recovery time tR 0 t RC* 5 See retention waveform Notes: 1. This characteristic is guaranteed only for L version. 2. This characteristic is guaranteed only for L-SL version. 3. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer, LB, UB buffer and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE, OE, CS1, LB, UB, I/O) can be in the high impedance state. If CS1 controls data retention mode, CS2 must be CS2 ≥ V CC – 0.2 V or 0 V ≤ CS2 ≤ 0.2 V. The other input levels (address, WE, OE, LB, UB, I/O) can be in the high impedance state. 4. Typical values are at VCC = 3.0 V, Ta = +25˚C and not guaranteed. 5. t RC = read cycle time. 14 HM62V16512I Series Low V CC Data Retention Timing Waveform (1) (CS1 Controlled) t CDR Data retention mode tR VCC 2.7 V 2.2 V VDR CS1 0V CS1 ≥ VCC – 0.2 V Low V CC Data Retention Timing Waveform (2) (CS2 Controlled) t CDR Data retention mode tR VCC 2.7 V CS2 VDR 0.6 V 0 V < CS2 < 0.2 V 0V Low V CC Data Retention Timing Waveform (3) (LB, UB Controlled) t CDR Data retention mode tR VCC 2.7 V 2.2 V VDR LB, UB 0V LB, UB ≥ VCC – 0.2 V 15 HM62V16512I Series Package Dimensions HM62V16512LBPI Series (TBP-48A) 1.375 0.75 2.275 6.50 0.20 C A 0.20 C B Unit: mm A Index mark Pin 1 Index B 0.75 9.80 A B C D E F G H 4× A 0.15 0.2 C 6 5 4 3 2 1 48 × φ0.35 ± 0.05 φ0.08 M C A B 1.2 Max 0.10 C 0.25 ± 0.05 C Details of the part A Hitachi Code JEDEC EIAJ Mass (reference value) 16 TBP-48A — — 0.13 g HM62V16512I Series Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: (03) 3270-2111 Fax: (03) 3270-5109 URL http://www.hitachisemiconductor.com/ For further information write to: Hitachi Semiconductor (America) Inc. 179 East Tasman Drive San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe Ltd. Electronic Components Group Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 585200 Hitachi Europe GmbH Electronic Components Group Dornacher Straße 3 D-85622 Feldkirchen Postfach 201,D-85619 Feldkirchen Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Asia Ltd. Hitachi Tower 16 Collyer Quay #20-00 Singapore 049318 Tel : <65>-538-6533/538-8577 Fax : <65>-538-6933/538-3877 URL : http://semiconductor.hitachi.com.sg Hitachi Asia Ltd. (Taipei Branch Office) 4/F, No. 167, Tun Hwa North Road Hung-Kuo Building Taipei (105), Taiwan Tel : <886>-(2)-2718-3666 Fax : <886>-(2)-2718-8180 Telex : 23222 HAS-TP URL : http://www.hitachi.com.tw Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel : <852>-(2)-735-9218 Fax : <852>-(2)-730-0281 URL : http://semiconductor.hitachi.com.hk Copyright © Hitachi, Ltd., 2001. All rights reserved. Printed in Japan. Colophon 5.0 17