D SILICON MMIC UPCONVERTER UPC8104GR AND QUADRATURE MODULATOR FUNCTIONAL BLOCK DIAGRAM FEATURES • WIDE SUPPLY VOLTAGE RANGE: 2.7 ~ 5.5 V LO1 LO2 UE • BROADBAND OPERATION: RFOUT = 0.8 - 2.4 GHz MODOUT = 100 - 400 MHz, I/Q = DC to 10 MHz • INTERNAL 90° PHASE SHIFTER I I 0˚ φ RF • PORTS FOR EXTERNAL IF FILTER 90˚ • LOW POWER CONSUMPTION: 28 mA AT 3 VOLT TYPICAL Q Q Filter • SMALL SSOP 20 PACKAGE IN • TAPE AND REEL PACKAGING AVAILABLE DESCRIPTION as 900 MHz Digital Cordless Phones, WLAN and PCN/PCS Handset Transmitters. NEC's stringent quality assurance and test procedures ensure the highest reliability and performance. NT The UPC8104GR Silicon MMIC Frequency Upconverter with I/Q Modulator is manufactured using the NESAT III MMIC process. The NESAT III process produces transistors with fT approaching 20 GHz. The device was designed for use in 800 MHz to 2.4 GHz Digital Mobile Communications circuits such ELECTRICAL CHARACTERISTICS (TA = 25°C, VCC = 3.0 V, VPS ≥1.8 V) PART NUMBER PACKAGE OUTLINE SYMBOLS PARAMETERS AND CONDITIONS Total Circuit Current (no signal) VPS ≥ 1.8 V VPS ≤ 1.0 V SC O Up Converter Total ICC Total Output Power1,2 Upconverter LO Carrier Leakage1 Image Rejection1 (Side Band Leakage) Circuit Current - Upconverter (no signal) PRF LOL ImR ICC CG VPS ≥ 1.8 V VPS ≤ 1.0 V Conversion Gain1 fRF = 900 MHz, fIF = 240 MHz, fLO = 1140 MHz fRF = 1900 MHz, fIF = 240 MHz, fLO = 1660 MHz fRF = 2450 MHz, fIF = 240 MHz, fLO = 2210 MHz Maximum Output Power - Upconverter fRF = 900 MHz, fIF = 240 MHz fRF = 1900 MHz, fIF = 240 MHz Output 3rd Order Intercept Point fRFOUT = 1.9 GHz fIF = 240.0 MHz/240.2 MHz Circuit Current - Modulator (no signal) VPS ≥ 1.8 V VPS ≤ 1.0 V Output Power - Modulator2 Local Oscillator Leakage2 Image Rejection2 PRF (SAT) OIP3 ICC Modulator DI PMOD LOLEAK ImR IM3 I/Q RLIN ZI/Q II/Q TPS(RISE) TPS (FALL) I/Q 3rd Order Intermodulation Distortion2 I/Q LO Input Return Loss Input Impedance I and Q Ports2 I/Q Bias Current Power Save Rise Time VPS ≤ 1.0 V to VPS ≥ 1.8V Power Save Fall Time VPS ≥1.8 V to VPS ≤1.0 V Notes: 1. PIFIN = -20 dBm 2. VI/Q = 1.5 V (DC) +0.5 Vp-p (AC) UPC8104GR S20 (SSOP 20) UNITS MIN TYP MAX mA µA dBm dBc dBc mA µA dB dB dB dBm dBm 18 28 0.1 -13.5 -40 -40 12 37 10 -8.5 -30 -30 dBm mA µA dBm dBc dBc dBc dB kΩ µA µS µS -18.5 5 10 4.5 4 -2 -6 10 0 16 21 5 -17.5 -40 -40 -30 -30 -50 20 20 5 2.0 2.0 5.0 5.0 California Eastern Laboratories UPC8104GR SYMBOLS UNITS RATINGS VCC Supply Voltage PARAMETERS V 6.0 VPS Enable Voltage for Power Save V 6.0 PD Power Dissipation2 mW 530 TOP Operating Temperature °C -40 to +85 TSTG Storage Temperature °C -65 to +150 RECOMMENDED OPERATING CONDITIONS SYMBOLS UNITS MIN TYP MAX VCC Supply Voltage V 2.7 3.0 TOP Operating Temperature °C -40 +25 +85 fRF Up Converter RF Frequency GHz 0.9 2.4 fIF IF fLO2 Notes: 1. Operation in excess of any one of these parameters may result in permanent damage. 2. Mounted on a 50x50x1.6 mm epoxy glass PWB (TA = 85°C). PARAMETERS fI/Q Frequency1 MHz 100 400 Up Converter LO Frequency GHz 0.9 2.2 DC 10 I/Q Input Frequency2 MHz UE Notes: 1. IF frequency range includes Up-Converter IF input, Modulator IF Output and Modulator LO Input Frequency (LO1). 2. VI/QIN = 600 mVp-p maximum. TYPICAL PERFORMANCE CURVES (TA = 25°C, VCC = VPS = 3 V, I/Q DC Offset = I/Q DC Offset = 1.5 V, I/Q Input Signal = 500 mVp-p (Single Ended), PLO1IN = -10 dBm, PLO2IN = -10 dBm unless otherwise specified) UPCONVERTER CONVERSION GAIN vs. VOLTAGE CURRENT vs. VOLTAGE 10 IN 35 Conversion Gain, CG (dB) 25 20 15 10 RF = 1.9 GHz LO2 = 1.66 GHz, -20 dBm IF = 240 MHz, -20 dBm VPS = VCC = 3 V 5 NT Circuit Current, ICC (mA) 30 VCC = VPS = 3 V RF None ICC Total ICC Modulator ICC Upconverter 5 0 -5 0 1 2 3 0 6 5 4 1 2 6 5 UPCONVERTER INPUT POWER vs. OUTPUT POWER UPCONVERTER INPUT POWER vs. OUTPUT POWER +10 OIP3 = +7 dBm OIP3 = +0.2 dBm 0 -10 -10 -20 PRF OUT -30 IM3 -40 -50 -60 -70 -30 -20 fRF OUT = 900 MHz fLO2 IN = 1140 MHz PLO2 IN = -10 dBm fIF IN1 = 240.0 MHz fIF IN2 = 240.2 MHz VCC = VPS = 3 V -10 Input Power , PIN (dBm) 0 +10 Output Power, IM3 (dBm) 0 DI Output Power, IM3 (dBm) 4 Supply Voltage, VCC (V) +10 -80 -40 3 Supply Voltage, VCC (V) SC O 0 5.5 D ABSOLUTE MAXIMUM RATINGS1 (TA = 25°C) -20 -30 PRF OUT -40 IM3 -50 fRF OUT = 1.9 GHz fLO2 IN = 1.66 GHz PLO2 IN = -10 dBm fIF IN1 = 240.0 MHz fIF IN2 = 240.2 MHz VCC = VPS = 3 V -60 -70 -80 -40 -30 -20 -10 Input Power , PIN (dBm) 0 +10 UPC8104GR TYPICAL PERFORMANCE CURVES (TA = 25°C) UPCONVERTER CONVERSION GAIN vs. LO POWER UPCONVERTER CONVERSION GAIN vs. LO POWER 5 fRF OUT = 900 MHz fLO2 IN = 1140MHz fIF IN = 240 MHz PIF IN = -20 dBm VCC = VPS = 3 V 0 fRF OUT = 1.9 GHz fLO2 IN = 1.66 GHz fIF IN = 240 MHz PIF IN = -20 dBm VCC = VPS = 3 V 5 -40 -30 -20 0 -10 -40 +10 LO2 Input Power, PLO2IN (dBm) -20 IN -10 POUT NT 5 SC O RF = 900 MHz LO2 IN = 1140MHz, -20 dBm IF = 240 MHz, -20 dBm PIF IN = -20 dBm VPS = VCC 1 2 4 3 5 6 -20 -40 ∆M 5 ∆A 3 ∆φ IM3 I/O 7 5 I/Q Input Signal, PI/QIN (mVp-p) 1500 ∆M 3 1 1000 -50 +10 0 VCC = 3 V LO1 = -15 dBm I/Q DC 1500 mV AC 430 mVp-p 10 1 500 -10 -20 VECTOR ERROR, MAGNITUDE ERROR, PHASE ERROR vs. LO1 INPUT FREQUENCY 2 0 -40 -60 2 0 IMR LO1 Input Power, PLO1IN (dBm) Phase Error, ∆φ (deg.) Magnitude Error, ∆A (%) Vector Error, ∆M (%) DI 7 -30 -50 VECTOR ERROR, MAGNITUDE ERROR, PHASE ERROR vs. I/Q INPUT SIGNAL 10 LOL -30 Supply Voltage, VCC (V) VCC = 3 V LO1: 240 MHz -10 dBm LO2: 1,660 MHz -8 dBm I/Q DC 1,500 mV -20 -10 -70 -30 0 0 +10 ∆A ∆φ 0 0 100 200 300 400 500 LO1 Input Frequency, fLO1 (MHz) Modulator Output Power, PMODOUT (dBm) 10 0 -10 MODULATOR OUTPUT POWER, LO LEAKAGE , IMAGE REJECTION AND I/Q 3rd ORDER INTERMODULATION DISTORTION vs. LO1 INPUT POWER 15 Phase Error, ∆φ (deg.) Magnitude Error, ∆A (%) Vector Error, ∆M (%) -30 LO2 Input Power, PLO2IN (dBm) UPCONVERTER CONVERSION GAIN vs. VOLTAGE Conversion Gain, CG (dB) 0 UE 10 D Conversion Gain, CG (dB) 5 LO Leakage, LOL ; Image Rejection, ImR; IM3 I/Q (dBc) Conversion Gain, CG (dB) 15 UPC8104GR TYPICAL PERFORMANCE CURVES (TA = 25°C) MODULATOR OUTPUT POWER, LO LEAKAGE, IMAGE REJECTION AND I/Q 3rd ORDER INTERMODULATION DISTORTION vs. LO1 INPUT FREQUENCY MODULATOR OUTPUT POWER, LO LEAKAGE , IMAGE REJECTION AND I/Q 3rd ORDER INTERMODULATION DISTORTION vs. I/Q INPUT SIGNAL -30 -30 LOL -40 IMR -40 -50 -60 IM3 I/Q -50 -70 0 -40 D -40 LOL -50 -50 IM3 I/O -60 -60 -70 100 500 200 IN MODULATOR TYPICAL SINE WAVE MODULATION OUTPUT SPECTRUM 0 Pout -20 -30 -40 Output Power, POUT (dBm) 384 kbps Data Rate LO1 -50 ImR -60 IM3 -70 IM3 -80 SC O -90 1.900 Frequency, f (GHz) DI -10 NT 0 Output Power, POUT (dBm) -30 LO1 Input Frequency, fLO1 (MHz) MODULATOR AND UPCONVERTER TYPICAL SINE WAVE MODULATION OUTPUT SPECTRUM 1.899 -30 50 I/Q Input Signal, P I/QIN (Vp-p) -10 -20 IMR -70 1 0.5 -20 UE -20 LO Leakage, LOL ; Image Rejection, ImR; IM3 I/Q (dBc) -20 -10 POUT 1.901 384 kbps Data Rate Pout -20 -30 -40 LO LEAK -50 ImR -60 -70 -80 IM3 -90 239.9 Modulator Output Power, PMODOUT (dBm) POUT -10 -10 Modulator Output Power, PMODOUT (dBm) LO Leakage, LOL; Image Rejection, ImR; IM3 I/Q (dBc) -10 240 Frequency, f (MHz) 240.1 UPC8104GR TYPICAL PERFORMANCE CURVES (TA = 25°C) LO2IN INPUT IMPEDANCE Impedance at Marker 2: 49.224 - j13.58 Ω D MODOUT OUTPUT IMPEDANCE Impedance at Marker 2: 20.184 - j113.66 Ω UE 2 3 1 2 LO2IN Marker 1. 900 MHz 2. 1.66 GHz 3. 1.8 GHz 1 MODOUT (IFOUT) Marker 1. 100 MHz 2. 240 MHz 3. 400 4Hz 3 800 MHz 1900 MHz Start Stop IN Start Stop Upconverter Input Impedance 50 MHz 500 MHz LOIN Input Impedance Impedance at Marker 2: 51.727 - j2 Ω NT Impedance at Marker 2: 262.19 - j394.97 Ω 2 2 3 1 1 3 SC O UPCONIN (IFIN) Marker 1. 100 MHz 2. 240 MHz 3. 400 MHz 50 MHz 500 MHz DI Start Stop LO1iN Marker 1. 100 MHz 2. 240 MHz 3. 400 MHz Start Stop 50 MHz 500 MHz UPC8104GR PIN FUNCTIONS Pin No. Symbol Supply Voltage Pin Voltage 1 LO1IN (Modulator) — 0 4 I Bypass of the LO1 input.This pin is grounded through an internal capacitor. For a single-ended design this pin should be left open. — VCC/2*2 VCC/2*2 6 Q VCC/2*2 7 Q VCC/2*2 — — Input for I signal. This input impedance is larger than 20 kΩ. The relationship between the amplitude and the DC bias of the input signal are as follows: *1 VCC/2 (V) Amp. (mVp-p) ≥1.35 400 ≥1.5 600 ≥1.75 1000 — — — 4 Input for Q signal. This input impedance is larger than 20 kΩ. VCC/2 biased DC signal should be input. Input for Q signal. This input impedance is larger than 20 kΩ. The relationship between the amplitude and the DC bias of the input signal are as follows: VCC/2 (V) ≥1.35 ≥1.5 ≥1.75 7 6 *1 Amp. (mVp-p) 400 600 1000 Output from the modulator. This is emitter follower output. Connect around 15 Ω in series to match to 50 Ω. 16 *1: In case I/Q input signals are single ended. I/Q signal inputs can be used either single-ended or differentially with proper terminations. *2: VCC/2 DC bias must be supplied to I, I, Q, Q. DI 5 Input for I signal. This input impedance is larger than 20 kΩ. VCC/2 biased DC signal should be input. SC O I MODOUT 2 Connect to ground with minimum inductance. Track length should be kept as short as possible. 5 16 50 Ω D GND (Modulator) 1 UE 3 Equivalent Circuit IN LO1IN (Bypass) NT 2 Description LO1 input for the phase shifter. This input impedance is internally matched to 50 Ω. UPC8104GR PIN FUNCTIONS Pin Voltage 8 10 GND (Upconverter)) 0 - LO2IN (Bypass) — 2.0 12 LO2IN (Upconverter) -— 0 13 VCC (Upconverter) 2.7~5.5 — 9 RFOUT VCC — 14 Upconverter in — 2.0 15 Upconverter in (Bypass) — 2.0 17 GND 0 Connect to ground with minimum inductance. Track length should be kept as short as possible. Bypass of the LO2 input. Requires grounding through an external capacitor. LO2 input for the Upconverter. This pin is a high impedance input. — 19 VCC (Modulator) VPS 2.7~5.5 DI 20 VPS (Power Save) — — 12 11 Supply voltage pin for the Upconverter. RF output from the Upconverter. This pin is an open collector output. IF input for the Upconverter. This pin is a high impedance input. Bypass of the IF input. Requires grounding through an external capacitor. 15 14 Connect to ground with minimum inductance. Track length should be kept as short as possible. Power save control pin can control the On/Sleep state with bias as follows: SC O 18 Equivalent Circuit NT 11 Description D Supply Voltage UE Symbol IN Pin No. VPS (V) 1.8~5.5 0~1.0 STATE ON SLEEP Supply voltage pin for the modulator. An internal regulator helps keep the device stable against temperature or VCC variation. 19 9 UPC8104GR MODULATOR INTERNAL FUNCTIONS Block Function/Operation Block Diagram from LO1in D UE Buffer amplifiers for each phase signal are sent to each mixer. Each signal from the buffer amps is quadrature modulated with two doublebalanced mixers. High accurate phase and amplitude inputs are realized to provide excellent image rejection. Mixer Adder .. 2 F / F I I IN Buffer Amplifier x2 Q Q Output signal from each mixer is added and sent through a final amplifier stage to pin 16 for further off-chip filtering if necessary. NT 90° Phase Shifter Input signal from LO1 is sent to a T-type flip-flop through a frequency doubler. The output signal from the T-type F/F is changed to the same frequency as LO1 with a quadrature phase shift of 0°, 90°, 180°, or 270°. These circuits provide self phase correction for proper quadrature signals. TEST CIRCUIT To MODout SC O 2.7 ~ 5.5 V fLO1 = 100 to 400 MHz PIN = -10 dBm 1 LO1 IN (OPEN) 2 LO1 IN 3 GND 4 I I/Q SIGNAL GENERATOR 5 8.2 nH 1.8 pF I 19 GND 17 MOD OUT 16 UP CON IN 15 UP CON IN 14 8 GND 10 kΩ GND 18 7 Q ~ 100 to 400 MHz 100 pF ~ 100 to 400 MHz PIN = -15 dBm VCC 13 L 9 RF OUT DI VENABLE 6 Q 10 GND For 900 MHz match L = 2 nH or Microstripline equivalent Desired Matching Network Impedance, Based On Load Pull Measurements Frequency VCC 20 ΓLoad (Mag) ΓLoad (Ang) 67.7° 900 MHz 0.614 1900 MHz 0.606 169° 2450 MHz 0.318 -127° LO2 IN 12 LO2 IN 11 100 pF All capacitor values are 1000 pF unless otherwise specified. UPC8104GR INTERNAL BLOCK DIAGRAM OUTLINE DIMENSIONS (Units in mm) PACKAGE OUTLINE SSOP 20 1 90˚ Phase Shifter 11 REG 19 V PS LO1 IN 2 GND (MOD) 3 18 GND I 4 17 GND I 5 16 MOD OUT 6 15 UP CON IN (POWER SAVE) 1 7.00 MAX XXX = Lot/Date Code 10 6.4±0.2 UE Q N NEC C8104G XXXXX D LO1 IN 20 20 VCC (MOD) 4.4±0.1 1.0 1.5 ±0.1 Q 7 14 UP CON IN +0.10 0.15 -0.05 1.8 MAX GND (UP CON) 8 RF OUT 9 12 LO2 IN GND 10 (UP CON) 11 LO2 IN +0.10 0.22 - 0.05 13 VCC (UP CON) QUANTITY UPC8104GR-E1 2500/Reel NT PART NUMBER LEAD CONNECTIONS 1. LO1IN (Modulator) 2. LO1IN (Bypass) 3. GND (Modulator) 4. I Input 5. I Input 6. Q Input 7. Q Input 8. GND (Up Converter) 9. RF OUT 10. GND (Up Converter) IN ORDERING INFORMATION 0.5±0.2 0.65 0.575 MAX 11. LO2IN (Bypass) 12. LO2IN (Upconverter) 13. VCC (Up Converter) 14. Up Converter Input 15. Up Converter Input (Bypass) 16. MOD Out 17. GND 18. GND 19. VPS (Power Save) 20. VCC (Modulator) DI SC O All dimensions are typical unless specified otherwise. EXCLUSIVE NORTH AMERICAN AGENT FOR RF, MICROWAVE & OPTOELECTRONIC SEMICONDUCTORS CALIFORNIA EASTERN LABORATORIES • Headquarters • 4590 Patrick Henry Drive • Santa Clara, CA 95054-1817 • (408) 988-3500 • Telex 34-6393 • FAX (408) 988-0279 24-Hour Fax-On-Demand: 800-390-3232 (U.S. and Canada only) • Internet: http://WWW.CEL.COM PRINTED IN USA ON RECYCLED PAPER -11/97 DATA SUBJECT TO CHANGE WITHOUT NOTICE