NEC UPC8129GR

DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
µPC8129GR
UP CONVERTER WITH AGC FUNCTION + QUADRATURE MODULATOR IC
FOR DIGITAL MOBILE COMMUNICATION SYSTEMS
DESCRIPTION
The µPC8129GR is a silicon monolithic integrated circuit designed as indirect quadrature modulator for digital
mobile communication systems. This modulator consists of 0.8 GHz to 1.9 GHz up-converter and 100 MHz to 400
MHz quadrature modulator which are packaged in 20 pin SSOP. The device has power save function and can
operate 2.7 to 5.5 V supply voltage, therefore, it can contribute to make RF block small, high performance and low
power consumption.
FEATURES
• High linearity up converter is incorporated; PRFout = –5 dBm TYP./@fRFout = 900 MHz
• Wide operating frequency range. Up converter ; fRFout = 800 MHz to 1900 MHz
Modulator
; fLO1in = 200 MHz to 800 MHz
fMODout = 100 MHz to 400 MHz, fI/Q = DC to 10 MHz
• External IF filter can be applied between modulator output and up converter input terminal.
• Low phase difference due to digital phase shifter is adopted.
• Supply voltage: VCC = 2.7 to 5.5 V
• Equipped with power save function.
• 20 pin SSOP suitable for high density surface mounting.
APPLICATIONS
• Digital cellular phones (ex. GSM etc…)
• Digital cordless phones
ORDERING INFORMATION
PART NUMBER
µPC8129GR-E1
PACKAGE
20 pin plastic SSOP
(225 mil)
SUPPLYING FORM
Embossed tape 12 mm wide. QTY 2.5 kp/Reel.
Pins 1 through 10 are in pull-out direction.
* To order evaluation samples, please contact your local NEC sales office. (Part number for sample order:
µPC8129GR)
Caution electro-static sensitive device
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. P12781EJ2V0DS00 (2nd edition)
Date Published October 1999 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1997, 1999
µPC8129GR
INTERNAL BLOCK DIAGRAM AND PIN CONNECTIONS
Up-Con in
1
Up-Con inb
Reg.
20
VCC (MOD)
2
19
VCC (Up-con)
MODout
3
18
RFout
I
4
17
GND
Ib
5
16
VPS
Qb
6
15
VAGC
Q
7
14
GND
LO1 in
8
13
LO2 in
LO1 inb
9
12
LO2 inb
11
GND
90deg. Phase
Shifter ( 2)
GND
10
QUADRATURE MODULATOR SERIES PRODUCT
Part Number
Functions
ICC
(mA)
fLO1in
(MHz)
fMODout RF Mixer
(MHz) fRFout (MHz)
Phase
Shifter
Package
Application
µPC8101GR
150 MHz Quad.Mod
15/@2.7 V 100 to 300 50 to 150
µPC8104GR
RF Up-Converter + IF
Quad.Mod
28/@3.0 V
100 to 400
µPC8105GR
400 MHz Quad.Mod
16/@3.0 V
100 to 400
External
16-pin
SSOP (225 mil)
µPC8110GR
1 GHz Direct Quad.Mod
24/@3.0 V
800 to 1 000
External
µPC8125GR
RF Up-Converter + IF
Quad.Mod + AGC
36/@3.0 V
220 to 270
1 800 to 2 000
20-pin
PDC800 MHz, etc.
SSOP (225 mil)
PHS
µPC8126GR
900 MHz Direct Quad.Mod 35/@3.0 V
with Offset-Mixer
915 to 960
915 to 960
889 to 960
889 to 960
µPC8126K
µPC8129GR
×2LO IF Quad. Mod+RF
Up-Converter
External
F/F
CT-2 etc.
20-pin
SSOP (225 mil)
900 to 1 900 Doubler
Digital Comm.
+ F/F
PDC800 MHz
28-pin QFN
28/@3.0 V 200 to 800 100 to 400 800 to 1 900
F/F
20-pin
GSM,
SSOP (225 mil) DCS1800, etc.
µPC8139GR-7JH Transceiver IC
(1.9 GHz Indirect Quad.
Mod + RX-IF + IF VCO)
TX: 32.5
RX: 4.8
/@3.0 V
220 to 270
1 800 to 2 000
CR
30-pin
PHS
TSSOP (225 mil)
µPC8158K
28/@3.0 V
100 to 300
800 to 1 500
2
RF Up-Converter + IF
Quad.Mod + AGC
Data Sheet P12781EJ2V0DS00
28-pin QFN
PDC800 M/1.5 G
µPC8129GR
APPLICATION EXAMPLE
[GSM]
SUB ANT
LNA
RX
1st MIX
2nd MIX
SW
DEMO.
I
Q
MAIN ANT
1st. LO
2nd. LO
SW
PLL1
PLL2
SW
I
AGC
0°
φ (F/F)
TX
PA
MODout
= fLO/2
fLO
90 °
Q
µPC8129GR
Data Sheet P12781EJ2V0DS00
3
µPC8129GR
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
Supply Voltage
VCC
6.0
V
Power Save Voltage
VPS
6.0
V
AGC Control Voltage
VAGC
6.0
V
IQ DC Offset Voltage
IQ (DC)
4.0
V
Power Dissipation
PD
430
mW
Operating Ambient Temperature
TA
–40 to +85
°C
Storage Temperature
Tstg
–55 to +150
°C
CONDITION
TA = +25 °C
Note
TA = +85 °C
Note Mounted on double sided copper clad 50 × 50 × 1.6 mm epoxy glass PWB.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply Voltage
VCC
2.7
3.0
5.5
V
Operating Ambient Temperature
TA
–40
+25
+85
°C
fRFout
800
1900
MHz
Up Converter Input Freq.
fUPCONin
100
400
MHz
Modulator Output Frequency
fMODout
800
MHz
–5
dBm
1800
MHz
–5
dBm
10
MHz
600
mVP-P
Up Converter RF Frequency
4
LO1 Input Frequency
fLO1in
200
LO1 Input Level
PLO1in
–15
LO2 Input Frequency
fLO2in
800
LO2 Input Level
PLO2in
–15
I/Q Input Frequency
fI/Qin
DC
I/Q Input Amplitude
VI/Qin
–10
–10
Data Sheet P12781EJ2V0DS00
CONDITIONS
Single ended Input
µPC8129GR
ELECTRICAL CHARACTERISTICS (1)
Conditions (unless otherwise specified):
TA = +25 °C, VCC = 3 V, VPS = 3 V, RPS = 1 kΩ, VAGC = 3 V, RAGC = 10 kΩ
I/Q DC = 1.5 V (Vbias(I) = Vbias(Ib) = Vbias (Q) = Vbias (Qb) = 1.5 V)
fI/Qin = 67.7 kHz, VI/Qin = 500 mVP-P (single ended input, Ib = Qb = 0 mVP-P)
Modulation Pattern: <0000>
fLO1in = 500 MHz, PLO1in = –10 dBm
fLO2in = 1150 MHz, PLO2in = –10 dBm
fUPCONin = fMODout = fLO1in/2 + fI/Qin = 250 MHz + fI/Qin
fRFout = 900 MHz – fI/Qin
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
TEST CONDITIONS
20
28
37
mA
No input signal
0.6
10
µA
VPS ≤ 0.5 V
–5
–2
dBm
UP CONVERTER + QUADRATURE MODULATOR TOTAL
Total Circuit Current
Total Circuit Current at Power Save
Mode
Total Output Power
ICC(TOTAL)
ICC(PS)TOTAL1
PRFout
–8
Local Oscillator Carrier Leakage
LoL
–40
–26.5
dBc
Image Rejection (Side Band Leak)
ImR
–30
–26.5
dBc
AGC Gain Control Rang
GCR
Power Save Rise Time
TPS(rise)
2.0
Power Save Fall Time
TPS(fall)
2.0
28
40
fLoL = fLO2 – fLO1/2
dB
VAGC = 2.5 V to 0 V
5.0
µs
VPS(Low) → VPS(High)
5.0
µs
VPS(High) → VPS(Low)
ICC(PS)
(Up con.)
5.0
µA
VPS ≤ 0.5 V
ICC(PS)
(MOD)
5.0
µA
VPS ≤ 0.5 V
UP CONVERTER BLOCK
Circuit Current at Power Save Mode
QUADRATURE MODULATOR BLOCK
Circuit Current at Power Save Mode
Data Sheet P12781EJ2V0DS00
5
µPC8129GR
STANDARD CHARACTERISTICS FOR REFERENCE (1)
Conditions (unless otherwise specified):
TA = +25 °C, VCC = 3 V, VPS = 3 V, RPS = 1 kΩ, VAGC = 3 V, RAGC = 10 kΩ
I/Q DC = 1.5 V (Vbias(I) = Vbias(Ib) = Vbias (Q) = Vbias (Qb) = 1.5 V)
fI/Qin = 67.7 kHz, PI/Qin = 500 mVP-P (single ended input, Ib = Qb = 0 mVP-P)
Modulation Pattern: <0000>
fLO1in = 500 MHz, PLO1in = –10 dBm
fLO2in = 1150 MHz, PLO2in = –10 dBm
fUPCONin = fMODout = fLO1in/2 + fI/Qin = 250 MHz + fI/Qin
fRFout = 900 MHz – fI/Qin
PARAMETER
SYMBOL
REFERENCE
UNIT
TEST CONDITIONS
ICC(PS)TOTAL2
60
µA
∆φ
1.8
deg. (rms)
ICC(UpCon)
14
mA
No input signal
ICC(PS)UpCon
60
µA
VPS ≤ 0.5 V, VAGC = 0 V
CG
12
dB
PUPCONin = –20 dBm
PRF(sat)
–1.5
dBm
PUPCONin = –4 dBm
OIP3
+6
dBm
fUPCONin = 250.0 MHz/250.2 MHz
MOD. Circuit Current
ICC(MOD)
14
mA
No input signal
Output Power
PMODout
–16.5
dBm
LO1 Carrier Leakage
LoL
–40
dBc
Image Rejection (Side Band Leak)
ImR
–30
dBc
I/Q 3rd Order Intermodulation Distortion
IM3I/Q
–50
dBc
I/Q Input Impedance
ZI/Q
200
kΩ
I to Ib, Q to Qb
IQ Bias Current
II/Q
5
µA
I, Ib, Q, Qb to GND (each)
VSWR(Lo1)
1.2 : 1
–
–133
dBc/Hz
UP CONVERTER + QUADRATURE MODULATOR TOTAL
Total Circuit Current at Power-Save
Mode
Phase Error
VPS ≤ 0.5 V, VAGC = 0 V
MOD Pattern: PN9
UP CONVERTER BLOCK
UP Con. Circuit Current
UP Con. Circuit Current at Power-Save
Mode
Conversion Gain
Maximum Output Power
Output 3rd Order Intercept Point
QUADRATURE MODULATOR BLOCK
LO1 Input VSWR
Output Noise Floor
6
Data Sheet P12781EJ2V0DS00
fLoL = fLO1/2
∆f = ±20 MHz
µPC8129GR
STANDARD CHARACTERISTICS FOR REFERENCE (2)
Conditions (unless otherwise specified):
TA = +25 °C, VCC = 3 V, VPS = 3 V, RPS = 1 kΩ, VAGC = 3 V, RAGC = 10 kΩ
I/Q DC = 1.5 V (Vbias(I) = Vbias(Ib) = Vbias (Q) = Vbias (Qb) = 1.5 V)
fI/Qin = 67.7 kHz, PI/Qin = 500 mVP-P (single ended input, Ib = Qb = 0 mVP-P)
Modulation Pattern: <0000>
fLO1in = 500 MHz, PLO1in = –10 dBm
fLO2in = 1650 MHz, PLO2in = –10 dBm
fUPCONin = fMODout = fLO1in/2 + fI/Qin = 250 MHz + fI/Qin
fRFout = 1900 MHz + fI/Qin
PARAMETER
SYMBOL
REFERENCE
UNIT
TEST CONDITIONS
PRFout
–12
dBm
Local Oscillator Carrier Leakage
LoL
–40
dBc
Image Rejection (Side Band Leak)
ImR
–30
dBc
AGC Gain Control Rang
GCR
45
dB
VAGC = 2.5 V to 0 V
∆φ
1.8
deg. (rms)
MOD Pattern: PN9
CG
5
dB
PUPCONin = –20 dBm
PRF(sat)
–7
dBm
PUPCONin = –4 dBm
OIP3
–1
dBm
fUPCONin = 250.0 MHz/250.2 MHz
UP CONVERTER + QUADRATURE MODULATOR TOTAL
Total Output Power
Phase Error
fLoL = fLO2 + fLO1/2
UP CONVERTER BLOCK
Conversion Gain
Maximum Output Power
Output Intercept Point
Data Sheet P12781EJ2V0DS00
7
µPC8129GR
PIN EXPLANATION
Pin
Voltage
Typ. (V)
@VCC = 3 V
Pin No.
Symbol
Supply
Voltage
(V)
18
RFout
VCC
–
1
UpCon in
–
2.2
IF input for Up-converter.
This pin is high impedance
input.
2
UpCon inb
–
2.2
Bypass of IF input.
Grounded through external
capacitor.
Description
Equivalent Circuit
RF output from Up-Converter.
This pin is open collector output.
18
3
MODout
–
1.9
1
2
Output from modulator.
This is emitter follower output.
3
4
I
VCC/2
–
Input for I signal. This input
impedance is about 200 kΩ.
Relations between amplitude
and VCC/2 bias of input signal
are following.
VCC/2
(V)
Signal Level
(mVP-P)
≥ 1.35
≤ 400
≥ 1.5
≤ 600
≥ 1.75
≤ 1000
Note
5
Ib
VCC/2
–
Input for I signal. This input
impedance is about 200 kΩ.
VCC/2 biased DC signal should
be input.
6
Qb
VCC/2
–
Input for Q signal. This input
impedance is about 200 kΩ
VCC/2 biased DC signal should
be input.
7
Q
VCC/2
–
Input for Q signal. This input
impedance is about 200 kΩ.
Relations between amplitude
and VCC/2 bias of input signal
are following.
VCC/2
(V)
Signal Level
(mVP-P)
≥ 1.35
≤ 400
≥ 1.5
≤ 600
≥ 1.75
≤ 1000
4
5
7
6
Note
Note In the case of that I/Q input signals are single ended.
Of course, I/Q signal inputs can be used either single endedly or differentially with proper terminations.
8
Data Sheet P12781EJ2V0DS00
µPC8129GR
PIN EXPLANATION
Pin No.
Symbol
Supply
Voltage
(V)
Pin
Voltage
Typ. (V)
@VCC = 3 V
8
LO1in
–
0
9
10
LO1in b
–
2.3
GND for
Modulator
0
–
LO2in b
–
1.9
11
12
13
14
LO2in
GND for
Up-con.
–
1.9
16
VAGC
Power
Save
Lo1 input for phase shifter.
This input impedance is 50 Ω
matched internally.
Equivalent Circuit
8
50 Ω
Bypass of Lo1 input.
This pin is grounded through
internal capacitor.
9
Connect to the ground with
minimum inductance.
Track length should be kept as
short as possible.
Bypass of Lo2 input.
Grounded through external
capacitor.
13
Lo2 input of Up-converter.
This pin is high impedance input.
0
–
Connect to the ground with
minimum inductance.
Track length should be kept as
short as possible.
0 to VCC
–
Input for AGC amplifier.
Total Output Power can be
controlled by changing input
voltage.
And as external series resistance
(RAGC) connecting, a slope of
AGC curve can be changed by
the resistance (RAGC).
0 to VCC
–
Power save control pin can be
controlled ON/OFF state with
bias as follows;
17
15
Description
VPS (V)
STATE
2 to VCC
ON (Active Mode)
0 to 0.5
OFF (Sleep Mode)
19
VCC for
Upconverter
2.7 to 5.5
–
Supply voltage pin for Upconverter.
20
VCC for
Modulator
2.7 to 5.5
–
Supply voltage pin for modulator.
Internal regulator can be kept
stable condition of supply bias
against the variable
temperature or VCC.
12
16
: Externally
Data Sheet P12781EJ2V0DS00
9
µPC8129GR
STANDARD TYPICAL CHARACTERISTICS <Modulator + Up-Converter Total at 900 MHz>
Test Circuit 1, TA = +25 °C, VCC = 3 V, VPS = 3 V, RPS = 1 kΩ, VAGC = 3 V, RAGC = 10 kΩ
I/Q DC = 1.5 V (Vbias(I) = Vbias(Ib) = Vbias(Q) = Vbias(Qb) = 1.5 V)
fI/Qin = 67.7 kHz, VI/Qin = 500 mVP-P (single ended input, Ib = Qb = 0 mVP-P)
Modulation Pattern: All Zero <0000>, fLO1in = 500 MHz, PLO1in = –10 dBm
fLO2in = 1150 MHz, PLO2in = –10 dBm, fUPCONin = fMODout = fLO1in/2 + fI/Qin = 250 MHz + fI/Qin
fRFout = 900 MHz – fI/Qin, Unless Otherwise Specified
ICC (TOTAL) vs VCC
ICC (TOTAL) vs VPS
ICC - Total Circuit Current - mA
ICC - Total Circuit Current - mA
No input signal
40
30
20
10
30
20
10
: TA = +25 °C
: TA = +85 °C
: TA = –40 °C
No input signal
0
1
2
3
4
5
0
6
ICC - Total Circuit Current - mA
10
0
+20
+40
+60
+80
No input signal
Vps = 0.5 V
30
20
10
0
TA - Operating Ambient Temperature - °C
10
3
ICC (PS) TOTAL vs TA
20
–20
2
ICC (TOTAL) vs TA
No input signal
–40
1
VPS - Power Save Control Voltage - V
30
0
0
VCC - Supply Voltage - V
ICC - Total Circuit Current at Power Save Mode - µ A
0
Data Sheet P12781EJ2V0DS00
–40
–20
0
+20
+40
+60
+80
TA - Operating Ambient Temperature - °C
µPC8129GR
ICC (PS) TOTAL1 vs VCC
150
ICC - Total Circuit Current at Power Save Mode - µ A
ICC - Total Circuit Current at Power Save Mode - µ A
ICC (PS) TOTAL2 vs TA
No input signal
Vps = 0.5 V
VAGC = 0 V
125
100
75
50
25
0
–40
–20
0
+20
+40
+60
+80
No input signal
Vps = 0.5 V
2
1
0
0
2
TA - Operating Ambient Temperature - °C
4
6
VCC - Supply Voltage - V
ICC - Total Circuit Current at Power Save Mode - µ A
ICC (PS) TOTAL2 vs VCC
150
No input signal
Vps = 0.5 V
VAGC = 0 V
125
100
75
50
25
0
0
2
4
6
VCC - Supply Voltage - V
–20
PRFout
ImR
–10
–30
LoL
–20
–40
IM3I/Q
–30
–50
0
1
2
3
4
VCC - Supply Voltage - V
5
6
PRFout - Total Output Power - dBm
0
–20
0
PRFout
ImR
–10
–30
–20
IM3I/Q
–40
LoL
–40 –20
0
+20 +40 +60 +80
TA - Operating Ambient Temperature - °C
Data Sheet P12781EJ2V0DS00
–50
LoL - Local Oscillator Carrier Leakage - dBc
ImR - Image Rejection - dBc
IM3I/Q - I/Q 3rd Order Intermodulation Distortion - dBc
PRFout, LoL, ImR, IM3I/Q vs TA
LoL - Local Oscillator Carrier Leakage - dBc
ImR - Image Rejection - dBc
IM3I/Q - I/Q 3rd Order Intermodulation Distortion - dBc
PRFout - Total Output Power - dBm
PRFout, LoL, ImR, IM3I/Q vs VCC
11
µPC8129GR
ImR
–10
–30
PRFout
–20
–40
–30
–50
–40
–60
IM3I/Q
100
500
1000
–70
2000
–20
0
PRFout
ImR
–30
–10
LoL
–40
–20
IM3I/Q
–50
–30
–30
–20
VI/Qin - I/Q Input Amplitude - mVp-p
–10
0
+10
PLO1in - LO1 Input Level - dBm
∆Φ vs VI/Qin
PRFout vs PLO2in
7
∆Φ - Phase Error - deg. (rms.)
PRFout - Total Output Power - dBm
MOD Pattern: PN9
0
–10
–20
–30
6
5
4
3
2
1
–40
–40
–30
–20
–10
0
0
100
500
1000
PLO2in - LO2 Input Level - dBm
VI/Qin - I/Q Input Amplitude - mVP-P
PRFout vs VAGC
PRFout vs VAGC
–30
TA = +85 °C
–40
+25 °C
–50
–40 °C
–60
–70
0
1
2
3
–20
–30
GCR
= 40.5 dB
(VCC = 2.7 V)
GCR
= 41.7 dB
(VCC = 5.5 V)
–40
–50
–60
0
VAGC - AGC Control Voltage - V
12
GCR
= 40.8 dB
(VCC = 3 V)
VCC = 5.5 V
–20
–10
VCC = 3 V
–10
0
VCC = 2.7 V
0
PRFout - Total Output Power - dBm
PRFout - Total Output Power - dBm
+10
1
2
3
4
5
VAGC - AGC Control Voltage - V
Data Sheet P12781EJ2V0DS00
6
PRFout - Total Output Power - dBm
–20
LoL
LoL - Local Oscillator Carrier Leakage - dBc
ImR - Image Rejection - dBc
IM3I/O - I/Q 3rd Order Intermodulation Distortion - dBc
0
PRFout, LoL, ImR, IM3I/Q vs PLO1in
LoL - Local Oscillator Carrier Leakage - dBc
ImR - Image Rejection - dBc
IM3I/O - I/Q 3rd Order Intermodulation Distortion - dBc
PRFout - Total Output Power - dBm
PRFout, LoL, ImR, IM3I/Q vs VI/Qin
µPC8129GR
PRFout vs VAGC
+10
ATT 10dB
=8
0k
10 kΩ,
GC
–30
GCR =
39.8 dB
SLOPE
Ω,
–20
= 143
SL
OP
E=
–10
dB/V
53
dB
/V
0
RA
–40
RAGC =
PRFout - Total Output Power - dBm
POWER SAVE RESPONSE
µPC8129GR
REF 0.0 dBm
10 dB/
RBW
3 MHz
VBW
3 MHz
–50
–60
0
1
2
3
SWP
50 µ s
CENTER 900.0677 MHz
SPAN 0 Hz
VAGC - AGC Control Voltage - V
TYPICAL SINE WAVE MODULATION OUTPUT SPECTRUM
1 ATT 10 dB
µPC8129GR
REF 0.0 dBm
10 dB/
TYPICAL GMSK MODULATION OUTPUT SPECTRUM
ATT 0 dB
µPC8129GR
REF –10.0 dBm
10 dB/
A write B view
MARKER
899.200 MHz
–77.25 dB
3
4
ADJ BS
135 kHz
2
3
4
DL –10.0 dBm
2
1
RBW 3 kHz
RBW 3 kHz
VBW 10 kHz
VBW 10 kHz
SWP 1.0 s
5
6
SWP 5.0 s
CENTER 900.0000 MHz
SPAN 500 KHz
*** Multi Marker List ***
No.1: 899.9323 MHz
–4.80 dBm
No.2: 900.0000 MHz
–48.02 dBc
No.3: 900.0677 MHz
–29.88 dBc
No.4: 900.2031 MHz
–42.41 dBc
TYPICAL SINE WAVE MODULATION OUTPUT SPECTRUM
ATT 10 dB
µPC8129GR
REF 0.0 dBm
10 dB/
MARKER
900 MHz
–4.67 dBm
CENTER 900. 000 MHz
No.1:
No.2:
No.3:
No.4:
No.5:
No.6:
∆:
SPAN 2.000 MHz
*** Multi Marker List ***
899.200 MHz
–77.25 dB
899.400 MHz
–76.50 dB
899.600 MHz
–68.00 dB
900.400 MHz
–68.25 dB
900.600 MHz
–77.50 dB
900.800 MHz
–77.50 dB
TYPICAL SINE WAVE MODULATION OUTPUT SPECTRUM
(IN BAND)
ATT 10 dB
µPC8129GR
REF 0.0 dBm
10 dB/
MARKER
900 MHz
–4.68 dBm
MKR 900 MHz
1
2 fLO1in
(= fIF) fLO1in
(= 2fIF)
fLO2in
750 MHz
–43.6 dBm
3
2
fLO1in
(= 3fIF)
2 fLO1in
(= 4fIF)
800 MHz
–49.5 dBm
850 MHz
–56.6 dBm
5
2
fLO1in
(=
5fIF)
1000 MHz
–53.0 dBm
950 MHz
–68.2 dBm
RBW 300 kHz
RBW 300 kHz
VBW 300 kHz
VBW 300 kHz
1050 MHz
–59.4 dBm
SWP 5.0 s
SWP 5.0 s
START 0 Hz
STOP 2.460 GHz
Data Sheet P12781EJ2V0DS00
CENTER 900.0 MHz
SPAN 400.0 MHz
13
µPC8129GR
TYPICAL SINE WAVE MODULATION OUTPUT SPECTRUM
(IN BAND)
µPC8129GR
REF 0.0 dBm
10 dB/
ATT 10 dB
fLO1in = 500 MHz
(fMODout = 250 MHz
+ fI/Q)
fLO2 = 1130 MHz
fRFout = 880 MHz
MARKER
880.0 MHz
–4.64 dBm
TYPICAL SINE WAVE MODULATION OUTPUT SPECTRUM
(IN BAND)
1010 MHz
–57.6 dBm
890 MHz
–63.0 dBm
1000 MHz
–54.8 dBm
950 MHz
–65.5 dBm
RBW 300 kHz
VBW 300 kHz
VBW 300 kHz
SWP 5.0 s
SWP 5.0 s
CENTER 920.0 MHz
SPAN 200.0 MHz
TYPICAL SINE WAVE MODULATION OUTPUT SPECTRUM
(IN BAND)
ATT 10 dB
fLO1in = 500 MHz
(fMODout = 250 MHz
+ fI/Qin)
fLO2in = 1210 MHz
fRFout = 960 MHz
– fI/Qin
MARKER
900 MHz
–7.41 dBm
920 MHz
–51.5 dBm
1000 MHz
–49.9 dBm
880 MHz
–59.9 dBm
RBW 300 kHz
VBW 300 kHz
SWP 5.0 s
CENTER 920.0 MHz
14
1000 MHz
–53.0 dBm
850 MHz
–56.2 dBm
RBW 300 kHz
MKR 900 MHz
MARKER
900 MHz
–4.66 dBm
MKR 900 MHz
870 MHz
–55.7 dBm
µPC8129GR
REF 0.0 dBm
10 dB/
ATT 10 dB
µPC8129GR
REF 0.0 dBm
10 dB/
SPAN 200.0 MHz
Data Sheet P12781EJ2V0DS00
CENTER 920.0 MHz
SPAN 200.0 MHz
µPC8129GR
STANDARD TYPICAL CHARACTERISTICS <Modulator + Up-Converter Total at 1900 MHz>
Test Circuit 2, TA = +25 °C, VCC = 3 V, VPS = 3 V, RPS = 1 kΩ, VAGC = 3 V, RAGC = 10 kΩ
I/Q DC = 1.5 V (Vbias(I) = Vbias(Ib) = Vbias(Q) = Vbias(Qb) = 1.5 V)
fI/Qin = 67.7 kHz, VI/Qin = 500 mVP-P (single ended input, Ib = Qb = 0 mVP-P)
Modulation Pattern: All Zero <0000>, fLO1in = 500 MHz, PLO1in = –10 dBm
fLO2in = 500 MHz, PLO2in = –10 dBm, fUPCONin = fMODout = fLO1in/2 + fI/Qin = 250 MHz + fI/Qin
fRFout = 1900 MHz + fI/Qin, Unless Otherwise Specified
PRFout vs VAGC
PRFout vs VI/Qin
0
C
=8
–40
RAGC =
–50
GCR =
45.4 dB
10 kΩ,
0k
Ω,
SLOPE
SLO
–30
PRFout - Total Output Power - dBm
PE
–20
= 154
=5
9d
dB/V
B/V
–10
RAG
PRFout - Total Output Power - dBm
0
–60
–70
0
1
2
–30
–40
100
500
1000
2000
VAGC - AGC Control Voltage - V
VI/Qin - I/Q Input Amplitude - mVP-P
PRFout vs PLO1in
PRFout vs PLO2in
0
PRFout - Total Output Power - dBm
PRFout - Total Output Power - dBm
–20
3
0
–10
–20
–30
–30
–10
–20
–10
0
+10
–10
–20
–30
–40
PLO1in - LO1 Input Level - dBm
–30
–20
–10
0
+10
PLO2in - LO2 Input Level - dBm
Data Sheet P12781EJ2V0DS00
15
µPC8129GR
∆Φ vs VI/Qin
TYPICAL SINE WAVE MODULATION OUTPUT SPECTRUM
ATT 10 dB
µPC8129GR
REF 0.0 dBm
10 dB/
7
MOD Pattern: PN9
1
∆Φ - Phase Error - deg. (rms)
6
5
3
4
2
4
3
2
RBW 3 kHz
1
VBW 10 kHz
0
100
500
1000
2000
SWP 1.0 s
CENTER 1.9000000 GHz
SPAN 500 kHz
*** Multi Marker List ***
No.1: 1.9000677 GHz
–12.13 dBm
No.2: 1.9000000 GHz
–39.30 dBc
No.3: 1.8999323 GHz
–28.98 dBc
No.4: 1.8997969 GHz
–41.30 dBc
VI/Qin - I/Q Input Amplitude - mVp-p
TYPICAL GMSK MODULATION OUTPUT SPECTRUM
ATT 0 dB
µPC8129GR
REF –10.0 dBm
10 dB/
A write B view
MARKER
1. 899200 GHz
–74. 75 dB
TYPICAL SINE WAVE MODULATION OUTPUT SPECTRUM
ATT 10 dB
µPC8129GR
REF 0.0 dBm
10 dB/
MARKER
1.900 GHz
–11. 67 dBm
fLO2in
1
2
fLO1in
(= fIF)
MKR 1.900 GHz
fLO1in
(= 2fIF) 32 fLO1in
MKR
1.899200 GHz
(= 3fIF)
2 fLO1in
(= 4fIF)
3
DL –10.0 dBm
1
4
2
5
5
2 fLO1in
(= 5fIF)
4 fLO1in
3 fLO1in 72 fLO1in (= 8fIF)
(= 6fIF) (= 7fIF)
6
RBW 3 kHz
RBW 300 kHz
VBW 10 kHz
VBW 300 kHz
SWP 5.0 s
SWP 5.0 s
CENTER 1.900000 GHz
No.1:
No.2:
No.3:
No.4:
No.5:
No.6:
∆:
SPAN 2. 000 MHz
START 0 Hz
*** Multi Marker List ***
1.899200 GHz
–74.75 dB
1.899400 GHz
–74.50 dB
1.899600 GHz
–64.75 dB
1.900400 GHz
–66.50 dB
1.900600 GHz
–74.25 dB
1.900800 GHz
–74.75 dB
TYPICAL SINE WAVE MODULATION OUTPUT SPECTRUM
(IN BAND)
ATT 10 dB
µPC8129GR
REF 0.0 dBm
10 dB/
TYPICAL SINE WAVE MODULATION OUTPUT SPECTRUM
(IN BAND)
ATT 10 dB
µPC8129GR
REF 0.0 dBm
10 dB/
1
STOP 2.500 GHz
fRFout = 1.71 GHz
+ fI/Qin
fLO2in = 1.46 GHz
2
1
6
7
4
3
4
5
6
7
3
RBW 300 kHz
RBW 300 kHz
VBW 300 kHz
VBW 300 kHz
SWP 5.0 s
SWP 5.0 s
CENTER 1.9000 GHz
No.1:
No.2:
No.3:
No.4:
No.5:
No.6:
No.7:
16
5
2
SPAN 600 MHz
CENTER 1.7950 GHz
*** Multi Marker List ***
1.900 GHz
–11.71 dBm
1.650 GHz
–24.07 dBm
1.750 GHz
–64.52 dBm
1.800 GHz
–63.37 dBm
2.000 GHz
–61.09 dBm
2.050 GHz
–59.39 dBm
2.150 GHz
–31.62 dBm
No.1:
No.2:
No.3:
No.4:
No.5:
No.6:
No.7:
Data Sheet P12781EJ2V0DS00
SPAN 600 MHz
*** Multi Marker List ***
1.710 GHz
–15.16 dBm
1.670 GHz
–61.50 dBm
1.750 GHz
–67.84 dBm
1.920 GHz
–46.33 dBm
1.940 GHz
–58.68 dBm
1.960 GHz
–27.94 dBm
2.000 GHz
–62.11 dBm
µPC8129GR
TYPICAL SINE WAVE MODULATION OUTPUT SPECTRUM
(IN BAND)
ATT 10 dB
µPC8129GR
REF 0.0 dBm
10 dB/
fRFout = 1.795 GHz
+ fI/Qin
fLO2in = 1.545 GHz
1
2
TYPICAL SINE WAVE MODULATION OUTPUT SPECTRUM
(IN BAND)
ATT 10 dB
µPC8129GR
REF 0.0 dBm
10 dB/
1
2
7
5
3
6
34
4
RBW 300 kHz
RBW 300 kHz
VBW 300 kHz
VBW 300 kHz
SWP 5.0 s
fRFout = 1.88 GHz
+ fI/Qin
fLO2in = 1.63 GHz
56
SWP 5.0 s
CENTER 1.7950 GHz
No.1:
No.2:
No.3:
No.4:
No.5:
No.6:
No.7:
*** Multi Marker List ***
1.795 GHz
1.545 GHz
1.590 GHz
1.750 GHz
1.840 GHz
2.000 GHz
2.045 GHz
SPAN 600 MHz
CENTER 1.7950 GHz
–14.21 dBm
–24.47 dBm
–65.96 dBm
–66.40 dBm
–60.91 dBm
–61.79 dBm
–28.73 dBm
No.1:
No.2:
No.3:
No.4:
No.5:
No.6:
Data Sheet P12781EJ2V0DS00
*** Multi Marker List ***
1.880 GHz
1.630 GHz
1.750 GHz
1.760 GHz
2.000 GHz
2.010 GHz
SPAN 600 MHz
–12.32 dBm
–23.47 dBm
–64.08 dBm
–63.19 dBm
–61.05 dBm
–60.25 dBm
17
µPC8129GR
STANDARD TYPICAL CHARACTERISTICS <Up-Converter Block>
TA = +25 °C, VCC = 3.0 V, VPS = 3.0 V, fUPCONin = 250 MHz, PUPCONin = –20 dBm
Test Circuit 1 (fRFout = 900 MHz, fLO2in = 1150 MHz) or
Test Circuit 2 (fRFout = 1900 MHz, fLO2in = 1650 MHz), Unless Otherwise Specified
–20
ut
Fo
PR
–30
3
–40
–50
–60
–70
–50
–40
–30
–20
–10
0
–40
–50
–60
–70
–80
–50
CG - Conversion Gain - dB
15
fRFout = 900 MHz
fLO2in = 1.15 GHz
5
fRFout = 1.9 GHz
fLO2in = 1.65 GHz
0
–30
–20
–10
0
PLO2in - LO2 Input Level - dBm
18
Fo
PR
–30
CG vs PLO2in
–40
ut
–20
PUPCONin - Up-Converter Input Level - dBm
10
OIP3
= –1.3 dBm
fRFout = 1.9000/1.9002 GHz
–10
3
fRFout = 899.8/900.0 MHz
–10
fUpConin = 250.0/250.2 MHz
0 fLO2in = 1.65 GHz
IM
OIP3
= +5.8 dBm
0 fLO2in = 1.15 GHz
PRFout - Output Power - dBm
IM3 - 3rd Order Intermoduration Distortion - dBm
fUpConin = 250.0/250.2 MHz
PRFout, IM3, vs PUpConin
IM
PRFout - Output Power - dBm
IM3 - 3rd Order Intermoduration Distortion - dBm
PRFout, IM3, vs PUpConin
Data Sheet P12781EJ2V0DS00
–40
–30
–20
–10
0
PUPCONin - Up-Converter Input Level - dBm
µPC8129GR
STANDARD TYPICAL CHARACTERISTICS <Modulator Block>
Test Circuit 1 or 2, TA = +25 °C, VCC = 3 V, VPS = 3 V
I/Q DC = 1.5 V (Vbias(I) = Vbias(Ib) = Vbias(Q) = Vbias(Qb) = 1.5 V)
fI/Qin = 67.7 kHz, VI/Qin = 500 mVP-P (single ended input, Ib = Qb = 0 mVP-P)
Modulation Pattern: All Zero <0000>, fLO1in = 500 MHz, PLO1in = –10 dBm
fMODout = fLO1in/2 + fI/Qin = 250 MHz + fI/Qin, Unless Otherwise Specified
PMODout vs VI/Qin
PMODout vs PLO1in
PMODout - Moduration Output Power - dBm
+10
0
–10
–20
–30
–40
100
200
500
1000
PMODout - Moduration Output Power - dBm
–20
–10
–20
–30
–40
–30
–20
–10
VI/Qin - I/Q Input Amplitude - mVP-P
PLO1in - LO1 Input Level - dBm
PMODout, LoL, ImR, IM3I/Q vs fLO1in
∆Φ vs VI/Qin
0
–10
0
–50
–40
2000
–20
PRFout
–30
LoL
–30
–40
ImR
–40
–50
–50
–60
IM3I/Q
100
200
500
1000
2000
–70
0
3
MOD Pattern: PN9
∆Φ - Phase Error - deg. (rms.)
–50
LoL - Local Oscillator Carrier Leakage - dBc
ImR - Image Rejection - dBc
IM3I/Q - I/Q 3rd Order Intermodulation Distortion - dBc
PMODout - Moduration Output Power - dBm
+10
2
1
fLO1in - LO1 Input Frequency - MHz
100
200
500
1000
2000
VI/Qin - I/Q Input Amplitude - mVP-P
Data Sheet P12781EJ2V0DS00
19
µPC8129GR
∆Φ vs fLO1in
TYPICAL SINE WAVE MODULATION OUTPUT SPECTRUM
MOD Pattern: PN9
∆Φ - Phase Error - deg. (rms.)
ATT 10 dB
µPC8129GR
REF 0.0 dBm
10 dB/
7
1
6
5
3
4
2
3
4
2
RBW 3 kHz
1
VBW 10 kHz
0
100
200
500
1000
2000
fLO1in - LO1 Input Frequency - MHz
20
SWP 1.0 s
CENTER 250.0000 MHz
SPAN 500 kMHz
*** Multi Marker List ***
–16.37 dBm
No.1: 250.0677 MHz
–39.49 dBc
No.2: 250.0000 MHz
–31.07 dBc
No.3: 249.9323 MHz
–58.80 dBc
No.4: 249.7969 MHz
Data Sheet P12781EJ2V0DS00
µPC8129GR
LO1 INPUT (Pin8) IMPEDANCE
VCC = VPS = 3 V
MOD OUTPUT (Pin3) IMPEDANCE
VCC = VPS = 3 V
CH1 S11 1 U FS 2: 47.998 Ω 0.8066 Ω 256.76 pH
500.000 000 MHz
MARKER 2
500 MHz
CH1 S22 1 U FS 2: 31.195 Ω 14.908 Ω 9.4909 nH
250.000 000 MHz
MARKER 2
250 MHz
2
3
2
1
31
MARKER
1: 100 MHz
2: 250 MHz
3: 400 MHz
MARKER
1: 200 MHz
2: 500 MHz
3: 800 MHz
START 100.000 000 MHz
STOP 1 000.000 000 MHz
START 50.000 000 MHz
Up-Con. INPUT (Pin1) IMPEDANCE
VCC = VPS = 3 V
STOP 500.000 000 MHz
LO2 INPUT (Pin13) IMPEDANCE
VCC = VPS = 3 V
CH1 S11 1 U FS 2: 101.78 Ω –387.03 Ω 1.6449 pF
250. 000 000 MHz
MARKER 2
250 MHz
CH1 S11 1 U FS 1: 22.379 Ω –93.543 Ω 1.8905 pF
900.000 000 MHz
MARKER 1
900 MHz
2
1
3 MARKER
1
1: 100 MHz
2: 250 MHz
3: 400 MHz
START 50.000 000 MHz
STOP 500.000 000 MHz
3
2
START 800.000 000 MHz
MARKER
1: 900 MHz
2: 1150 MHz
3: 1900 MHz
STOP 2 000.000 000 MHz
RF OUTPUT (Pin18) IMPEDANCE
VCC = VPS = 3 V
CH1 S22 1 U FS 1: 18.953 Ω –158.83 Ω 1.1134 pF
900.000 000 MHz
MARKER 1
Connect to inductor
900 MHz
(L2 = 100 nH)
between pin18 and
pin19
1
2
3
START 800.000 000 MHz
MARKER
1: 900 MHz
2: 1150 MHz
3: 1900 MHz
STOP 2 000.000 000 MHz
Data Sheet P12781EJ2V0DS00
21
µPC8129GR
TEST CIRCUIT 1 (In the case of fRFout = 900 MHz Band)
1
Up-Con. in
VCC(MOD.)
10 nF VCC
20
1000 pF
100 pF
100 pF
2
Up-Con. inb
VCC(UP-CON.)
19
3
MODout
RFout
18
4
I
GND
17
Ib(DC)
5
Ib
VPS
16
6
Qb
VAGC
15
Q(DC), VQin
7
Q
GND
14
8
LO1in
LO2in
13
1000 pF
10 nF
RAGC = 10 kΩ
Note 1
ZL = 50 Ω
6.8 nH
100 pF
9
LO1inb
LO2inb
4 pF
12
100 pF
10
GND
Notes 1. 50 Ω matching circuit at fLO2in = 1150 MHz.
In the case of using NEC’s evaluation board.
2. 50 Ω matching circuit at fRFout = 900 MHz.
In the case of using NEC’s evaluation board.
Data Sheet P12781EJ2V0DS00
GND
11
VAGC
10 nF
LO1in
22
100 pF
6 pF
1000 pF
(Open)
fRFout
Note 2
RPS = 1 kΩ
10 nF Vps
10 nF
Qb(DC)
10 nF VCC
1000 pF
ZL = 50 Ω
15 nH
I(DC), VIin
84 nH
LO2in
100 pF
µPC8129GR
TEST CIRCUIT 2 (In the case of fRFout = 1900 MHz Band)
1
Up-Con. in
VCC(MOD.)
10 nF VCC
20
1000 pF
100 pF
100 pF
VCC(UP-CON.)
19
RFout
18
GND
17
Ib
VPS
16
6
Qb
VAGC
15
7
Q
GND
14
8
LO1in
LO2in
13
2
Up-Con. inb
3
MODout
4
I
5
10 nF
Qb(DC)
Q(DC), VQin
1000 pF
ZL = 50 Ω
3 pF
I(DC), VIin
Ib(DC)
68 nH
1000 pF
10 nF
10 nF VCC
fRFout
100 pF
Note 2
RPS = 1 kΩ
10 nF Vps
RAGC = 10 kΩ 10 nF VAGC
1000 pF
LO1in
100 pF
Note 1
ZL = 50 Ω
2 pF
(Open)
9
LO1inb
LO2inb
LO2in
100 pF
12
100 pF
10
GND
GND
11
Notes 1. 50 Ω matching circuit at fLO2in = 1650 MHz.
In the case of using NEC’s evaluation board.
2. 50 Ω matching circuit at fRFout = 1900 MHz.
In the case of using NEC’s evaluation board.
Data Sheet P12781EJ2V0DS00
23
µPC8129GR
Qb
C = 10 nF
C = 100 pF
L = 6.8 nH
RAGC
= 10 kΩ
C = 10 nF
C = 100 pF
Ib
C = 10 nF
C = 100 pF
C = 1000 pF
C = 1000 pF
C = 1000 pF
L = 15 nH
C = 100 pF
C = 10 nF
VCC
L=
84 nH
C = 6 pF
RPS = 1 kΩ
C = 10 nF
VPS
VAGC
C = 10 nF
C = 4 pF
C = 100 pF
C = 100 pF
C = 10 nF
fLO2in = 1150 MHz
fRFout = 900 MHz
fLO1in = 500 MHz
(fMODout = 250 MHz + fI/Qin)
EXAMPLE OF TEST CIRCUIT 1 ASSEMBLED ON EVALUATION BOARD
Notes 1. Double-sided patterning with 35 µm thick copper on 50 × 50 × 0.4 mm polyimide board.
2. GND pattern on backside.
3. Solder coating over patterns.
4.
,
indicate through-holes.
NOTICE The test circuits and board pattern on data sheet are for performance evaluation use only. In the
case of actual design-in, matching circuit should be determined using S-parameter of desired
frequency in accordance to actual mounting pattern.
24
Data Sheet P12781EJ2V0DS00
µPC8129GR
C = 1000 pF
C = 100 pF
C = 1000 pF
C = 100 pF
C = 100 pF
C = 1000 pF
C=
1000 pF
L = 68 nH
RPS = 1 kΩ
C = 3 pF
Ib
C = 10 nF
C = 100 pF
C = 10 nF
VCC
C = 10 nF
VPS
VAGC
RAGC
= 10 kΩ
C = 10 nF
C = 2 pF
C = 100 pF
C = 100 pF
C = 10 nF
Qb
fLO2in = 1.65 GHz
fRFout = 1.9 GHz + fI/Qin
fLO1in = 500 MHz
(fMODout = 250 MHz + fI/Qin)
EXAMPLE OF TEST CIRCUIT 2 ASSEMBLED ON EVALUATION BOARD
Notes 1. Double-sided patterning with 35 µm thick copper on polyimide board.
2. GND pattern on backside.
3. Solder coating over patterns.
4.
,
indicate through-holes.
NOTICE The test circuits and board pattern on data sheet are for performance evaluation use only. In the
case of actual design-in, matching circuit should be determined using S-parameter of desired
frequency in accordance to actual mounting pattern.
Data Sheet P12781EJ2V0DS00
25
µPC8129GR
PACKAGE DIMENSIONS
20 PIN PLASTIC SSOP (225 mil) (UNIT: mm)
20
11
detail of lead end
+7˚
3˚–3˚
1
10
6.7 ± 0.3
6.4 ± 0.2
1.8 MAX.
4.4 ± 0.1
1.5 ± 0.1
1.0 ± 0.2
0.5 ± 0.2
0.15
0.65
+0.10
0.22 –0.05
0.15
+0.10
–0.05
0.575 MAX.
0.10 M
0.1 ± 0.1
NOTE
26
Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition.
Data Sheet P12781EJ2V0DS00
µPC8129GR
NOTE ON CORRECT USE
(1) Observe precautions for handling because of electrostatic sensitive devices.
(2) Form a ground pattern as widely as possible to minimize ground impedance (to prevent undesired oscillation).
(3) Keep the track length of the ground pins as short as possible.
(4) Connect a bypass capacitor (e.x. 1000 pF) to the VCC pin.
RECOMMENDED SOLDERING CONDITIONS
This product should be soldered in the following recommended conditions.
Other soldering method and
conditions than the recommended conditions are to be consulted with sales representatives.
µPC8129GR
Soldering process
Soldering conditions
Symbol
Infrared ray reflow
Peak package’s surface temperature: 235 °C or below,
Reflow time: 30 seconds or below (210 °C or higher)
Note
Number of reflow process: 2, Exposure limit : None
IR35-00-2
VPS
Peak package’s surface temperature: 215 °C or below,
Reflow time: 40 seconds or below (200 °C or higher)
Note
Number of reflow process: 2, Exposure limit : None
VP15-00-2
Wave soldering
Solder temperature: 260 °C or below,
Flow time: 10 seconds or below,
Note
Number of flow process: 1, Exposure limit : None
WS60-00-1
Partial heating method
Terminal temperature: 300 °C or below,
Flow time: 3 seconds/pin or below,
Note
Exposure limit : None
Note Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25 °C and relative humidity at 65 % or less.
Caution Apply only a single process at once, except for “Partial heating method”.
For details of recommended soldering conditions for surface mounting, refer to information
document SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL (C10535E).
Data Sheet P12781EJ2V0DS00
27
µPC8129GR
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
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