NEC UPC8104GR

PRELIMINARY DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
µPC8158K
RF UP-CONVERTER WITH AGC FUNCTION + IF QUADRATURE MODULATOR IC
FOR DIGITAL MOBILE COMMUNICATION SYSTEMS
DESCRIPTION
The µPC8158K is a silicon microwave monolithic integrated circuit designed as quadrature modulator for digital
mobile communication systems. This MMIC consists of 0.8 GHz to 1.5 GHz up-converter and 100 MHz to 300 MHz
quadrature modulator which are equipped with AGC and power save functions.
This configuration suits to IF
modulation system. The package is 28-pin QFN suitable for high density mounting. The chip is manufactured using
NEC’s.
20 GHz fT silicon bipolar process NESATTM III to realize low power consumption.
Consequently the
µPC8158K can contribute to make RF blocks smaller size, higher performance and lower power consumption.
FEATURES
•
•
•
•
•
Supply voltage: VCC = 2.7 to 4.0 V, ICC = 28 mA @ VCC = 3.0 V
Built-in LPF suppresses spurious multipled by TX local (LO1)
AGC amplifier is installed in local port of up converter: GCR = 35 dB MIN. @ fout = 1.5 GHz
Excellent performance: Padj = –65 dBc TYP. @ ∆f = ±50 kHz, EVM = 1.2 % rms TYP.
External IF filter can be applied between modulator output and up converter input terminal.
APPLICATIONS
• Digital cellular phones (PDC800M, PDC1.5G and so on)
ORDERING INFORMATION
Part Number
µPC8158K-E1
Package
28-pin plastic QFN
(5.1 × 5.5 × 0.95 mm)
Supplying Form
Embossed tape 12 mm wide.
Pin 1 is in pull-out direction.
QTY 2.5 kp/Reel.
Remark To order evaluation samples, please contact your local NEC sales office. (Part number for sample order:
µPC8158K)
Caution
Electro-static sensitive device
The information in this document is subject to change without notice.
Document No. P13831EJ1V1DS00 (1st edition)
Date Published January 1999 N CP(K)
Printed in Japan
©
1998
µPC8158K
17
16
N.C.
GND
18
QMOD + AGC + Up-Mix
VPS/VAGC
GND
19
N.C.
20
QMOD + AGC + Up-Mix
VCC
21
QMOD + AGC + Up-Mix
GND
22
Output Buffer
N.C.
INTERNAL BLOCK DIAGRAM AND PIN CONNECTIONS (TOP View)
15
AGCcont
RFout
23
N.C.
24
Up-Mix
14
LO2inb
13
LO2in
12
GND
QMOD + AGC + Up-Mix
11
VCC
QMOD + AGC + Up-Mix
10
LO1in
AGC
VCC
Output Buffer
REG
25
LPF
Fil1
26
Fil2
27
REG
φ
GND
28 I/Q-Mix
QMOD + AGC + Up-Mix
9
2
2
3
4
5
6
7
8
N.C.
Qinb
Qin
N.C.
N.C.
N.C.
Iin
1
Iinb
Phase
Shifter
Preliminary Data Sheet P13831EJ1V1DS00
LO1inb
µPC8158K
QUADRATURE MODULATOR SERIES
Part Number
Functions
ICC (mA)
fLO1in
(MHz)
fMODout
(MHz)
50 to 150
µPC8101GR
150 MHz Quad. Mod
15/@ 2.7 V 100 to 300
µPC8104GR
RF Up-Converter + IF
Quad. Mod
28/@ 3.0 V
µPC8105GR
400 MHz Quad. Mod
µPC8110GR
Up-Converter Phase
fRFout (MHz) Shifter
Package
Application
External
F/F
100 to 400
900 to 1 900
Doubler
+ F/F
16/@ 3.0 V
100 to 400
External
16-pin
SSOP (225 mil)
1GHz Direct Quad. Mod
24/@ 3.0 V
800 to 1 000
Direct
20-pin
SSOP (225 mil)
µPC8125GR
RF Up-Converter + IF
Quad. Mod + AGC
36/@ 3.0 V
220 to 270
1 800 to 2 000
PHS
µPC8126GR
900 MHz Direct Quad.
Mod with Offset-Mixer
35/@ 3.0 V
915 to 960
915 to 960
(LO pre-mixer)
PDC800 MHz
×2LO IF Quad. Mod +
RF Up-Converter
28/@ 3.0 V 200 to 800 100 to 400
800 to 1900
F/F
20-pin
SSOP (225 mil)
GSM,
DCS1800, etc.
µPC8139GR-7JH Transceiver IC
(1.9 GHz Indirect Quad.
Mod + RX-IF + IF VCO)
TX: 32.5
RX: 4.8
/@ 3.0 V
220 to 270
1 800 to 2 000
CR
30-pin
TSSOP
(225 mil)
PHS
µPC8158K
28/@ 3.0 V
100 to 300
800 to 1 500
28-pin QFN
PDC800 M/
1.5 G
µPC8126K
µPC8129GR
RF Up-Converter + IF
Quad. Mod + AGC
889 to 960
20-pin
SSOP (225 mil)
CT-2, etc.
Digital
Comm.
PDC800 MHz,
etc.
28-pin QFN
For outline of the quadrature modulator series, please refer to the application note ‘Usage of µPC8101, 8104,
8105, 8125, 8129’ (Document No. P13251E) and so on.
SYSTEM APPLICATION EXAMPLE
[PDC800 MHz/1.5 GHz]
SUB ANT
LNA
1st MIX
2nd MIX
SW
To DEMOD
MAIN ANT
RSSI
RSSI OUT
1st LO
PLL1
SW
2nd LO
PLL2
SW
LO2
LO1
AGC
I
0°
φ (CR)
PA
90°
Q
Filter
µ PC8158K
Preliminary Data Sheet P13831EJ1V1DS00
3
µPC8158K
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Power Save and AGC Control Pin
Applied Voltage
Symbol
Conditions
Rating
Unit
VCC
Pin11, 20 and 25,
TA = +25°C
5.0
V
VPS/VAGC
Pin17, TA = +25°C
5.0
V
430
mW
Note
TA = +85°C
Power Dissipation
PD
Operating Ambient Temperature
TA
–40 to +85
°C
Storage Temperature
Tstg
–55 to +150
°C
Note Mounted on double sided copper clad 50 × 50 × 1.6 mm epoxy glass PWB.
RECOMMENDED OPERATING CONDITIONS
Parameter
Test Conditions
MIN.
TYP.
MAX.
Unit
2.7
3.0
4.0
V
Supply Voltage
VCC
Pin11, 20 and 25
Power Save Voltage
VPS
Pin17
0
–
0.3
V
AGC Control Voltage
VAGCPS
Pin17
1.0
–
2.5
V
TA
–30
+25
+80
°C
Up-converter RF Output Frequency
fRFout
800
–
1500
MHz
LO2 Input Frequency
fLO2in
PLO2in = –15 dBm
600
–
1750
MHz
I/Q Input Frequency
fI/Qin
VI/Qin = 500 mVP-P MAX.
(Differential input)
DC
–
10
MHz
Operating Ambient Temperature
LO1 Input Level
PLO1in
–18
–15
–12
dBm
LO2 Input Level
PLO2in
–18
–15
–12
dBm
I/Q Input Amplitude
VI/Qin
–
420
500
mVP-P
100
–
300
MHz
Up-converter Input Frequency
fUPCONin
Modulator Output Frequency
fMODout
LO1 Input Frequency
4
Symbol
fLO1in
I, Ib, Q, Qb each
PLO1in = –15 dBm
Preliminary Data Sheet P13831EJ1V1DS00
µPC8158K
ELECTRICAL CHARACTERISTICS
Conditions (Unless otherwise specified):
TA = +25 °C, VCC1 = VCC2 = VCC3 = 3.0 V, VPS/VAGC = 2.5 V,
I/Q (DC) = Ib/Qb (DC) = VCC/2 = 1.5 V, VI/Ibin = VQ/Qbin = 500 mVP-P (each), fI/Qin = 2.625 kHz,
π/4DQPSK wave input, transmission rate 42 kbps, filter roll-off α = 0.5,
Modulation Pattern: <0000>
fLO1in = 178.05 MHz, PLO1in = –15 dBm
fLO2in = 1619.05 MHz, PLO2in = –15 dBm
fRFout = 1441 MHz – fI/Qin
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
23.7
28
37.6
mA
–
0.3
10
µA
UP-CONVERTER + QUADRATURE MODULATOR TOTAL
Total Circuit Current
Total Circuit Current at Power Save Mode
ICC (TOTAL)
ICC (PS) TOTAL
No input signal
VPS ≤ 0.5 V (Low),
No input signal
Total Output Power 1
PRFout1
VAGC = 2.5 V
–15
–11.5
–8
dBm
Total Output Power 2
PRFout2
VAGC = 1.0 V
–56.5
–52
–46.5
dBm
–
–40
–30
dBc
LO Carrier Leak
LOL
Image Rejection (Side Band Leak)
ImR
–
–40
–30
dBc
IM3 (I/Q)
–
–50
–30
dBc
I/Q 3rd order distortion
fLOL = fLO1 + fLO2
AGC Gain Control Range
GCR
VAGC = 2 V → 1 V
35
40
–
dB
Error Vector Magnitude
EVM
MOD Pattern: PN9
–
1.2
3.0
%rms
Padj
∆f = ±50 kHz,
MOD Pattern: PN9
–
–65
–60
dBc
fLO1 × 8, fLO1 × 8 (image)
–
–70
–65
dBc
Adjacent channel interference
Note
Spurious suppression
Pout (8fLO1)
Power Save Rise Time
TPS (Rise)
VPS (Low) → VPS (High)
–
2
5
µs
Power Save Fall Time
TPS (Fall)
VPS (High) → VPS (Low)
–
2
5
µs
I/Q input impedance
ZI/Q
Between pin I/Ib, Q/Qb
80
200
–
kΩ
I/Q input bias current
II/Q
Between pin I/Ib, Q/Qb
–
5
13
µA
fLO1 = 100 M to 300 MHz
–
1.5:1
–
–
LO1 input VSWR
ZLO1
Note Without external LC between Fil1 and Fil2 pin on this frequency conditions.
Spectrum analyzer conditions: VBW = 300 Hz, RBW = 300 Hz.
Remark Electrical characteristics in this document is described for 1.5 GHz system.
Preliminary Data Sheet P13831EJ1V1DS00
5
µPC8158K
PIN EXPLANATIONS
Supply
Voltage
(V)
Pin
Voltage
Iin
VCC/2
–
Input for I signal. This input
impedance is 200 kΩ. In the case of
that I/Q input signals are single
ended, amplitude of the signal is
500 m VP-P max.
Iinb
VCC/2
–
Input for I signal. This input
impedance is 200 kΩ. In the case of
that I/Q input signals are single
ended, VCC/2 biased DC signal
should be input. In the case of the
I/Q input signals are differential,
amplitude of the signal is 500 m VP-P
max.
Pin
No.
Symbol
1
2
3
N.C.
–
Function and Application
–
Qinb
VCC/2
–
Input for Q signal. This input
impedance is 200 kΩ. In the case of
that I/Q input signals are single
ended, amplitude of the signal is
500 m VP-P max.
5
Qin
VCC/2
–
Input for I signal. This input
impedance is 200 kΩ. In the case of
that I/Q input signals are single
ended, VCC/2 biased DC signal
should be input. In case of the I/Q
input signals are differential,
amplitude of the signal is 500 m VP-P
max.
N.C.
7
N.C.
8
N.C.
9
LO1inb
–
–
–
2.98
10
LO1in
–
2.98
11
VCC
2.7 to 4.0
–
2
–––––––––––––––––
4
5
These pins are not connected to
internal circuit. These pins should
be opened or grounded.
Bypass pin of modulator’s local
input. This pin should be decoupled
with 330 pF capacitor.
–––––––––––––––––
9
10
Local signal input for modulator.
This pin must be coupled with DC
cut capacitor 330 pF and should be
terminated with 51 Ω resistor.
Supply voltage pin for modulator,
up-converter and AGC circuits.
Note Pin Voltages are measured on VCC = 3.0 V.
6
1
This pin is not connected to internal
circuit. This pin should be opened
or grounded.
4
6
Internal Equivalent Circuit
Note
(V)
Preliminary Data Sheet P13831EJ1V1DS00
–––––––––––––––––
µPC8158K
Pin
No.
Symbol
12
GND
13
LO2in
Supply
Voltage
(V)
Pin
Voltage
0
–
–
1.8
14
LO2inb
–
1.8
15
N.C.
–
–
16
17
18
19
GND
VPS/VAGC
N.C.
GND
0
VPS/VAGC
–
0
Function and Application
Internal Equivalent Circuit
Ground pin for modulator, upconverter and AGC circuits. This pin
should be grounded with minimum
inductance. Form the ground
pattern as widely as possible to
minimize ground impedance.
–––––––––––––––––
Note
(V)
–
–
–
–
Local signal input for modulator.
This pin must be coupled with DC
cut capacitor 33 pF and should be
terminated with 51 Ω resistor.
13
14
Bypass pin of up-converter’s local
signal input. This pin should be
decoupled with 33 pF capacitor.
This pin is not connected to internal
circuit. This pin should be opened
or grounded.
–––––––––––––––––
Ground pin for modulator, upconverter and AGC circuits. This pin
should be grounded with minimum
inductance.
–––––––––––––––––
Power save control pin for
modulator, up-converter and AGC
circuits. This pin also assigned as
gain control pin for AGC circuits.
Operation status with applied
voltages are as follows.
VPS/VAGC (V)
STATE
0 to 0.4
OFF (Sleep Mode)
1 to 2.5
On (AGC Mode)
REG
17
AGC Cont
This pin is not connected to internal
circuit. This pin should be opened
or grounded.
–––––––––––––––––
Ground pin for modulator, upconverter and AGC circuits. This pin
should be grounded with minimum
inductance.
–––––––––––––––––
20
VCC
2.7 to 4.0
–
Supply voltage pin for modulator,
up-converter and AGC circuits.
–––––––––––––––––
21
GND
0
–
Ground pin for RF output buffer.
This pin should be grounded with
minimum inductance.
–––––––––––––––––
Note Pin Voltages are measured on VCC = 3.0 V.
Preliminary Data Sheet P13831EJ1V1DS00
7
µPC8158K
Pin
No.
Symbol
22
N.C.
23
24
RFout
N.C.
Supply
Voltage
(V)
Pin
Voltage
–
–
–
–
1.75
–
25
VCC
2.7 to 4.0
–
26
Fil1
–
2.76
27
Fil2
–
2.76
28
GND
0
Function and Application
Internal Equivalent Circuit
This pin is not connected to internal
circuit. This pin should be opened
or grounded.
–––––––––––––––––
Note
(V)
–
RF output pin. This pin is emitter
follower which is low impedance
output port. This pin can be easily
matched to 50 Ω impedance using
external coupling and decoupling
capacitors.
23
These pins are not connected to
internal circuit. These pins should
be opened or grounded.
–––––––––––––––––
Supply voltage pin for RF output
buffer.
–––––––––––––––––
External inductor and capacitor can
supress harmonics spurious of LO1
frequency.
LC value should be determined
according to LO1 input frequency
and suppression level.
Ground pin for modulator, upconverter and AGC circuits. This pin
should be grounded with minimum
inductance. Form the ground
pattern as widely as possible to
minimize ground impedance.
Note Pin Voltages are measured on VCC = 3.0 V.
8
External
Preliminary Data Sheet P13831EJ1V1DS00
External
26
27
–––––––––––––––––
µPC8158K
Voltage Source or
Pulse Pattern Generator
100 pF
0.22 µF
Voltage
Source
1 000 pF
TEST CIRCUIT
Vector Signal
Analyzer or Spectrum
Analyzer
GND
LO2b 14 33 pF
LO2in 13 33 pF
GND 12
24
25
26
27
REG
REG
I/Q Mixer
Phase
Shifter
Fil1
Fil2
GND
I
Ib
28
AGC
LPF
VCC
1
100 pF
2
3
4
100 pF
5
6
7
51 Ω
51 Ω BPF
0.22 µ F
VPS/VAGC
GND
UP-CON AGCcont
RFout
1 000 pF
23
100 pF
2 pF
Signal Generator
Qb
Q
100 pF
1 000 pF
Voltage
Source
0.22 µ F
GND
VCC
22 21 20 19 18 17 16 15
Voltage
Source
VCC 11
BPF
LO1in 10 330 pF
LO1b 9
51 Ω
Signal Generator
or Network
330 pF
Analyzer
8
100 pF
100 pF
I/Q Signal
Generator
TEST CONDITIONS
fLO1in = 178.05 MHz, PLO1in = –15 dBm
fLO2in = 1619.05 MHz, PLO2in = –15 dBm
fRFout = 1441 MHz – fI/Qin
Preliminary Data Sheet P13831EJ1V1DS00
9
µPC8158K
PACKAGE DIMENSIONS
0.22
0.5
0.125
0.95 ± 0.1
Pin 28
Pin 1
0.22
(4.7)
(5.1 ± 0.1)
5.1 ± 0.1
2 × 0.5 = 1
1.2
2 × 0.5 = 1
4 – 0.5
0.5
4 – 0.5
28 pin plastic QFN (UNIT: mm)
0.5
7 × 0.5 = 3.5
(5.1)
0.5
(4.1)
(5.5 ± 0.1)
(0.22)
0.3
0.5
5.5 ± 0.1
(0.22)
0.5
(4.5)
Bottom View
10
Preliminary Data Sheet P13831EJ1V1DS00
0.5
µPC8158K
RECOMMENDED SOLDERING CONDITIONS
This product should be soldered under the following recommended conditions.
For soldering methods and
conditions other than those recommended below, contact your NEC sales representative.
µPC8158K
Soldering Method
Soldering Conditions
Recommended Condition
Symbol
Infrared Reflow
Package peak temperature: 235°C or below
Time: 30 seconds or less (at 210°C)
Note
Count: 2, Exposure limit : None
IR35-00-2
Partial Heating
Pin temperature: 300°C
Time: 3 seconds or less (per side of device)
Note
Exposure limit : None
–
Note After opening the dry pack, keep it in a place below 25°C and 65% RH for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
For details of recommended soldering conditions for surface mounting, refer to information document
SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL (C10535E).
Preliminary Data Sheet P13831EJ1V1DS00
11
µPC8158K
NESAT (NEC Silicon Advanced Technology) is a trademark of NEC Corporation.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96. 5