Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B VREF Pin Name/Function VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 REFCLK1Ln REFCLK1Lp GXB_TX_L4n GXB_TX_L4p GXB_RX_L4p,GXB_REFCLK_L4p GXB_RX_L4n,GXB_REFCLK_L4n GXB_TX_L3n GXB_TX_L3p GXB_RX_L3p,GXB_REFCLK_L3p GXB_RX_L3n,GXB_REFCLK_L3n GXB_TX_L2n GXB_TX_L2p GXB_RX_L2p,GXB_REFCLK_L2p GXB_RX_L2n,GXB_REFCLK_L2n GXB_TX_L1n GXB_TX_L1p GXB_RX_L1p,GXB_REFCLK_L1p GXB_RX_L1n,GXB_REFCLK_L1n GXB_TX_L0n GXB_TX_L0p GXB_RX_L0p,GXB_REFCLK_L0p GXB_RX_L0n,GXB_REFCLK_L0n REFCLK0Lp REFCLK0Ln TDO nCSO TMS AS_DATA3 TCK AS_DATA2 TDI AS_DATA1 DCLK AS_DATA0,ASDO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Optional Function(s) Configuration Function TDO DATA4 TMS DATA3 TCK DATA2 TDI DATA1 DCLK DATA0 DATA6 DATA5 DATA8 DATA7 DATA10 DATA9 DATA12 DATA11 DATA14 DATA13 CLKUSR DATA15 PR_DONE PR_READY PR_ERROR CLK0n,FPLL_BL_FBn CLK0p,FPLL_BL_FBp Dedicated Tx/Rx Channel DIFFIO_RX_B1n DIFFIO_TX_B2n DIFFIO_RX_B1p DIFFIO_TX_B2p DIFFIO_RX_B3n DIFFIO_TX_B4n DIFFIO_RX_B3p DIFFIO_TX_B4p DIFFIO_RX_B5n DIFFIO_TX_B6n DIFFIO_RX_B5p DIFFIO_TX_B6p DIFFIO_RX_B7n DIFFIO_TX_B8n DIFFIO_RX_B7p DIFFIO_TX_B8p DIFFIO_TX_B33n DIFFIO_RX_B34n DIFFIO_TX_B33p DIFFIO_RX_B34p DIFFIO_RX_B35n DIFFIO_TX_B36n DIFFIO_RX_B35p DIFFIO_TX_B36p DIFFIO_TX_B37n DIFFIO_RX_B38n DIFFIO_TX_B37p DIFFIO_RX_B38p DIFFIO_RX_B39n DIFFIO_TX_B40n DIFFIO_RX_B39p DIFFIO_TX_B40p DIFFIO_TX_B41n DIFFIO_RX_B42n DIFFIO_TX_B41p DIFFIO_RX_B42p DIFFIO_RX_B43n Pin List AU19 Emulated LVDS Output Channel U484 DIFFOUT_B1n DIFFOUT_B2n DIFFOUT_B1p DIFFOUT_B2p DIFFOUT_B3n DIFFOUT_B4n DIFFOUT_B3p DIFFOUT_B4p DIFFOUT_B5n DIFFOUT_B6n DIFFOUT_B5p DIFFOUT_B6p DIFFOUT_B7n DIFFOUT_B8n DIFFOUT_B7p DIFFOUT_B8p DIFFOUT_B33n DIFFOUT_B34n DIFFOUT_B33p DIFFOUT_B34p DIFFOUT_B35n DIFFOUT_B36n DIFFOUT_B35p DIFFOUT_B36p DIFFOUT_B37n DIFFOUT_B38n DIFFOUT_B37p DIFFOUT_B38p DIFFOUT_B39n DIFFOUT_B40n DIFFOUT_B39p DIFFOUT_B40p DIFFOUT_B41n DIFFOUT_B42n DIFFOUT_B41p DIFFOUT_B42p DIFFOUT_B43n G4 F5 E1 E2 G2 G1 J1 J2 L2 L1 N1 N2 R2 R1 U1 U2 W2 W1 Y3 Y4 AA2 AA1 V4 U4 V3 AB6 R4 AA5 V5 T5 P5 W5 M5 AB4 P6 U7 N6 U6 M6 R5 M7 R6 R7 L7 T7 L8 T8 P7 T9 P8 V8 N8 W8 M8 N9 AA7 N10 AB7 Y7 U8 W7 V9 R9 AB8 P9 AA8 Y10 AA9 AA10 Y9 L9 DQS for X8 DQS for X16 HMC Pin Assignment for DDR3/DDR2 (2) HMC Pin Assignment for LPDDR2 GND DQ5B DQ5B DQ5B DQ5B GND B_A_15 B_WE# B_A_14 B_CS#_1 B_A_13 B_CS#_0 B_A_12 B_A_11 B_A_9 B_A_10 B_A_8 DQ5B B_RAS# DQ5B B_CAS# GND B_BA_2 B_BA_0 B_BA_1 B_CK# DQ1B DQ1B DQ1B DQSn1B DQ1B DQS1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ5B DQ5B DQ5B DQSn5B DQ5B DQS5B DQ6B DQ6B DQ6B DQSn6B B_CS#_1 B_CS#_0 B_CA_9 B_CA_8 GND B_CK# Page 1 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Optional Function(s) Configuration Function FPLL_BL_CLKOUT1,FPLL_BL_CLKOUTn FPLL_BL_CLKOUT0,FPLL_BL_CLKOUTp,FPLL_BL_FB CLK1n CLK1p RZQ_0 CLK2n CLK2p CLK3n CLK3p RZQ_1 INIT_DONE PR_REQUEST CRC_ERROR nCEO CvP_CONFDONE DEV_OE DEV_CLRn nPERSTL1 Dedicated Tx/Rx Channel Emulated LVDS Output Channel U484 DQS for X8 DIFFIO_TX_B44n DIFFIO_RX_B43p DIFFIO_TX_B44p DIFFIO_TX_B45n DIFFIO_RX_B46n DIFFIO_TX_B45p DIFFIO_RX_B46p DIFFIO_RX_B47n DIFFIO_TX_B48n DIFFIO_RX_B47p DIFFIO_TX_B48p DIFFIO_TX_B49n DIFFIO_RX_B50n DIFFIO_TX_B49p DIFFIO_RX_B50p DIFFIO_RX_B51n DIFFIO_TX_B52n DIFFIO_RX_B51p DIFFIO_TX_B52p DIFFIO_TX_B53n DIFFIO_RX_B54n DIFFIO_TX_B53p DIFFIO_RX_B54p DIFFIO_RX_B55n DIFFIO_TX_B56n DIFFIO_RX_B55p DIFFIO_TX_B56p DIFFIO_TX_B57n DIFFIO_RX_B58n DIFFIO_TX_B57p DIFFIO_RX_B58p DIFFIO_RX_B59n DIFFIO_TX_B60n DIFFIO_RX_B59p DIFFIO_TX_B60p DIFFIO_TX_B61n DIFFIO_RX_B62n DIFFIO_TX_B61p DIFFIO_RX_B62p DIFFIO_RX_B63n DIFFIO_TX_B64n DIFFIO_RX_B63p DIFFIO_TX_B64p DIFFIO_TX_B65n DIFFIO_RX_B66n DIFFIO_TX_B65p DIFFIO_RX_B66p DIFFIO_RX_B67n DIFFIO_TX_B68n DIFFIO_RX_B67p DIFFIO_TX_B68p DIFFIO_TX_B69n DIFFIO_RX_B70n DIFFIO_TX_B69p DIFFIO_RX_B70p DIFFIO_RX_B71n DIFFIO_TX_B72n DIFFIO_RX_B71p DIFFIO_TX_B72p DIFFIO_TX_R1p DIFFIO_RX_R2p DIFFIO_TX_R1n DIFFIO_RX_R2n DIFFIO_TX_R3p DIFFIO_RX_R4p DIFFIO_TX_R3n DIFFIO_RX_R4n DIFFIO_TX_R5p DIFFIO_RX_R6p DIFFIO_TX_R5n DIFFIO_RX_R6n DIFFOUT_B44n DIFFOUT_B43p DIFFOUT_B44p DIFFOUT_B45n DIFFOUT_B46n DIFFOUT_B45p DIFFOUT_B46p DIFFOUT_B47n DIFFOUT_B48n DIFFOUT_B47p DIFFOUT_B48p DIFFOUT_B49n DIFFOUT_B50n DIFFOUT_B49p DIFFOUT_B50p DIFFOUT_B51n DIFFOUT_B52n DIFFOUT_B51p DIFFOUT_B52p DIFFOUT_B53n DIFFOUT_B54n DIFFOUT_B53p DIFFOUT_B54p DIFFOUT_B55n DIFFOUT_B56n DIFFOUT_B55p DIFFOUT_B56p DIFFOUT_B57n DIFFOUT_B58n DIFFOUT_B57p DIFFOUT_B58p DIFFOUT_B59n DIFFOUT_B60n DIFFOUT_B59p DIFFOUT_B60p DIFFOUT_B61n DIFFOUT_B62n DIFFOUT_B61p DIFFOUT_B62p DIFFOUT_B63n DIFFOUT_B64n DIFFOUT_B63p DIFFOUT_B64p DIFFOUT_B65n DIFFOUT_B66n DIFFOUT_B65p DIFFOUT_B66p DIFFOUT_B67n DIFFOUT_B68n DIFFOUT_B67p DIFFOUT_B68p DIFFOUT_B69n DIFFOUT_B70n DIFFOUT_B69p DIFFOUT_B70p DIFFOUT_B71n DIFFOUT_B72n DIFFOUT_B71p DIFFOUT_B72p DIFFOUT_R1p DIFFOUT_R2p DIFFOUT_R1n DIFFOUT_R2n DIFFOUT_R3p DIFFOUT_R4p DIFFOUT_R3n DIFFOUT_R4n DIFFOUT_R5p DIFFOUT_R6p DIFFOUT_R5n DIFFOUT_R6n W11 M10 Y11 AB10 U10 AB11 U11 T10 R11 R10 P12 AA13 W12 AB13 Y12 U12 R12 T12 T13 AB15 W13 AB16 V13 T14 AB18 U13 AA18 AA19 Y14 Y19 W14 P14 AA20 R14 Y20 AA15 U15 Y15 V15 R15 AB20 T15 AB21 AB22 Y16 AA22 Y17 U16 AA17 U17 AB17 Y22 V18 Y21 W18 W16 W21 W17 W22 U22 V20 U21 V19 T19 T17 T20 T18 T22 R16 R22 R17 DQ6B DQS6B Pin List AU19 DQS for X16 DQ6B DQ6B DQ6B DQ6B HMC Pin Assignment for DDR3/DDR2 (2) B_A_7 B_CK B_A_6 B_A_3 B_A_5 B_A_2 B_A_4 HMC Pin Assignment for LPDDR2 B_CA_7 B_CK B_CA_6 B_CA_3 B_CA_5 B_CA_2 B_CA_4 DQ6B B_A_1 B_CA_1 DQ6B B_A_0 B_CA_0 DQ7B DQ7B DQ7B DQSn7B DQ7B DQS7B DQ7B DQ7B DQ7B DQ7B B_DQ_0 B_DQ_2 B_DQ_1 B_DQS#_0 B_DQ_3 B_DQS_0 B_ODT_0 B_ODT_1 B_DQ_4 B_DQ_6 B_DQ_5 B_DQ_0 B_DQ_2 B_DQ_1 B_DQS#_0 B_DQ_3 B_DQS_0 B_ODT_0 B_ODT_1 B_DQ_4 B_DQ_6 B_DQ_5 DQ7B B_DQ_7 B_DQ_7 B_DM_0 GND B_DQ_8 B_DQ_10 B_DQ_9 B_DQS#_1 B_DQ_11 B_DQS_1 B_CKE_1 B_CKE_0 B_DQ_12 B_DQ_14 B_DQ_13 DQ7B DQ8B DQ8B DQ8B DQSn8B DQ8B DQS8B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ8B DQ8B DQ8B DQ8B DQ1B DQ1B DQ1B DQ1B B_DM_0 GND B_DQ_8 B_DQ_10 B_DQ_9 B_DQS#_1 B_DQ_11 B_DQS_1 B_CKE_1 B_CKE_0 B_DQ_12 B_DQ_14 B_DQ_13 DQ8B DQ1B B_DQ_15 B_DQ_15 DQ8B DQ1B DQ9B DQ9B DQ9B DQSn9B DQ9B DQS9B DQ1B DQ1B DQ1B DQSn1B DQ1B DQS1B DQ9B DQ9B DQ9B DQ9B DQ1B DQ1B DQ1B DQ1B DQ9B DQ1B DQ9B DQ1R DQ1B B_DM_1 GND B_DQ_16 B_DQ_18 B_DQ_17 B_DQS#_2 B_DQ_19 B_DQS_2 B_RESET# GND B_DQ_20 B_DQ_22 B_DQ_21 GND B_DQ_23 GND B_DM_2 B_DM_1 GND B_DQ_16 B_DQ_18 B_DQ_17 B_DQS#_2 B_DQ_19 B_DQS_2 B_RESET# GND B_DQ_20 B_DQ_22 B_DQ_21 GND B_DQ_23 GND B_DM_2 DQ1R DQ1R DQ1R DQ1R DQ1R DQS1R DQ1R DQSn1R Page 2 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function 5A 5A 5A 5A 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO GND IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Optional Function(s) CLK7p,FPLL_BR_FBp CLK7n,FPLL_BR_FBn CLK6p CLK6n FPLL_BR_CLKOUT0,FPLL_BR_CLKOUTp,FPLL_BR_FB FPLL_BR_CLKOUT1,FPLL_BR_CLKOUTn CLK11p Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel U484 DQS for X8 DIFFIO_TX_R7p DIFFIO_RX_R8p DIFFIO_TX_R7n DIFFIO_RX_R8n DIFFIO_RX_R25p DIFFIO_TX_R26p DIFFIO_RX_R25n DIFFIO_TX_R26n DIFFIO_RX_R27p DIFFIO_TX_R28p DIFFIO_RX_R27n DIFFIO_TX_R28n DIFFIO_RX_R29p DIFFIO_TX_R30p DIFFIO_RX_R29n DIFFIO_TX_R30n DIFFIO_RX_R31p DIFFIO_TX_R32p DIFFIO_RX_R31n DIFFIO_TX_R32n DIFFIO_RX_R33p DIFFIO_TX_R34p DIFFIO_RX_R33n DIFFIO_TX_R34n DIFFIO_RX_R35p DIFFIO_TX_R36p DIFFIO_RX_R35n DIFFIO_TX_R36n DIFFIO_RX_R37p DIFFIO_TX_R38p DIFFIO_RX_R37n DIFFIO_TX_R38n DIFFIO_RX_R39p DIFFIO_TX_R40p DIFFIO_RX_R39n DIFFIO_TX_R40n DIFFIO_RX_R41p DIFFIO_TX_R42p DIFFIO_RX_R41n DIFFIO_TX_R42n DIFFIO_RX_R43p DIFFIO_TX_R44p DIFFIO_RX_R43n DIFFIO_TX_R44n DIFFIO_RX_R45p DIFFIO_TX_R46p DIFFIO_RX_R45n DIFFIO_TX_R46n DIFFIO_RX_R47p DIFFIO_TX_R48p DIFFIO_RX_R47n DIFFIO_TX_R48n DIFFOUT_R7p DIFFOUT_R8p DIFFOUT_R7n DIFFOUT_R8n DIFFOUT_R25p DIFFOUT_R26p DIFFOUT_R25n DIFFOUT_R26n DIFFOUT_R27p DIFFOUT_R28p DIFFOUT_R27n DIFFOUT_R28n DIFFOUT_R29p DIFFOUT_R30p DIFFOUT_R29n DIFFOUT_R30n DIFFOUT_R31p DIFFOUT_R32p DIFFOUT_R31n DIFFOUT_R32n DIFFOUT_R33p DIFFOUT_R34p DIFFOUT_R33n DIFFOUT_R34n DIFFOUT_R35p DIFFOUT_R36p DIFFOUT_R35n DIFFOUT_R36n DIFFOUT_R37p DIFFOUT_R38p DIFFOUT_R37n DIFFOUT_R38n DIFFOUT_R39p DIFFOUT_R40p DIFFOUT_R39n DIFFOUT_R40n DIFFOUT_R41p DIFFOUT_R42p DIFFOUT_R41n DIFFOUT_R42n DIFFOUT_R43p DIFFOUT_R44p DIFFOUT_R43n DIFFOUT_R44n DIFFOUT_R45p DIFFOUT_R46p DIFFOUT_R45n DIFFOUT_R46n DIFFOUT_R47p DIFFOUT_R48p DIFFOUT_R47n DIFFOUT_R48n DQ1R DQ1R DIFFIO_RX_T25p DIFFIO_TX_T26p DIFFIO_RX_T25n DIFFIO_TX_T26n DIFFIO_RX_T27p DIFFIO_TX_T28p DIFFIO_RX_T27n DIFFIO_TX_T28n DIFFIO_RX_T29p DIFFIO_TX_T30p DIFFIO_RX_T29n DIFFIO_TX_T30n DIFFIO_RX_T31p DIFFIO_TX_T32p DIFFIO_RX_T31n DIFFIO_TX_T32n DIFFIO_RX_T33p DIFFIO_TX_T34p DIFFOUT_T25p DIFFOUT_T26p DIFFOUT_T25n DIFFOUT_T26n DIFFOUT_T27p DIFFOUT_T28p DIFFOUT_T27n DIFFOUT_T28n DIFFOUT_T29p DIFFOUT_T30p DIFFOUT_T29n DIFFOUT_T30n DIFFOUT_T31p DIFFOUT_T32p DIFFOUT_T31n DIFFOUT_T32n DIFFOUT_T33p DIFFOUT_T34p R20 R19 R21 P19 P16 P21 N16 P22 N20 M22 N21 L22 P18 K22 N18 J22 M21 F22 M20 E22 M16 E21 M17 D22 L19 K21 L20 J21 L15 G22 K15 G21 L18 G20 K19 H21 L17 E20 K17 F20 H20 G18 H19 G17 K16 F19 J16 F18 J17 J19 J18 H18 F17 H16 C21 G16 C20 D18 B20 E17 B21 G15 B22 G14 A22 E16 A20 D17 A19 G13 C19 Pin List AU19 DQS for X16 HMC Pin Assignment for DDR3/DDR2 (2) HMC Pin Assignment for LPDDR2 GND T_DM_2 GND T_DQ_23 T_DQ_21 T_DQ_22 T_DQ_20 GND T_DQS_2 T_RESET# T_DQS#_2 T_DQ_19 T_DQ_17 T_DQ_18 T_DQ_16 GND GND T_DM_2 GND T_DQ_23 T_DQ_21 T_DQ_22 T_DQ_20 GND T_DQS_2 T_RESET# T_DQS#_2 T_DQ_19 T_DQ_17 T_DQ_18 T_DQ_16 GND T_DM_1 T_DM_1 DQ1R DQ4R DQ4R DQ4R DQ4R DQ4R DQ4R DQS4R DQSn4R DQ4R DQ4R DQ4R DQ4R DQ5R DQ5R DQ5R DQ5R DQ5R DQ5R DQS5R DQSn5R DQ5R DQ5R DQ5R DQ5R DQ6R DQ6R DQ6R DQ6R DQ6R DQ6R DQS6R DQSn6R DQ6R DQ6R DQ6R DQ6R DQ4T DQ1T DQ4T DQ4T DQ4T DQ4T DQ4T DQS4T DQ1T DQ1T DQ1T DQ1T DQ1T DQS1T DQSn4T DQ4T DQ4T DQ4T DQ4T DQSn1T DQ1T DQ1T DQ1T DQ1T DQ5T DQ1T Page 3 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function Optional Function(s) 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 9A 9A 9A 9A 9A 9A 9A 9A 9A VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO MSEL0 CONF_DONE MSEL1 nSTATUS nCE MSEL2 MSEL3 nCONFIG MSEL4 CLK11n PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Configuration Function CLK10p CLK10n RZQ_2 CLK9p CLK9n FPLL_TL_CLKOUT0,FPLL_TL_CLKOUTp,FPLL_TL_FB FPLL_TL_CLKOUT1,FPLL_TL_CLKOUTn CLK8p,FPLL_TL_FBp CLK8n,FPLL_TL_FBn Dedicated Tx/Rx Channel Emulated LVDS Output Channel U484 DIFFIO_RX_T33n DIFFIO_TX_T34n DIFFIO_RX_T35p DIFFIO_TX_T36p DIFFIO_RX_T35n DIFFIO_TX_T36n DIFFIO_RX_T37p DIFFIO_TX_T38p DIFFIO_RX_T37n DIFFIO_TX_T38n DIFFIO_RX_T39p DIFFIO_TX_T40p DIFFIO_RX_T39n DIFFIO_TX_T40n DIFFIO_RX_T41p DIFFIO_TX_T42p DIFFIO_RX_T41n DIFFIO_TX_T42n DIFFIO_RX_T43p DIFFIO_TX_T44p DIFFIO_RX_T43n DIFFIO_TX_T44n DIFFIO_RX_T45p DIFFIO_TX_T46p DIFFIO_RX_T45n DIFFIO_TX_T46n DIFFIO_RX_T47p DIFFIO_TX_T48p DIFFIO_RX_T47n DIFFIO_TX_T48n DIFFIO_RX_T49p DIFFIO_TX_T50p DIFFIO_RX_T49n DIFFIO_TX_T50n DIFFIO_RX_T51p DIFFIO_TX_T52p DIFFIO_RX_T51n DIFFIO_TX_T52n DIFFIO_RX_T53p DIFFIO_TX_T54p DIFFIO_RX_T53n DIFFIO_TX_T54n DIFFIO_RX_T55p DIFFIO_TX_T56p DIFFIO_RX_T55n DIFFIO_TX_T56n DIFFIO_RX_T57p DIFFIO_TX_T58p DIFFIO_RX_T57n DIFFIO_TX_T58n DIFFIO_RX_T59p DIFFIO_TX_T60p DIFFIO_RX_T59n DIFFIO_TX_T60n DIFFIO_RX_T61p DIFFIO_TX_T62p DIFFIO_RX_T61n DIFFIO_TX_T62n DIFFIO_RX_T63p DIFFIO_TX_T64p DIFFIO_RX_T63n DIFFIO_TX_T64n DIFFOUT_T33n DIFFOUT_T34n DIFFOUT_T35p DIFFOUT_T36p DIFFOUT_T35n DIFFOUT_T36n DIFFOUT_T37p DIFFOUT_T38p DIFFOUT_T37n DIFFOUT_T38n DIFFOUT_T39p DIFFOUT_T40p DIFFOUT_T39n DIFFOUT_T40n DIFFOUT_T41p DIFFOUT_T42p DIFFOUT_T41n DIFFOUT_T42n DIFFOUT_T43p DIFFOUT_T44p DIFFOUT_T43n DIFFOUT_T44n DIFFOUT_T45p DIFFOUT_T46p DIFFOUT_T45n DIFFOUT_T46n DIFFOUT_T47p DIFFOUT_T48p DIFFOUT_T47n DIFFOUT_T48n DIFFOUT_T49p DIFFOUT_T50p DIFFOUT_T49n DIFFOUT_T50n DIFFOUT_T51p DIFFOUT_T52p DIFFOUT_T51n DIFFOUT_T52n DIFFOUT_T53p DIFFOUT_T54p DIFFOUT_T53n DIFFOUT_T54n DIFFOUT_T55p DIFFOUT_T56p DIFFOUT_T55n DIFFOUT_T56n DIFFOUT_T57p DIFFOUT_T58p DIFFOUT_T57n DIFFOUT_T58n DIFFOUT_T59p DIFFOUT_T60p DIFFOUT_T59n DIFFOUT_T60n DIFFOUT_T61p DIFFOUT_T62p DIFFOUT_T61n DIFFOUT_T62n DIFFOUT_T63p DIFFOUT_T64p DIFFOUT_T63n DIFFOUT_T64n F14 C18 C16 B16 C15 B15 G12 A18 H12 A17 F15 B18 E14 B17 H10 A15 G11 A14 D13 C14 C13 D14 H9 A13 G8 B13 E12 B12 F12 A12 G10 C11 F10 B11 D11 A8 E11 A7 J9 F8 J8 E7 C10 C6 C9 D7 K7 A10 J7 A9 D9 B6 D8 B5 H8 C8 G7 B8 H6 E6 G6 F7 L6 J6 K6 G5 H5 A2 E5 A4 C5 MSEL0 CONF_DONE MSEL1 nSTATUS nCE MSEL2 MSEL3 nCONFIG MSEL4 Pin List AU19 DQS for X8 DQS for X16 HMC Pin Assignment for DDR3/DDR2 (2) HMC Pin Assignment for LPDDR2 DQ5T DQ5T DQ5T DQ5T DQ5T DQS5T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQSn5T DQ5T DQ5T DQ5T DQ5T DQ1T DQ1T DQ1T DQ1T DQ1T T_DQ_15 T_DQ_13 T_DQ_14 T_DQ_12 T_CKE_0 T_DQS_1 T_CKE_1 T_DQS#_1 T_DQ_11 T_DQ_9 T_DQ_10 T_DQ_8 GND T_DQ_15 T_DQ_13 T_DQ_14 T_DQ_12 T_CKE_0 T_DQS_1 T_CKE_1 T_DQS#_1 T_DQ_11 T_DQ_9 T_DQ_10 T_DQ_8 GND DQ6T T_DM_0 T_DM_0 DQ6T DQ6T DQ6T DQ6T DQ6T DQS6T T_DQ_7 T_DQ_5 T_DQ_6 T_DQ_4 T_ODT_1 T_DQS_0 T_ODT_0 T_DQS#_0 T_DQ_3 T_DQ_1 T_DQ_2 T_DQ_0 T_DQ_7 T_DQ_5 T_DQ_6 T_DQ_4 T_ODT_1 T_DQS_0 T_ODT_0 T_DQS#_0 T_DQ_3 T_DQ_1 T_DQ_2 T_DQ_0 DQSn6T DQ6T DQ6T DQ6T DQ6T DQ7T T_A_0 T_CA_0 DQ7T DQ7T DQ7T DQ7T DQ7T DQS7T T_A_1 T_A_4 T_A_2 T_A_5 T_A_3 T_CK T_A_6 T_CK# T_A_7 T_BA_1 T_BA_0 T_BA_2 GND T_CA_1 T_CA_4 T_CA_2 T_CA_5 T_CA_3 T_CK T_CA_6 T_CK# T_CA_7 DQSn7T DQ7T DQ7T DQ7T DQ7T DQ8T T_CAS# DQ8T DQ8T DQ8T DQ8T DQ8T DQS8T T_RAS# T_A_8 T_A_10 T_A_9 T_A_11 T_CS#_0 T_A_12 T_CS#_1 T_A_13 T_A_14 T_WE# T_A_15 GND DQSn8T DQ8T DQ8T DQ8T DQ8T GND T_CA_8 T_CA_9 T_CS#_0 T_CS#_1 GND Page 4 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Emulated LVDS Output Channel U484 DQS for X8 DQS for X16 HMC Pin Assignment for DDR3/DDR2 (2) HMC Pin Assignment for LPDDR2 F3 M9 V22 L3 N11 W20 F11 C3 Y8 K14 D1 K8 V2 C7 A5 B2 M14 M4 G9 D2 L5 J5 K1 F1 C22 AB1 L16 C4 H2 H1 J13 AB2 E4 AB19 D5 J20 V17 A11 U5 G3 H14 T11 M2 J15 D10 J3 L13 F6 H4 U9 N7 U19 N15 K12 AA11 K2 E3 P10 A21 F2 M1 P1 K10 Y5 D20 B14 Y2 T2 K4 P4 C17 Pin List AU19 Page 5 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC DNU DNU DNU DNU DNU DNU VCCPGM VCCPGM VCCPGM VCCBAT VCCIO3A VCCIO3A VCCIO3B VCCIO3B VCCIO3B VCCIO3B VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO5A VCCIO5A PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Emulated LVDS Output Channel U484 DQS for X8 DQS for X16 HMC Pin Assignment for DDR3/DDR2 (2) HMC Pin Assignment for LPDDR2 M12 N22 Y1 N13 W4 AA3 B1 U14 R3 AA16 T1 AA4 H3 V1 F21 N5 M19 U3 J11 Y13 E13 P2 N3 R13 L11 W3 F16 M13 K13 J10 M11 P13 H15 M15 N14 L12 J12 H13 L10 K9 P11 P15 N12 H11 J14 L14 K11 B3 B4 AB3 V11 D21 E10 Y6 U20 B7 A3 AA6 T6 R8 AB9 W10 V7 Y18 W15 T16 V12 AB14 AA21 T21 R18 Pin List AU19 Page 6 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number 3A 3B 4A 5A 5B 7A 8A VREF VREFB3AN0 VREFB3BN0 VREFB4AN0 VREFB5AN0 VREFB5BN0 VREFB7AN0 VREFB8AN0 Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel VCCIO5B VCCIO5B VCCIO5B VCCIO5B VCCIO5B VCCIO5B VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCPD3A VCCPD3B4A VCCPD3B4A VCCPD3B4A VCCPD3B4A VCCPD5A VCCPD5B VCCPD5B VCCPD7A8A VCCPD7A8A VCCPD7A8A VCCPD7A8A VREFB3AN0 VREFB3BN0 VREFB4AN0 VREFB5AN0 VREFB5BN0 VREFB7AN0 VREFB8AN0 NC NC NC NC VCCH_GXBL VCCH_GXBL VCCL_GXBL VCCL_GXBL RREF_TL VCCA_FPLL VCCA_FPLL VCCA_FPLL VCCA_FPLL VCC_AUX VCC_AUX VCC_AUX VCC_AUX VCC_AUX VCC_AUX VCCE_GXBL VCCE_GXBL VCCE_GXBL VCCE_GXBL Emulated LVDS Output Channel U484 DQS for X8 DQS for X16 HMC Pin Assignment for DDR3/DDR2 (2) HMC Pin Assignment for LPDDR2 G19 N17 P20 K18 L21 H22 H17 C12 D15 B19 A16 E18 E8 A6 H7 B9 V6 V14 V10 W9 V16 P17 N19 M18 E9 F13 F9 E15 W6 AB12 AA14 V21 K20 D16 B10 C2 C1 D4 D3 T3 M3 P3 K3 A1 T4 F4 U18 E19 D19 AA12 W19 D6 D12 AB5 N4 L4 J4 K5 Notes: (1) For more information about pin definition and pin connection guidelines, refer to the Cyclone V Device Family Pin Connection Guidelines. (2) RESET pin is only applicable for DDR3 device. PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Pin List AU19 Page 7 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B VREF Pin Name/Function VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 REFCLK1Ln REFCLK1Lp GXB_TX_L5n GXB_TX_L5p GXB_RX_L5p,GXB_REFCLK_L5p GXB_RX_L5n,GXB_REFCLK_L5n GXB_TX_L4n GXB_TX_L4p GXB_RX_L4p,GXB_REFCLK_L4p GXB_RX_L4n,GXB_REFCLK_L4n GXB_TX_L3n GXB_TX_L3p GXB_RX_L3p,GXB_REFCLK_L3p GXB_RX_L3n,GXB_REFCLK_L3n GXB_TX_L2n GXB_TX_L2p GXB_RX_L2p,GXB_REFCLK_L2p GXB_RX_L2n,GXB_REFCLK_L2n GXB_TX_L1n GXB_TX_L1p GXB_RX_L1p,GXB_REFCLK_L1p GXB_RX_L1n,GXB_REFCLK_L1n GXB_TX_L0n GXB_TX_L0p GXB_RX_L0p,GXB_REFCLK_L0p GXB_RX_L0n,GXB_REFCLK_L0n REFCLK0Lp REFCLK0Ln TDO nCSO TMS AS_DATA3 TCK AS_DATA2 TDI AS_DATA1 DCLK AS_DATA0,ASDO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Optional Function(s) Configuration Function TDO DATA4 TMS DATA3 TCK DATA2 TDI DATA1 DCLK DATA0 DATA6 DATA5 DATA8 DATA7 DATA10 DATA9 DATA12 DATA11 DATA14 DATA13 CLKUSR DATA15 PR_DONE PR_READY PR_ERROR CLK0n,FPLL_BL_FBn CLK0p,FPLL_BL_FBp Dedicated Tx/Rx Channel DIFFIO_RX_B1n DIFFIO_TX_B2n DIFFIO_RX_B1p DIFFIO_TX_B2p DIFFIO_RX_B3n DIFFIO_TX_B4n DIFFIO_RX_B3p DIFFIO_TX_B4p DIFFIO_RX_B5n DIFFIO_TX_B6n DIFFIO_RX_B5p DIFFIO_TX_B6p DIFFIO_RX_B7n DIFFIO_TX_B8n DIFFIO_RX_B7p DIFFIO_TX_B8p DIFFIO_TX_B33n DIFFIO_RX_B34n DIFFIO_TX_B33p DIFFIO_RX_B34p DIFFIO_RX_B35n DIFFIO_TX_B36n DIFFIO_RX_B35p DIFFIO_TX_B36p DIFFIO_TX_B37n DIFFIO_RX_B38n DIFFIO_TX_B37p DIFFIO_RX_B38p DIFFIO_RX_B39n DIFFIO_TX_B40n DIFFIO_RX_B39p DIFFIO_TX_B40p DIFFIO_TX_B41n Pin List CF23 Emulated LVDS Output Channel F484 DIFFOUT_B1n DIFFOUT_B2n DIFFOUT_B1p DIFFOUT_B2p DIFFOUT_B3n DIFFOUT_B4n DIFFOUT_B3p DIFFOUT_B4p DIFFOUT_B5n DIFFOUT_B6n DIFFOUT_B5p DIFFOUT_B6p DIFFOUT_B7n DIFFOUT_B8n DIFFOUT_B7p DIFFOUT_B8p DIFFOUT_B33n DIFFOUT_B34n DIFFOUT_B33p DIFFOUT_B34p DIFFOUT_B35n DIFFOUT_B36n DIFFOUT_B35p DIFFOUT_B36p DIFFOUT_B37n DIFFOUT_B38n DIFFOUT_B37p DIFFOUT_B38p DIFFOUT_B39n DIFFOUT_B40n DIFFOUT_B39p DIFFOUT_B40p DIFFOUT_B41n F5 G4 D3 D4 C2 C1 E1 E2 G2 G1 J1 J2 L2 L1 N1 N2 R2 R1 U1 U2 W2 W1 Y3 Y4 AA2 AA1 V4 U4 M5 R4 P5 T4 V5 AA5 W5 AB3 V3 AB4 R6 U7 R5 U8 P6 W8 N6 W9 T7 U6 T8 V6 M6 R7 M7 P7 AB6 V9 AB5 V10 P8 AA7 N8 AB7 AA8 T9 AB8 U10 M8 AA10 M9 AA9 Y10 DQS for X8 DQS for X16 HMC Pin Assignment for DDR3/DDR2 (2), (3) HMC Pin Assignment for LPDDR2 (3) GND DQ2B DQ2B DQ2B DQ2B GND B_A_15 B_WE# B_A_14 B_CS#_1 B_A_13 B_CS#_0 B_A_12 B_A_11 B_A_9 B_A_10 B_A_8 DQ2B B_RAS# DQ2B B_CAS# GND DQ1B DQ1B DQ1B DQSn1B DQ1B DQS1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ2B DQ2B DQ2B DQSn2B DQ2B DQS2B B_CS#_1 B_CS#_0 B_CA_9 B_CA_8 GND Page 8 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 5A 5A 5A 5A 5A 5A 5A 5A VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Optional Function(s) Configuration Function FPLL_BL_CLKOUT1,FPLL_BL_CLKOUTn FPLL_BL_CLKOUT0,FPLL_BL_CLKOUTp,FPLL_BL_FB CLK1n CLK1p RZQ_0 CLK2n CLK2p CLK3n CLK3p RZQ_1 INIT_DONE PR_REQUEST CRC_ERROR nCEO CvP_CONFDONE Dedicated Tx/Rx Channel Emulated LVDS Output Channel F484 DQS for X8 DIFFIO_RX_B42n DIFFIO_TX_B41p DIFFIO_RX_B42p DIFFIO_RX_B43n DIFFIO_TX_B44n DIFFIO_RX_B43p DIFFIO_TX_B44p DIFFIO_TX_B45n DIFFIO_RX_B46n DIFFIO_TX_B45p DIFFIO_RX_B46p DIFFIO_RX_B47n DIFFIO_TX_B48n DIFFIO_RX_B47p DIFFIO_TX_B48p DIFFIO_TX_B49n DIFFIO_RX_B50n DIFFIO_TX_B49p DIFFIO_RX_B50p DIFFIO_RX_B51n DIFFIO_TX_B52n DIFFIO_RX_B51p DIFFIO_TX_B52p DIFFIO_TX_B53n DIFFIO_RX_B54n DIFFIO_TX_B53p DIFFIO_RX_B54p DIFFIO_RX_B55n DIFFIO_TX_B56n DIFFIO_RX_B55p DIFFIO_TX_B56p DIFFIO_TX_B57n DIFFIO_RX_B58n DIFFIO_TX_B57p DIFFIO_RX_B58p DIFFIO_RX_B59n DIFFIO_TX_B60n DIFFIO_RX_B59p DIFFIO_TX_B60p DIFFIO_TX_B61n DIFFIO_RX_B62n DIFFIO_TX_B61p DIFFIO_RX_B62p DIFFIO_RX_B63n DIFFIO_TX_B64n DIFFIO_RX_B63p DIFFIO_TX_B64p DIFFIO_TX_B65n DIFFIO_RX_B66n DIFFIO_TX_B65p DIFFIO_RX_B66p DIFFIO_RX_B67n DIFFIO_TX_B68n DIFFIO_RX_B67p DIFFIO_TX_B68p DIFFIO_TX_B69n DIFFIO_RX_B70n DIFFIO_TX_B69p DIFFIO_RX_B70p DIFFIO_RX_B71n DIFFIO_TX_B72n DIFFIO_RX_B71p DIFFIO_TX_B72p DIFFIO_TX_R1p DIFFIO_RX_R2p DIFFIO_TX_R1n DIFFIO_RX_R2n DIFFIO_TX_R3p DIFFIO_RX_R4p DIFFIO_TX_R3n DIFFIO_RX_R4n DIFFOUT_B42n DIFFOUT_B41p DIFFOUT_B42p DIFFOUT_B43n DIFFOUT_B44n DIFFOUT_B43p DIFFOUT_B44p DIFFOUT_B45n DIFFOUT_B46n DIFFOUT_B45p DIFFOUT_B46p DIFFOUT_B47n DIFFOUT_B48n DIFFOUT_B47p DIFFOUT_B48p DIFFOUT_B49n DIFFOUT_B50n DIFFOUT_B49p DIFFOUT_B50p DIFFOUT_B51n DIFFOUT_B52n DIFFOUT_B51p DIFFOUT_B52p DIFFOUT_B53n DIFFOUT_B54n DIFFOUT_B53p DIFFOUT_B54p DIFFOUT_B55n DIFFOUT_B56n DIFFOUT_B55p DIFFOUT_B56p DIFFOUT_B57n DIFFOUT_B58n DIFFOUT_B57p DIFFOUT_B58p DIFFOUT_B59n DIFFOUT_B60n DIFFOUT_B59p DIFFOUT_B60p DIFFOUT_B61n DIFFOUT_B62n DIFFOUT_B61p DIFFOUT_B62p DIFFOUT_B63n DIFFOUT_B64n DIFFOUT_B63p DIFFOUT_B64p DIFFOUT_B65n DIFFOUT_B66n DIFFOUT_B65p DIFFOUT_B66p DIFFOUT_B67n DIFFOUT_B68n DIFFOUT_B67p DIFFOUT_B68p DIFFOUT_B69n DIFFOUT_B70n DIFFOUT_B69p DIFFOUT_B70p DIFFOUT_B71n DIFFOUT_B72n DIFFOUT_B71p DIFFOUT_B72p DIFFOUT_R1p DIFFOUT_R2p DIFFOUT_R1n DIFFOUT_R2n DIFFOUT_R3p DIFFOUT_R4p DIFFOUT_R3n DIFFOUT_R4n T10 Y9 R9 U11 R12 U12 P12 AB10 R10 AB11 R11 P9 Y11 N9 AA12 AB13 V13 AB12 U13 T12 AA14 T13 AA13 AB15 Y14 AA15 Y15 V14 AB17 V15 AB18 AB20 Y16 AB21 Y17 T14 AA17 U15 AA18 AA19 V20 AA20 W19 V16 AB22 W16 AA22 Y22 Y20 W22 Y19 P14 Y21 R14 W21 U22 V19 V21 V18 U16 U21 U17 U20 T19 T18 T20 T17 T22 T15 R22 R15 DQ3B DQ3B DQ3B DQSn3B DQ3B DQS3B Pin List CF23 DQS for X16 DQ3B DQ3B DQ3B DQ3B HMC Pin Assignment for DDR3/DDR2 (2), (3) B_BA_2 B_BA_0 B_BA_1 B_CK# B_A_7 B_CK B_A_6 B_A_3 B_A_5 B_A_2 B_A_4 HMC Pin Assignment for LPDDR2 (3) B_CK# B_CA_7 B_CK B_CA_6 B_CA_3 B_CA_5 B_CA_2 B_CA_4 DQ3B B_A_1 B_CA_1 DQ3B B_A_0 B_CA_0 DQ4B DQ4B DQ4B DQSn4B DQ4B DQS4B DQ4B DQ4B DQ4B DQ4B B_DQ_0 B_DQ_2 B_DQ_1 B_DQS#_0 B_DQ_3 B_DQS_0 B_ODT_0 B_ODT_1 B_DQ_4 B_DQ_6 B_DQ_5 B_DQ_0 B_DQ_2 B_DQ_1 B_DQS#_0 B_DQ_3 B_DQS_0 B_ODT_0 B_ODT_1 B_DQ_4 B_DQ_6 B_DQ_5 DQ4B B_DQ_7 B_DQ_7 DQ4B B_DM_0 GND B_DQ_8 B_DQ_10 B_DQ_9 B_DQS#_1 B_DQ_11 B_DQS_1 B_CKE_1 B_CKE_0 B_DQ_12 B_DQ_14 B_DQ_13 DQ5B DQ5B DQ5B DQSn5B DQ5B DQS5B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ5B DQ5B DQ5B DQ5B DQ1B DQ1B DQ1B DQ1B B_DM_0 GND B_DQ_8 B_DQ_10 B_DQ_9 B_DQS#_1 B_DQ_11 B_DQS_1 B_CKE_1 B_CKE_0 B_DQ_12 B_DQ_14 B_DQ_13 DQ5B DQ1B B_DQ_15 B_DQ_15 DQ5B DQ1B DQ6B DQ6B DQ6B DQSn6B DQ6B DQS6B DQ1B DQ1B DQ1B DQSn1B DQ1B DQS1B DQ6B DQ6B DQ6B DQ6B DQ1B DQ1B DQ1B DQ1B DQ6B DQ1B DQ6B DQ1R DQ1B B_DM_1 GND B_DQ_16 B_DQ_18 B_DQ_17 B_DQS#_2 B_DQ_19 B_DQS_2 B_RESET# GND B_DQ_20 B_DQ_22 B_DQ_21 GND B_DQ_23 GND B_DM_2 B_DM_1 GND B_DQ_16 B_DQ_18 B_DQ_17 B_DQS#_2 B_DQ_19 B_DQS_2 B_RESET# GND B_DQ_20 B_DQ_22 B_DQ_21 GND B_DQ_23 GND B_DM_2 DQ1R DQ1R DQ1R DQ1R DQ1R Page 9 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function 5A 5A 5A 5A 5A 5A 5A 5A 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO GND IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Optional Function(s) CLK6p CLK6n FPLL_BR_CLKOUT0,FPLL_BR_CLKOUTp,FPLL_BR_FB FPLL_BR_CLKOUT1,FPLL_BR_CLKOUTn CLK11p CLK11n Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F484 DEV_OE nPERSTL0 DEV_CLRn nPERSTL1 DIFFIO_TX_R5p DIFFIO_RX_R6p DIFFIO_TX_R5n DIFFIO_RX_R6n DIFFIO_TX_R7p DIFFIO_RX_R8p DIFFIO_TX_R7n DIFFIO_RX_R8n DIFFIO_RX_R41p DIFFIO_TX_R42p DIFFIO_RX_R41n DIFFIO_TX_R42n DIFFIO_RX_R43p DIFFIO_TX_R44p DIFFIO_RX_R43n DIFFIO_TX_R44n DIFFIO_RX_R45p DIFFIO_TX_R46p DIFFIO_RX_R45n DIFFIO_TX_R46n DIFFIO_RX_R47p DIFFIO_TX_R48p DIFFIO_RX_R47n DIFFIO_TX_R48n DIFFOUT_R5p DIFFOUT_R6p DIFFOUT_R5n DIFFOUT_R6n DIFFOUT_R7p DIFFOUT_R8p DIFFOUT_R7n DIFFOUT_R8n DIFFOUT_R41p DIFFOUT_R42p DIFFOUT_R41n DIFFOUT_R42n DIFFOUT_R43p DIFFOUT_R44p DIFFOUT_R43n DIFFOUT_R44n DIFFOUT_R45p DIFFOUT_R46p DIFFOUT_R45n DIFFOUT_R46n DIFFOUT_R47p DIFFOUT_R48p DIFFOUT_R47n DIFFOUT_R48n DIFFIO_RX_T9p DIFFIO_TX_T10p DIFFIO_RX_T9n DIFFIO_TX_T10n DIFFIO_RX_T11p DIFFIO_TX_T12p DIFFIO_RX_T11n DIFFIO_TX_T12n DIFFIO_RX_T13p DIFFIO_TX_T14p DIFFIO_RX_T13n DIFFIO_TX_T14n DIFFIO_RX_T15p DIFFIO_TX_T16p DIFFIO_RX_T15n DIFFIO_TX_T16n DIFFIO_RX_T25p DIFFIO_TX_T26p DIFFIO_RX_T25n DIFFIO_TX_T26n DIFFIO_RX_T27p DIFFIO_TX_T28p DIFFIO_RX_T27n DIFFIO_TX_T28n DIFFIO_RX_T29p DIFFIO_TX_T30p DIFFIO_RX_T29n DIFFIO_TX_T30n DIFFIO_RX_T31p DIFFIO_TX_T32p DIFFIO_RX_T31n DIFFIO_TX_T32n DIFFIO_RX_T33p DIFFIO_TX_T34p DIFFIO_RX_T33n DIFFIO_TX_T34n DIFFIO_RX_T35p DIFFIO_TX_T36p DIFFIO_RX_T35n DIFFIO_TX_T36n DIFFIO_RX_T37p DIFFIO_TX_T38p DIFFIO_RX_T37n DIFFIO_TX_T38n DIFFIO_RX_T39p DIFFIO_TX_T40p DIFFOUT_T9p DIFFOUT_T10p DIFFOUT_T9n DIFFOUT_T10n DIFFOUT_T11p DIFFOUT_T12p DIFFOUT_T11n DIFFOUT_T12n DIFFOUT_T13p DIFFOUT_T14p DIFFOUT_T13n DIFFOUT_T14n DIFFOUT_T15p DIFFOUT_T16p DIFFOUT_T15n DIFFOUT_T16n DIFFOUT_T25p DIFFOUT_T26p DIFFOUT_T25n DIFFOUT_T26n DIFFOUT_T27p DIFFOUT_T28p DIFFOUT_T27n DIFFOUT_T28n DIFFOUT_T29p DIFFOUT_T30p DIFFOUT_T29n DIFFOUT_T30n DIFFOUT_T31p DIFFOUT_T32p DIFFOUT_T31n DIFFOUT_T32n DIFFOUT_T33p DIFFOUT_T34p DIFFOUT_T33n DIFFOUT_T34n DIFFOUT_T35p DIFFOUT_T36p DIFFOUT_T35n DIFFOUT_T36n DIFFOUT_T37p DIFFOUT_T38p DIFFOUT_T37n DIFFOUT_T38n DIFFOUT_T39p DIFFOUT_T40p R21 R16 P22 R17 P19 P16 P18 P17 N16 N20 M16 N21 N19 M22 M18 L22 K17 M20 L17 M21 L19 K21 L18 K22 F17 H21 E21 G21 D21 E19 C20 D19 B20 J21 B18 J22 B17 C21 G22 B21 F22 K20 B16 K19 C16 D17 G17 E16 G16 G18 J19 H18 J18 E15 A15 F15 A14 H16 J17 H15 K16 C15 G15 B15 F14 H14 B13 J13 A13 E14 J11 Pin List CF23 DQS for X8 DQS for X16 HMC Pin Assignment for DDR3/DDR2 (2), (3) HMC Pin Assignment for LPDDR2 (3) GND T_DM_4 GND T_DQ_39 T_DQ_37 T_DQ_38 T_DQ_36 GND T_DQS_4 GND T_DQS#_4 T_DQ_35 T_DQ_33 T_DQ_34 T_DQ_32 GND GND T_DM_2 GND T_DQ_23 T_DQ_21 T_DQ_22 T_DQ_20 GND T_DQS_2 T_RESET# T_DQS#_2 T_DQ_19 T_DQ_17 T_DQ_18 T_DQ_16 GND GND T_DM_4 GND T_DQ_39 T_DQ_37 T_DQ_38 T_DQ_36 GND T_DQS_4 GND T_DQS#_4 T_DQ_35 T_DQ_33 T_DQ_34 T_DQ_32 GND GND T_DM_2 GND T_DQ_23 T_DQ_21 T_DQ_22 T_DQ_20 GND T_DQS_2 T_RESET# T_DQS#_2 T_DQ_19 T_DQ_17 T_DQ_18 T_DQ_16 GND DQS1R DQ1R DQSn1R DQ1R DQ1R DQ1R DQ2R DQ2R DQ2R DQ2R DQ2R DQ2R DQS2R DQSn2R DQ2R DQ2R DQ2R DQ2R DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQS1T DQSn1T DQ1T DQ1T DQ1T DQ1T DQ2T DQ1T DQ2T DQ2T DQ2T DQ2T DQ2T DQS2T DQ1T DQ1T DQ1T DQ1T DQ1T DQS1T DQSn2T DQ2T DQ2T DQ2T DQ2T DQSn1T DQ1T DQ1T DQ1T DQ1T DQ3T DQ1T T_DM_1 T_DM_1 DQ3T DQ3T DQ3T DQ3T DQ3T DQS3T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQSn3T DQ3T DQ3T DQ3T DQ1T DQ1T DQ1T DQ1T T_DQ_15 T_DQ_13 T_DQ_14 T_DQ_12 T_CKE_0 T_DQS_1 T_CKE_1 T_DQS#_1 T_DQ_11 T_DQ_9 T_DQ_10 T_DQ_15 T_DQ_13 T_DQ_14 T_DQ_12 T_CKE_0 T_DQS_1 T_CKE_1 T_DQS#_1 T_DQ_11 T_DQ_9 T_DQ_10 Page 10 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 9A 9A 9A 9A 9A 9A 9A 9A 9A 9A VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO MSEL0 CONF_DONE MSEL1 nSTATUS nCE MSEL2 MSEL3 nCONFIG MSEL4 GND GND GND GND GND GND GND GND GND GND GND GND PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Optional Function(s) Configuration Function CLK10p CLK10n RZQ_2 CLK9p CLK9n FPLL_TL_CLKOUT0,FPLL_TL_CLKOUTp,FPLL_TL_FB FPLL_TL_CLKOUT1,FPLL_TL_CLKOUTn CLK8p,FPLL_TL_FBp CLK8n,FPLL_TL_FBn Dedicated Tx/Rx Channel Emulated LVDS Output Channel F484 DQS for X8 DQS for X16 DIFFIO_RX_T39n DIFFIO_TX_T40n DIFFIO_RX_T41p DIFFIO_TX_T42p DIFFIO_RX_T41n DIFFIO_TX_T42n DIFFIO_RX_T43p DIFFIO_TX_T44p DIFFIO_RX_T43n DIFFIO_TX_T44n DIFFIO_RX_T45p DIFFIO_TX_T46p DIFFIO_RX_T45n DIFFIO_TX_T46n DIFFIO_RX_T47p DIFFIO_TX_T48p DIFFIO_RX_T47n DIFFIO_TX_T48n DIFFIO_RX_T49p DIFFIO_TX_T50p DIFFIO_RX_T49n DIFFIO_TX_T50n DIFFIO_RX_T51p DIFFIO_TX_T52p DIFFIO_RX_T51n DIFFIO_TX_T52n DIFFIO_RX_T53p DIFFIO_TX_T54p DIFFIO_RX_T53n DIFFIO_TX_T54n DIFFIO_RX_T55p DIFFIO_TX_T56p DIFFIO_RX_T55n DIFFIO_TX_T56n DIFFIO_RX_T57p DIFFIO_TX_T58p DIFFIO_RX_T57n DIFFIO_TX_T58n DIFFIO_RX_T59p DIFFIO_TX_T60p DIFFIO_RX_T59n DIFFIO_TX_T60n DIFFIO_RX_T61p DIFFIO_TX_T62p DIFFIO_RX_T61n DIFFIO_TX_T62n DIFFIO_RX_T63p DIFFIO_TX_T64p DIFFIO_RX_T63n DIFFIO_TX_T64n DIFFOUT_T39n DIFFOUT_T40n DIFFOUT_T41p DIFFOUT_T42p DIFFOUT_T41n DIFFOUT_T42n DIFFOUT_T43p DIFFOUT_T44p DIFFOUT_T43n DIFFOUT_T44n DIFFOUT_T45p DIFFOUT_T46p DIFFOUT_T45n DIFFOUT_T46n DIFFOUT_T47p DIFFOUT_T48p DIFFOUT_T47n DIFFOUT_T48n DIFFOUT_T49p DIFFOUT_T50p DIFFOUT_T49n DIFFOUT_T50n DIFFOUT_T51p DIFFOUT_T52p DIFFOUT_T51n DIFFOUT_T52n DIFFOUT_T53p DIFFOUT_T54p DIFFOUT_T53n DIFFOUT_T54n DIFFOUT_T55p DIFFOUT_T56p DIFFOUT_T55n DIFFOUT_T56n DIFFOUT_T57p DIFFOUT_T58p DIFFOUT_T57n DIFFOUT_T58n DIFFOUT_T59p DIFFOUT_T60p DIFFOUT_T59n DIFFOUT_T60n DIFFOUT_T61p DIFFOUT_T62p DIFFOUT_T61n DIFFOUT_T62n DIFFOUT_T63p DIFFOUT_T64p DIFFOUT_T63n DIFFOUT_T64n F13 H10 H13 G11 G13 F12 D13 B12 C13 A12 H11 L8 G12 K9 D12 C11 E12 B11 G10 L7 F10 K7 J7 H8 J8 G8 J9 A10 H9 A9 B10 A5 C9 B5 E10 B6 F9 B7 A8 C6 A7 D6 E9 D7 D9 C8 G6 F7 H6 E7 L6 K6 J6 H5 G5 A2 E5 A4 F3 C5 J20 L21 N22 T21 Y18 AB14 V12 AA6 V7 U5 AA4 DQ3T DQ1T MSEL0 CONF_DONE MSEL1 nSTATUS nCE MSEL2 MSEL3 nCONFIG MSEL4 Pin List CF23 HMC Pin Assignment for DDR3/DDR2 (2), (3) T_DQ_8 GND HMC Pin Assignment for LPDDR2 (3) T_DQ_8 GND DQ4T T_DM_0 T_DM_0 DQ4T DQ4T DQ4T DQ4T DQ4T DQS4T DQSn4T DQ4T DQ4T DQ4T DQ4T T_DQ_7 T_DQ_5 T_DQ_6 T_DQ_4 T_ODT_1 T_DQS_0 T_ODT_0 T_DQS#_0 T_DQ_3 T_DQ_1 T_DQ_2 T_DQ_0 T_DQ_7 T_DQ_5 T_DQ_6 T_DQ_4 T_ODT_1 T_DQS_0 T_ODT_0 T_DQS#_0 T_DQ_3 T_DQ_1 T_DQ_2 T_DQ_0 DQ5T T_A_0 T_CA_0 DQ5T DQ5T DQ5T DQ5T DQ5T DQS5T T_A_1 T_A_4 T_A_2 T_A_5 T_A_3 T_CK T_A_6 T_CK# T_A_7 T_BA_1 T_BA_0 T_BA_2 GND T_CA_1 T_CA_4 T_CA_2 T_CA_5 T_CA_3 T_CK T_CA_6 T_CK# T_CA_7 DQSn5T DQ5T DQ5T DQ5T DQ5T DQ6T T_CAS# DQ6T DQ6T DQ6T DQ6T DQ6T DQS6T T_RAS# T_A_8 T_A_10 T_A_9 T_A_11 T_CS#_0 T_A_12 T_CS#_1 T_A_13 T_A_14 T_WE# T_A_15 GND DQSn6T DQ6T DQ6T DQ6T DQ6T GND T_CA_8 T_CA_9 T_CS#_0 T_CS#_1 GND Page 11 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Emulated LVDS Output Channel F484 DQS for X8 DQS for X16 HMC Pin Assignment for DDR3/DDR2 (2), (3) HMC Pin Assignment for LPDDR2 (3) Y5 U3 R3 P4 P2 N5 L3 M4 L5 K2 J3 K4 H2 H3 J5 G3 H4 F2 B1 E3 AB19 AB9 AB2 AB1 AA11 AA3 Y2 Y1 W4 W3 V22 V17 V2 V1 U9 T16 T2 T1 R13 P10 P1 N17 N15 N13 N11 N7 N3 M14 M12 M10 M2 M1 L15 L13 L11 K14 K12 K10 K8 K1 J15 H22 H12 H7 H1 G19 G9 F16 F6 F1 E13 Pin List CF23 Page 12 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC DNU DNU DNU DNU DNU DNU VCCPGM VCCPGM VCCPGM VCCBAT VCCIO3A VCCIO3A VCCIO3B VCCIO3B VCCIO3B VCCIO3B VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO5A VCCIO5A VCCIO5B VCCIO5B VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO8A PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Emulated LVDS Output Channel F484 DQS for X8 DQS for X16 HMC Pin Assignment for DDR3/DDR2 (2), (3) HMC Pin Assignment for LPDDR2 (3) E4 D20 D10 D5 D2 D1 C17 C4 C3 B14 B9 B2 A21 A11 P15 P13 P11 N14 N12 N10 M15 M13 M11 L16 L14 L12 L10 K15 K13 K11 J16 J14 J12 J10 B3 B4 Y6 V11 E17 L9 V8 R19 F8 A3 T6 Y8 R8 Y13 W10 T11 U19 AA21 AA16 W20 W15 U14 P20 R18 M19 K18 B19 H17 G14 F21 F11 E18 D15 C22 C12 A16 A6 Pin List CF23 Page 13 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number 3A 3B 4A 5A 5B 7A 8A VREF VREFB3AN0 VREFB3BN0 VREFB4AN0 VREFB5AN0 VREFB5BN0 VREFB7AN0 VREFB8AN0 Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel VCCIO8A VCCIO8A VCCIO8A VCCPD3A VCCPD3B4A VCCPD3B4A VCCPD3B4A VCCPD3B4A VCCPD5A VCCPD5B VCCPD5B VCCPD7A8A VCCPD7A8A VCCPD7A8A VCCPD7A8A VCCPD7A8A VREFB3AN0 VREFB3BN0 VREFB4AN0 VREFB5AN0 VREFB5BN0 VREFB7AN0 VREFB8AN0 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VCCH_GXBL VCCH_GXBL VCCL_GXBL VCCL_GXBL RREF_TL VCCA_FPLL VCCA_FPLL VCCA_FPLL VCCA_FPLL VCC_AUX VCC_AUX VCC_AUX VCC_AUX VCC_AUX VCC_AUX VCCE_GXBL VCCE_GXBL VCCE_GXBL VCCE_GXBL Emulated LVDS Output Channel F484 DQS for X8 DQS for X16 HMC Pin Assignment for DDR3/DDR2 (2), (3) HMC Pin Assignment for LPDDR2 (3) G7 E8 C7 W6 W12 W17 W14 W11 P21 M17 N18 D8 E11 D16 D14 C10 Y7 Y12 AB16 R20 L20 C14 B8 H20 G20 F20 F19 F18 E22 E20 D22 C19 C18 B22 A22 A20 A19 A18 A17 M3 T3 K3 P3 A1 T5 F4 U18 H19 E6 D11 W18 W13 W7 D18 J4 N4 L4 K5 Notes: (1) For more information about pin definition and pin connection guidelines, refer to the Cyclone V Device Family Pin Connection Guidelines. (2) RESET pin is only applicable for DDR3 device. (3) This package supports only a 24-bit HMC using T_DQ_[0..23] pins. The T_DQ_[32..39] pins cannot be used for HMC. PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Pin List CF23 Page 14 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B VREF Pin Name/Function VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 GXB_TX_L8n GXB_TX_L8p GXB_RX_L8p,GXB_REFCLK_L8p GXB_RX_L8n,GXB_REFCLK_L8n GXB_TX_L7n GXB_TX_L7p GXB_RX_L7p,GXB_REFCLK_L7p GXB_RX_L7n,GXB_REFCLK_L7n GXB_TX_L6n GXB_TX_L6p GXB_RX_L6p,GXB_REFCLK_L6p GXB_RX_L6n,GXB_REFCLK_L6n REFCLK2Lp REFCLK2Ln REFCLK1Ln REFCLK1Lp GXB_TX_L5n GXB_TX_L5p GXB_RX_L5p,GXB_REFCLK_L5p GXB_RX_L5n,GXB_REFCLK_L5n GXB_TX_L4n GXB_TX_L4p GXB_RX_L4p,GXB_REFCLK_L4p GXB_RX_L4n,GXB_REFCLK_L4n GXB_TX_L3n GXB_TX_L3p GXB_RX_L3p,GXB_REFCLK_L3p GXB_RX_L3n,GXB_REFCLK_L3n GXB_TX_L2n GXB_TX_L2p GXB_RX_L2p,GXB_REFCLK_L2p GXB_RX_L2n,GXB_REFCLK_L2n GXB_TX_L1n GXB_TX_L1p GXB_RX_L1p,GXB_REFCLK_L1p GXB_RX_L1n,GXB_REFCLK_L1n GXB_TX_L0n GXB_TX_L0p GXB_RX_L0p,GXB_REFCLK_L0p GXB_RX_L0n,GXB_REFCLK_L0n REFCLK0Lp REFCLK0Ln TDO nCSO TMS AS_DATA3 TCK AS_DATA2 TDI AS_DATA1 DCLK AS_DATA0,ASDO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Optional Function(s) Configuration Function TDO DATA4 TMS DATA3 TCK DATA2 TDI DATA1 DCLK DATA0 DATA6 DATA5 DATA8 DATA7 DATA10 DATA9 DATA12 DATA11 DATA14 DATA13 CLKUSR DATA15 PR_DONE PR_READY PR_ERROR Dedicated Tx/Rx Channel DIFFIO_RX_B1n DIFFIO_TX_B2n DIFFIO_RX_B1p DIFFIO_TX_B2p DIFFIO_RX_B3n DIFFIO_TX_B4n DIFFIO_RX_B3p DIFFIO_TX_B4p DIFFIO_RX_B5n DIFFIO_TX_B6n DIFFIO_RX_B5p DIFFIO_TX_B6p DIFFIO_RX_B7n DIFFIO_TX_B8n DIFFIO_RX_B7p DIFFIO_TX_B8p DIFFIO_TX_B33n DIFFIO_RX_B34n DIFFIO_TX_B33p DIFFIO_RX_B34p DIFFIO_RX_B35n DIFFIO_TX_B36n DIFFIO_RX_B35p DIFFIO_TX_B36p DIFFIO_TX_B37n DIFFIO_RX_B38n Pin List DF27 Emulated LVDS Output Channel F672 DIFFOUT_B1n DIFFOUT_B2n DIFFOUT_B1p DIFFOUT_B2p DIFFOUT_B3n DIFFOUT_B4n DIFFOUT_B3p DIFFOUT_B4p DIFFOUT_B5n DIFFOUT_B6n DIFFOUT_B5p DIFFOUT_B6p DIFFOUT_B7n DIFFOUT_B8n DIFFOUT_B7p DIFFOUT_B8p DIFFOUT_B33n DIFFOUT_B34n DIFFOUT_B33p DIFFOUT_B34p DIFFOUT_B35n DIFFOUT_B36n DIFFOUT_B35p DIFFOUT_B36p DIFFOUT_B37n DIFFOUT_B38n C3 C4 D2 D1 E3 E4 F2 F1 G3 G4 H2 H1 M6 L5 P6 N7 K1 K2 M2 M1 P1 P2 T2 T1 W3 W4 V2 V1 AA3 AA4 Y2 Y1 AC3 AC4 AB2 AB1 AE3 AE4 AD2 AD1 V6 W6 V7 Y6 R6 U6 Y5 AB5 T6 AD5 N8 AF5 T7 U7 T8 V8 W8 AB6 Y9 AA6 R10 AA7 R9 Y8 R8 AD6 P8 AD7 U9 Y11 T9 W11 T11 AC10 R11 AB10 AC8 AB11 DQS for X8 DQS for X16 HMC Pin Assignment for DDR3/DDR2 (2) HMC Pin Assignment for LPDDR2 GND B_A_15 B_WE# B_A_14 B_CS#_1 B_A_13 B_CS#_0 B_A_12 B_A_11 B_A_9 GND DQ1B DQ1B DQ1B DQSn1B DQ1B DQS1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ2B DQ2B DQ2B DQSn2B DQ2B DQS2B DQ2B DQ2B B_CS#_1 B_CS#_0 B_CA_9 Page 15 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Optional Function(s) CLK0n,FPLL_BL_FBn CLK0p,FPLL_BL_FBp FPLL_BL_CLKOUT1,FPLL_BL_CLKOUTn FPLL_BL_CLKOUT0,FPLL_BL_CLKOUTp,FPLL_BL_FB CLK1n CLK1p RZQ_0 CLK2n CLK2p CLK3n CLK3p Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F672 DQS for X8 DIFFIO_TX_B37p DIFFIO_RX_B38p DIFFIO_RX_B39n DIFFIO_TX_B40n DIFFIO_RX_B39p DIFFIO_TX_B40p DIFFIO_TX_B41n DIFFIO_RX_B42n DIFFIO_TX_B41p DIFFIO_RX_B42p DIFFIO_RX_B43n DIFFIO_TX_B44n DIFFIO_RX_B43p DIFFIO_TX_B44p DIFFIO_TX_B45n DIFFIO_RX_B46n DIFFIO_TX_B45p DIFFIO_RX_B46p DIFFIO_RX_B47n DIFFIO_TX_B48n DIFFIO_RX_B47p DIFFIO_TX_B48p DIFFIO_TX_B49n DIFFIO_RX_B50n DIFFIO_TX_B49p DIFFIO_RX_B50p DIFFIO_RX_B51n DIFFIO_TX_B52n DIFFIO_RX_B51p DIFFIO_TX_B52p DIFFIO_TX_B53n DIFFIO_RX_B54n DIFFIO_TX_B53p DIFFIO_RX_B54p DIFFIO_RX_B55n DIFFIO_TX_B56n DIFFIO_RX_B55p DIFFIO_TX_B56p DIFFIO_TX_B57n DIFFIO_RX_B58n DIFFIO_TX_B57p DIFFIO_RX_B58p DIFFIO_RX_B59n DIFFIO_TX_B60n DIFFIO_RX_B59p DIFFIO_TX_B60p DIFFIO_TX_B61n DIFFIO_RX_B62n DIFFIO_TX_B61p DIFFIO_RX_B62p DIFFIO_RX_B63n DIFFIO_TX_B64n DIFFIO_RX_B63p DIFFIO_TX_B64p DIFFIO_TX_B65n DIFFIO_RX_B66n DIFFIO_TX_B65p DIFFIO_RX_B66p DIFFIO_RX_B67n DIFFIO_TX_B68n DIFFIO_RX_B67p DIFFIO_TX_B68p DIFFIO_TX_B69n DIFFIO_RX_B70n DIFFIO_TX_B69p DIFFIO_RX_B70p DIFFIO_RX_B71n DIFFIO_TX_B72n DIFFIO_RX_B71p DIFFIO_TX_B72p DIFFIO_TX_B73n DIFFIO_RX_B74n DIFFIO_TX_B73p DIFFIO_RX_B74p DIFFIO_RX_B75n DIFFIO_TX_B76n DIFFIO_RX_B75p DIFFIO_TX_B76p DIFFOUT_B37p DIFFOUT_B38p DIFFOUT_B39n DIFFOUT_B40n DIFFOUT_B39p DIFFOUT_B40p DIFFOUT_B41n DIFFOUT_B42n DIFFOUT_B41p DIFFOUT_B42p DIFFOUT_B43n DIFFOUT_B44n DIFFOUT_B43p DIFFOUT_B44p DIFFOUT_B45n DIFFOUT_B46n DIFFOUT_B45p DIFFOUT_B46p DIFFOUT_B47n DIFFOUT_B48n DIFFOUT_B47p DIFFOUT_B48p DIFFOUT_B49n DIFFOUT_B50n DIFFOUT_B49p DIFFOUT_B50p DIFFOUT_B51n DIFFOUT_B52n DIFFOUT_B51p DIFFOUT_B52p DIFFOUT_B53n DIFFOUT_B54n DIFFOUT_B53p DIFFOUT_B54p DIFFOUT_B55n DIFFOUT_B56n DIFFOUT_B55p DIFFOUT_B56p DIFFOUT_B57n DIFFOUT_B58n DIFFOUT_B57p DIFFOUT_B58p DIFFOUT_B59n DIFFOUT_B60n DIFFOUT_B59p DIFFOUT_B60p DIFFOUT_B61n DIFFOUT_B62n DIFFOUT_B61p DIFFOUT_B62p DIFFOUT_B63n DIFFOUT_B64n DIFFOUT_B63p DIFFOUT_B64p DIFFOUT_B65n DIFFOUT_B66n DIFFOUT_B65p DIFFOUT_B66p DIFFOUT_B67n DIFFOUT_B68n DIFFOUT_B67p DIFFOUT_B68p DIFFOUT_B69n DIFFOUT_B70n DIFFOUT_B69p DIFFOUT_B70p DIFFOUT_B71n DIFFOUT_B72n DIFFOUT_B71p DIFFOUT_B72p DIFFOUT_B73n DIFFOUT_B74n DIFFOUT_B73p DIFFOUT_B74p DIFFOUT_B75n DIFFOUT_B76n DIFFOUT_B75p DIFFOUT_B76p AC9 AB12 T12 Y10 T13 W10 V9 AE8 V10 AD8 P10 AF9 N10 AE9 AF8 U11 AF7 U10 P12 AF6 P11 AE6 AE11 AA14 AD11 Y14 W13 AD12 V13 AD13 AE10 Y13 AD10 W12 V12 AF12 U12 AF11 AC13 AC15 AC14 AB15 V14 AF13 U14 AE13 AF14 AB16 AE14 AA16 Y16 AF18 Y15 AE18 AD18 AD16 AC18 AD17 W15 AF19 V15 AE19 AF22 AC17 AF21 AB17 U17 AE21 T17 AE20 AD20 AE15 AC20 AE16 W17 AD21 W16 AD22 DQ2B DQ2B HMC Pin Assignment for DDR3/DDR2 (2) B_A_10 B_A_8 DQ2B B_RAS# DQ2B DQ3B DQ3B DQ3B DQ3B B_CAS# GND B_BA_2 B_BA_0 B_BA_1 B_CK# B_A_7 B_CK B_A_6 B_A_3 B_A_5 B_A_2 B_A_4 B_CK# B_CA_7 B_CK B_CA_6 B_CA_3 B_CA_5 B_CA_2 B_CA_4 DQ3B B_A_1 B_CA_1 DQ3B B_A_0 B_CA_0 DQ4B DQ4B DQ4B DQSn4B DQ4B DQS4B DQ4B DQ4B DQ4B DQ4B B_DQ_0 B_DQ_2 B_DQ_1 B_DQS#_0 B_DQ_3 B_DQS_0 B_ODT_0 B_ODT_1 B_DQ_4 B_DQ_6 B_DQ_5 B_DQ_0 B_DQ_2 B_DQ_1 B_DQS#_0 B_DQ_3 B_DQS_0 B_ODT_0 B_ODT_1 B_DQ_4 B_DQ_6 B_DQ_5 DQ4B B_DQ_7 B_DQ_7 DQ4B B_DM_0 GND B_DQ_8 B_DQ_10 B_DQ_9 B_DQS#_1 B_DQ_11 B_DQS_1 B_CKE_1 B_CKE_0 B_DQ_12 B_DQ_14 B_DQ_13 Pin List DF27 DQS for X16 DQ3B DQ3B DQ3B DQSn3B DQ3B DQS3B HMC Pin Assignment for LPDDR2 B_CA_8 GND DQ5B DQ5B DQ5B DQSn5B DQ5B DQS5B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ5B DQ5B DQ5B DQ5B DQ1B DQ1B DQ1B DQ1B B_DM_0 GND B_DQ_8 B_DQ_10 B_DQ_9 B_DQS#_1 B_DQ_11 B_DQS_1 B_CKE_1 B_CKE_0 B_DQ_12 B_DQ_14 B_DQ_13 DQ5B DQ1B B_DQ_15 B_DQ_15 DQ5B DQ1B DQ6B DQ6B DQ6B DQSn6B DQ6B DQS6B DQ1B DQ1B DQ1B DQSn1B DQ1B DQS1B DQ6B DQ6B DQ6B DQ6B DQ1B DQ1B DQ1B DQ1B DQ6B DQ1B DQ6B DQ1B DQ7B DQ7B DQ7B DQSn7B DQ7B DQS7B DQ2B DQ2B DQ2B DQ2B DQ2B DQ2B B_DM_1 GND B_DQ_16 B_DQ_18 B_DQ_17 B_DQS#_2 B_DQ_19 B_DQS_2 B_RESET# GND B_DQ_20 B_DQ_22 B_DQ_21 GND B_DQ_23 GND B_DM_2 GND B_DQ_24 B_DQ_26 B_DQ_25 B_DQS#_3 B_DQ_27 B_DQS_3 GND B_DM_1 GND B_DQ_16 B_DQ_18 B_DQ_17 B_DQS#_2 B_DQ_19 B_DQS_2 B_RESET# GND B_DQ_20 B_DQ_22 B_DQ_21 GND B_DQ_23 GND B_DM_2 GND B_DQ_24 B_DQ_26 B_DQ_25 B_DQS#_3 B_DQ_27 B_DQS_3 GND Page 16 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 6A 6A 6A 6A 6A 6A VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Optional Function(s) Configuration Function RZQ_1 INIT_DONE PR_REQUEST CRC_ERROR nCEO CvP_CONFDONE DEV_OE nPERSTL0 DEV_CLRn nPERSTL1 CLK7p,FPLL_BR_FBp CLK7n,FPLL_BR_FBn CLK6p CLK6n FPLL_BR_CLKOUT0,FPLL_BR_CLKOUTp,FPLL_BR_FB FPLL_BR_CLKOUT1,FPLL_BR_CLKOUTn CLK5p CLK5n FPLL_TR_CLKOUT0,FPLL_TR_CLKOUTp,FPLL_TR_FB Dedicated Tx/Rx Channel Emulated LVDS Output Channel F672 DQS for X8 DQS for X16 DIFFIO_TX_B77n DIFFIO_RX_B78n DIFFIO_TX_B77p DIFFIO_RX_B78p DIFFIO_RX_B79n DIFFIO_TX_B80n DIFFIO_RX_B79p DIFFIO_TX_B80p DIFFIO_TX_B81n DIFFIO_RX_B82n DIFFIO_TX_B81p DIFFIO_RX_B82p DIFFIO_RX_B83n DIFFIO_TX_B84n DIFFIO_RX_B83p DIFFIO_TX_B84p DIFFIO_TX_B85n DIFFIO_RX_B86n DIFFIO_TX_B85p DIFFIO_RX_B86p DIFFIO_RX_B87n DIFFIO_TX_B88n DIFFIO_RX_B87p DIFFIO_TX_B88p DIFFIO_TX_R1p DIFFIO_RX_R2p DIFFIO_TX_R1n DIFFIO_RX_R2n DIFFIO_TX_R3p DIFFIO_RX_R4p DIFFIO_TX_R3n DIFFIO_RX_R4n DIFFIO_TX_R5p DIFFIO_RX_R6p DIFFIO_TX_R5n DIFFIO_RX_R6n DIFFIO_TX_R7p DIFFIO_RX_R8p DIFFIO_TX_R7n DIFFIO_RX_R8n DIFFIO_RX_R33p DIFFIO_TX_R34p DIFFIO_RX_R33n DIFFIO_TX_R34n DIFFIO_RX_R35p DIFFIO_TX_R36p DIFFIO_RX_R35n DIFFIO_TX_R36n DIFFIO_RX_R37p DIFFIO_TX_R38p DIFFIO_RX_R37n DIFFIO_TX_R38n DIFFIO_RX_R39p DIFFIO_TX_R40p DIFFIO_RX_R39n DIFFIO_TX_R40n DIFFIO_RX_R41p DIFFIO_TX_R42p DIFFIO_RX_R41n DIFFIO_TX_R42n DIFFIO_RX_R43p DIFFIO_TX_R44p DIFFIO_RX_R43n DIFFIO_TX_R44n DIFFIO_RX_R45p DIFFIO_TX_R46p DIFFIO_RX_R45n DIFFIO_TX_R46n DIFFIO_RX_R47p DIFFIO_TX_R48p DIFFIO_RX_R47n DIFFIO_TX_R48n DIFFIO_RX_R49p DIFFIO_TX_R50p DIFFIO_RX_R49n DIFFIO_TX_R50n DIFFIO_RX_R51p DIFFIO_TX_R52p DIFFOUT_B77n DIFFOUT_B78n DIFFOUT_B77p DIFFOUT_B78p DIFFOUT_B79n DIFFOUT_B80n DIFFOUT_B79p DIFFOUT_B80p DIFFOUT_B81n DIFFOUT_B82n DIFFOUT_B81p DIFFOUT_B82p DIFFOUT_B83n DIFFOUT_B84n DIFFOUT_B83p DIFFOUT_B84p DIFFOUT_B85n DIFFOUT_B86n DIFFOUT_B85p DIFFOUT_B86p DIFFOUT_B87n DIFFOUT_B88n DIFFOUT_B87p DIFFOUT_B88p DIFFOUT_R1p DIFFOUT_R2p DIFFOUT_R1n DIFFOUT_R2n DIFFOUT_R3p DIFFOUT_R4p DIFFOUT_R3n DIFFOUT_R4n DIFFOUT_R5p DIFFOUT_R6p DIFFOUT_R5n DIFFOUT_R6n DIFFOUT_R7p DIFFOUT_R8p DIFFOUT_R7n DIFFOUT_R8n DIFFOUT_R33p DIFFOUT_R34p DIFFOUT_R33n DIFFOUT_R34n DIFFOUT_R35p DIFFOUT_R36p DIFFOUT_R35n DIFFOUT_R36n DIFFOUT_R37p DIFFOUT_R38p DIFFOUT_R37n DIFFOUT_R38n DIFFOUT_R39p DIFFOUT_R40p DIFFOUT_R39n DIFFOUT_R40n DIFFOUT_R41p DIFFOUT_R42p DIFFOUT_R41n DIFFOUT_R42n DIFFOUT_R43p DIFFOUT_R44p DIFFOUT_R43n DIFFOUT_R44n DIFFOUT_R45p DIFFOUT_R46p DIFFOUT_R45n DIFFOUT_R46n DIFFOUT_R47p DIFFOUT_R48p DIFFOUT_R47n DIFFOUT_R48n DIFFOUT_R49p DIFFOUT_R50p DIFFOUT_R49n DIFFOUT_R50n DIFFOUT_R51p DIFFOUT_R52p AE23 AF16 AD23 AF17 U16 AF23 U15 AE24 AF24 AA18 AE25 Y18 V17 AE26 V18 AD26 AC19 Y19 AB19 Y20 W18 AA21 V19 AB22 AC22 U19 AC23 V20 AA22 W20 AA23 W21 AC24 V22 AB24 U22 Y23 T19 Y24 U20 T21 V23 T22 V24 T23 AA24 T24 AB25 R23 AD25 P23 AC25 R24 U24 R25 V25 R20 AB26 P20 AA26 T26 Y25 R26 Y26 P21 W25 P22 W26 N25 U25 P26 U26 N20 J25 M21 J26 N24 F26 DQ7B DQ7B DQ7B DQ7B DQ2B DQ2B DQ2B DQ2B DQ7B DQ2B DQ7B DQ2B DQ8B DQ8B DQ8B DQSn8B DQ8B DQS8B DQ2B DQ2B DQ2B DQSn2B DQ2B DQS2B DQ8B DQ8B DQ8B DQ8B DQ2B DQ2B DQ2B DQ2B DQ8B DQ2B DQ8B DQ1R DQ2B Pin List DF27 HMC Pin Assignment for DDR3/DDR2 (2) GND B_DQ_28 B_DQ_30 B_DQ_29 GND B_DQ_31 GND B_DM_3 GND B_DQ_32 B_DQ_34 B_DQ_33 B_DQS#_4 B_DQ_35 B_DQS_4 GND GND B_DQ_36 B_DQ_38 B_DQ_37 GND B_DQ_39 GND B_DM_4 HMC Pin Assignment for LPDDR2 GND B_DQ_28 B_DQ_30 B_DQ_29 GND B_DQ_31 GND B_DM_3 GND B_DQ_32 B_DQ_34 B_DQ_33 B_DQS#_4 B_DQ_35 B_DQS_4 GND GND B_DQ_36 B_DQ_38 B_DQ_37 GND B_DQ_39 GND B_DM_4 DQ1R DQ1R DQ1R DQ1R DQ1R DQS1R DQ1R DQSn1R DQ1R DQ1R DQ1R DQ2R DQ2R DQ2R DQ2R DQ2R DQ2R DQS2R DQSn2R DQ2R DQ2R DQ2R DQ2R DQ3R DQ3R DQ3R DQ3R DQ3R DQ3R DQS3R DQSn3R DQ3R DQ3R DQ3R DQ3R DQ4R DQ4R DQ4R DQ4R Page 17 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO GND IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Optional Function(s) FPLL_TR_CLKOUT1,FPLL_TR_CLKOUTn CLK4p,FPLL_TR_FBp CLK4n,FPLL_TR_FBn Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F672 DQS for X8 DIFFIO_RX_R51n DIFFIO_TX_R52n DIFFIO_RX_R53p DIFFIO_TX_R54p DIFFIO_RX_R53n DIFFIO_TX_R54n DIFFIO_RX_R55p DIFFIO_TX_R56p DIFFIO_RX_R55n DIFFIO_TX_R56n DIFFIO_RX_R57p DIFFIO_TX_R58p DIFFIO_RX_R57n DIFFIO_TX_R58n DIFFIO_RX_R59p DIFFIO_TX_R60p DIFFIO_RX_R59n DIFFIO_TX_R60n DIFFIO_RX_R61p DIFFIO_TX_R62p DIFFIO_RX_R61n DIFFIO_TX_R62n DIFFIO_RX_R63p DIFFIO_TX_R64p DIFFIO_RX_R63n DIFFIO_TX_R64n DIFFIO_RX_R73p DIFFIO_TX_R74p DIFFIO_RX_R73n DIFFIO_TX_R74n DIFFIO_RX_R75p DIFFIO_TX_R76p DIFFIO_RX_R75n DIFFIO_TX_R76n DIFFIO_RX_R77p DIFFIO_TX_R78p DIFFIO_RX_R77n DIFFIO_TX_R78n DIFFIO_RX_R79p DIFFIO_TX_R80p DIFFIO_RX_R79n DIFFIO_TX_R80n DIFFOUT_R51n DIFFOUT_R52n DIFFOUT_R53p DIFFOUT_R54p DIFFOUT_R53n DIFFOUT_R54n DIFFOUT_R55p DIFFOUT_R56p DIFFOUT_R55n DIFFOUT_R56n DIFFOUT_R57p DIFFOUT_R58p DIFFOUT_R57n DIFFOUT_R58n DIFFOUT_R59p DIFFOUT_R60p DIFFOUT_R59n DIFFOUT_R60n DIFFOUT_R61p DIFFOUT_R62p DIFFOUT_R61n DIFFOUT_R62n DIFFOUT_R63p DIFFOUT_R64p DIFFOUT_R63n DIFFOUT_R64n DIFFOUT_R73p DIFFOUT_R74p DIFFOUT_R73n DIFFOUT_R74n DIFFOUT_R75p DIFFOUT_R76p DIFFOUT_R75n DIFFOUT_R76n DIFFOUT_R77p DIFFOUT_R78p DIFFOUT_R77n DIFFOUT_R78n DIFFOUT_R79p DIFFOUT_R80p DIFFOUT_R79n DIFFOUT_R80n DQ4R DQ4R DQS4R DIFFIO_RX_T9p DIFFIO_TX_T10p DIFFIO_RX_T9n DIFFIO_TX_T10n DIFFIO_RX_T11p DIFFIO_TX_T12p DIFFIO_RX_T11n DIFFIO_TX_T12n DIFFIO_RX_T13p DIFFIO_TX_T14p DIFFIO_RX_T13n DIFFIO_TX_T14n DIFFIO_RX_T15p DIFFIO_TX_T16p DIFFIO_RX_T15n DIFFIO_TX_T16n DIFFIO_RX_T17p DIFFIO_TX_T18p DIFFIO_RX_T17n DIFFIO_TX_T18n DIFFIO_RX_T19p DIFFIO_TX_T20p DIFFIO_RX_T19n DIFFIO_TX_T20n DIFFIO_RX_T21p DIFFIO_TX_T22p DIFFIO_RX_T21n DIFFIO_TX_T22n DIFFIO_RX_T23p DIFFIO_TX_T24p DIFFIO_RX_T23n DIFFIO_TX_T24n DIFFIO_RX_T25p DIFFIO_TX_T26p DIFFIO_RX_T25n DIFFOUT_T9p DIFFOUT_T10p DIFFOUT_T9n DIFFOUT_T10n DIFFOUT_T11p DIFFOUT_T12p DIFFOUT_T11n DIFFOUT_T12n DIFFOUT_T13p DIFFOUT_T14p DIFFOUT_T13n DIFFOUT_T14n DIFFOUT_T15p DIFFOUT_T16p DIFFOUT_T15n DIFFOUT_T16n DIFFOUT_T17p DIFFOUT_T18p DIFFOUT_T17n DIFFOUT_T18n DIFFOUT_T19p DIFFOUT_T20p DIFFOUT_T19n DIFFOUT_T20n DIFFOUT_T21p DIFFOUT_T22p DIFFOUT_T21n DIFFOUT_T22n DIFFOUT_T23p DIFFOUT_T24p DIFFOUT_T23n DIFFOUT_T24n DIFFOUT_T25p DIFFOUT_T26p DIFFOUT_T25n M24 G26 N23 G25 M22 H25 M25 D26 M26 E26 K25 E24 K26 E25 K24 F24 K23 G24 L23 H23 L24 H24 H22 F23 J23 G22 L22 B25 K21 B26 H19 D25 H20 C25 J20 D22 J21 E23 G20 E21 F21 F22 D23 H15 C23 J16 C22 B24 A23 A24 A22 H18 B22 H17 A21 D21 B21 D20 B20 G16 C20 G17 B19 E20 C19 E19 C18 J12 A19 J11 A18 D18 A17 D17 A16 H14 C17 H13 Pin List DF27 DQS for X16 HMC Pin Assignment for DDR3/DDR2 (2) HMC Pin Assignment for LPDDR2 GND T_DM_4 GND T_DQ_39 T_DQ_37 T_DQ_38 T_DQ_36 GND T_DQS_4 GND T_DQS#_4 T_DQ_35 T_DQ_33 T_DQ_34 T_DQ_32 GND GND T_DM_3 GND T_DQ_31 T_DQ_29 T_DQ_30 T_DQ_28 GND T_DQS_3 GND T_DQS#_3 T_DQ_27 T_DQ_25 T_DQ_26 T_DQ_24 GND GND T_DM_2 GND GND T_DM_4 GND T_DQ_39 T_DQ_37 T_DQ_38 T_DQ_36 GND T_DQS_4 GND T_DQS#_4 T_DQ_35 T_DQ_33 T_DQ_34 T_DQ_32 GND GND T_DM_3 GND T_DQ_31 T_DQ_29 T_DQ_30 T_DQ_28 GND T_DQS_3 GND T_DQS#_3 T_DQ_27 T_DQ_25 T_DQ_26 T_DQ_24 GND GND T_DM_2 GND DQSn4R DQ4R DQ4R DQ4R DQ4R DQ5R DQ5R DQ5R DQ5R DQ5R DQ5R DQS5R DQSn5R DQ5R DQ5R DQ5R DQ5R DQ6R DQ6R DQ6R DQ6R DQ6R DQ6R DQS6R DQSn6R DQ6R DQ6R DQ6R DQ6R DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQS1T DQ1T DQ1T DQ1T DQ1T DQ1T DQS1T DQSn1T DQ1T DQ1T DQ1T DQ1T DQSn1T DQ1T DQ1T DQ1T DQ1T DQ2T DQ1T DQ2T DQ2T DQ2T DQ2T DQ2T DQS2T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQSn2T DQ2T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQ1T DQ1T DQ3T DQ2T Page 18 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 9A VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO MSEL0 PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Optional Function(s) Configuration Function CLK11p CLK11n CLK10p CLK10n RZQ_2 CLK9p CLK9n FPLL_TL_CLKOUT0,FPLL_TL_CLKOUTp,FPLL_TL_FB FPLL_TL_CLKOUT1,FPLL_TL_CLKOUTn CLK8p,FPLL_TL_FBp CLK8n,FPLL_TL_FBn Dedicated Tx/Rx Channel Emulated LVDS Output Channel F672 DQS for X8 DQS for X16 DIFFIO_TX_T26n DIFFIO_RX_T27p DIFFIO_TX_T28p DIFFIO_RX_T27n DIFFIO_TX_T28n DIFFIO_RX_T29p DIFFIO_TX_T30p DIFFIO_RX_T29n DIFFIO_TX_T30n DIFFIO_RX_T31p DIFFIO_TX_T32p DIFFIO_RX_T31n DIFFIO_TX_T32n DIFFIO_RX_T33p DIFFIO_TX_T34p DIFFIO_RX_T33n DIFFIO_TX_T34n DIFFIO_RX_T35p DIFFIO_TX_T36p DIFFIO_RX_T35n DIFFIO_TX_T36n DIFFIO_RX_T37p DIFFIO_TX_T38p DIFFIO_RX_T37n DIFFIO_TX_T38n DIFFIO_RX_T39p DIFFIO_TX_T40p DIFFIO_RX_T39n DIFFIO_TX_T40n DIFFIO_RX_T41p DIFFIO_TX_T42p DIFFIO_RX_T41n DIFFIO_TX_T42n DIFFIO_RX_T43p DIFFIO_TX_T44p DIFFIO_RX_T43n DIFFIO_TX_T44n DIFFIO_RX_T45p DIFFIO_TX_T46p DIFFIO_RX_T45n DIFFIO_TX_T46n DIFFIO_RX_T47p DIFFIO_TX_T48p DIFFIO_RX_T47n DIFFIO_TX_T48n DIFFIO_RX_T49p DIFFIO_TX_T50p DIFFIO_RX_T49n DIFFIO_TX_T50n DIFFIO_RX_T51p DIFFIO_TX_T52p DIFFIO_RX_T51n DIFFIO_TX_T52n DIFFIO_RX_T53p DIFFIO_TX_T54p DIFFIO_RX_T53n DIFFIO_TX_T54n DIFFIO_RX_T55p DIFFIO_TX_T56p DIFFIO_RX_T55n DIFFIO_TX_T56n DIFFIO_RX_T57p DIFFIO_TX_T58p DIFFIO_RX_T57n DIFFIO_TX_T58n DIFFIO_RX_T59p DIFFIO_TX_T60p DIFFIO_RX_T59n DIFFIO_TX_T60n DIFFIO_RX_T61p DIFFIO_TX_T62p DIFFIO_RX_T61n DIFFIO_TX_T62n DIFFIO_RX_T63p DIFFIO_TX_T64p DIFFIO_RX_T63n DIFFIO_TX_T64n DIFFOUT_T26n DIFFOUT_T27p DIFFOUT_T28p DIFFOUT_T27n DIFFOUT_T28n DIFFOUT_T29p DIFFOUT_T30p DIFFOUT_T29n DIFFOUT_T30n DIFFOUT_T31p DIFFOUT_T32p DIFFOUT_T31n DIFFOUT_T32n DIFFOUT_T33p DIFFOUT_T34p DIFFOUT_T33n DIFFOUT_T34n DIFFOUT_T35p DIFFOUT_T36p DIFFOUT_T35n DIFFOUT_T36n DIFFOUT_T37p DIFFOUT_T38p DIFFOUT_T37n DIFFOUT_T38n DIFFOUT_T39p DIFFOUT_T40p DIFFOUT_T39n DIFFOUT_T40n DIFFOUT_T41p DIFFOUT_T42p DIFFOUT_T41n DIFFOUT_T42n DIFFOUT_T43p DIFFOUT_T44p DIFFOUT_T43n DIFFOUT_T44n DIFFOUT_T45p DIFFOUT_T46p DIFFOUT_T45n DIFFOUT_T46n DIFFOUT_T47p DIFFOUT_T48p DIFFOUT_T47n DIFFOUT_T48n DIFFOUT_T49p DIFFOUT_T50p DIFFOUT_T49n DIFFOUT_T50n DIFFOUT_T51p DIFFOUT_T52p DIFFOUT_T51n DIFFOUT_T52n DIFFOUT_T53p DIFFOUT_T54p DIFFOUT_T53n DIFFOUT_T54n DIFFOUT_T55p DIFFOUT_T56p DIFFOUT_T55n DIFFOUT_T56n DIFFOUT_T57p DIFFOUT_T58p DIFFOUT_T57n DIFFOUT_T58n DIFFOUT_T59p DIFFOUT_T60p DIFFOUT_T59n DIFFOUT_T60n DIFFOUT_T61p DIFFOUT_T62p DIFFOUT_T61n DIFFOUT_T62n DIFFOUT_T63p DIFFOUT_T64p DIFFOUT_T63n DIFFOUT_T64n B17 E18 A14 F18 B14 L12 B15 K11 C15 C14 A8 D15 A9 G15 C9 G14 B9 E16 D10 D16 C10 N12 B10 M12 A11 F16 E10 E15 E11 H12 B12 G11 A13 G12 A12 F12 B11 M11 C13 L11 C12 E13 D11 D13 D12 N9 A5 M10 B6 H8 A7 H9 B7 M9 D6 L9 E6 H10 D7 G10 C7 L8 F6 K9 G6 K8 G7 J8 F7 K10 H7 J10 J7 L7 D8 K6 E9 M7 DQ3T DQ3T DQ3T DQ3T DQ3T DQS3T DQ2T DQ2T DQ2T DQ2T DQ2T DQS2T DQSn3T DQ3T DQ3T DQ3T DQ3T DQSn2T DQ2T DQ2T DQ2T DQ2T MSEL0 Pin List DF27 HMC Pin Assignment for DDR3/DDR2 (2) T_DQ_23 T_DQ_21 T_DQ_22 T_DQ_20 GND T_DQS_2 T_RESET# T_DQS#_2 T_DQ_19 T_DQ_17 T_DQ_18 T_DQ_16 GND HMC Pin Assignment for LPDDR2 T_DQ_23 T_DQ_21 T_DQ_22 T_DQ_20 GND T_DQS_2 T_RESET# T_DQS#_2 T_DQ_19 T_DQ_17 T_DQ_18 T_DQ_16 GND DQ4T DQ2T T_DM_1 T_DM_1 DQ4T DQ4T DQ4T DQ4T DQ4T DQS4T DQ2T DQ2T DQ2T DQ2T DQ2T DQ2T DQSn4T DQ4T DQ4T DQ4T DQ4T DQ2T DQ2T DQ2T DQ2T DQ2T T_DQ_15 T_DQ_13 T_DQ_14 T_DQ_12 T_CKE_0 T_DQS_1 T_CKE_1 T_DQS#_1 T_DQ_11 T_DQ_9 T_DQ_10 T_DQ_8 GND T_DQ_15 T_DQ_13 T_DQ_14 T_DQ_12 T_CKE_0 T_DQS_1 T_CKE_1 T_DQS#_1 T_DQ_11 T_DQ_9 T_DQ_10 T_DQ_8 GND DQ5T T_DM_0 T_DM_0 DQ5T DQ5T DQ5T DQ5T DQ5T DQS5T DQSn5T DQ5T DQ5T DQ5T DQ5T T_DQ_7 T_DQ_5 T_DQ_6 T_DQ_4 T_ODT_1 T_DQS_0 T_ODT_0 T_DQS#_0 T_DQ_3 T_DQ_1 T_DQ_2 T_DQ_0 T_DQ_7 T_DQ_5 T_DQ_6 T_DQ_4 T_ODT_1 T_DQS_0 T_ODT_0 T_DQS#_0 T_DQ_3 T_DQ_1 T_DQ_2 T_DQ_0 DQ6T T_A_0 T_CA_0 DQ6T DQ6T DQ6T DQ6T DQ6T DQS6T T_A_1 T_A_4 T_A_2 T_A_5 T_A_3 T_CK T_A_6 T_CK# T_A_7 T_BA_1 T_BA_0 T_BA_2 GND T_CA_1 T_CA_4 T_CA_2 T_CA_5 T_CA_3 T_CK T_CA_6 T_CK# T_CA_7 DQSn6T DQ6T DQ6T DQ6T DQ6T DQ7T T_CAS# DQ7T DQ7T DQ7T DQ7T DQ7T DQS7T T_RAS# T_A_8 T_A_10 T_A_9 T_A_11 T_CS#_0 T_A_12 T_CS#_1 T_A_13 T_A_14 T_WE# T_A_15 GND DQSn7T DQ7T DQ7T DQ7T DQ7T GND T_CA_8 T_CA_9 T_CS#_0 T_CS#_1 GND Page 19 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF 9A 9A 9A 9A 9A 9A 9A 9A 9A PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Pin Name/Function CONF_DONE MSEL1 nSTATUS nCE MSEL2 MSEL3 nCONFIG MSEL4 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function Dedicated Tx/Rx Channel CONF_DONE MSEL1 nSTATUS nCE MSEL2 MSEL3 nCONFIG MSEL4 Emulated LVDS Output Channel F672 DQS for X8 DQS for X16 HMC Pin Assignment for DDR3/DDR2 (2) HMC Pin Assignment for LPDDR2 A6 L6 B5 D5 A2 K5 F5 J5 H5 E7 G5 C11 D14 E17 F20 G23 L25 N21 P24 P19 T20 U23 Y22 AA15 AE17 AD14 M8 A25 D24 H26 V26 AA25 AC26 AF25 K22 AD24 C21 L20 K19 M19 W19 AC21 AF20 B18 L18 K17 J18 N18 M17 R18 P17 AB18 A15 H16 L16 L14 K15 J14 N16 N14 M15 T15 R16 R14 P15 V16 G13 K13 K12 M13 R12 P13 U13 Y12 F10 L10 J9 N11 Pin List DF27 Page 20 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Emulated LVDS Output Channel F672 DQS for X8 DQS for X16 HMC Pin Assignment for DDR3/DDR2 (2) HMC Pin Assignment for LPDDR2 T10 P9 W9 AC11 AF10 B8 H6 N6 R7 P7 AB8 AE7 C5 B4 F4 E5 D4 H4 L4 J4 N4 M5 T5 R4 P5 V5 V4 U4 AA5 Y4 W5 AC5 AB4 AF4 AE5 AD4 C2 C1 B3 B2 F3 E2 E1 D3 H3 G2 G1 L2 L1 K3 J2 J1 N2 N1 M3 T3 R2 R1 P3 V3 U2 U1 AA2 AA1 Y3 W2 W1 AC2 AC1 AB3 AF3 AF2 AE2 AE1 AD3 J19 L19 K20 Pin List DF27 Page 21 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC DNU DNU DNU DNU DNU DNU VCCPGM VCCPGM VCCPGM VCCBAT VCCIO3A VCCIO3A VCCIO3B VCCIO3B VCCIO3B VCCIO3B VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO5A VCCIO5A VCCIO5B VCCIO5B VCCIO5B VCCIO5B VCCIO6A VCCIO6A VCCIO6A VCCIO6A VCCIO6A VCCIO6A VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO8A VCCIO8A VCCIO8A PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Emulated LVDS Output Channel F672 DQS for X8 DQS for X16 HMC Pin Assignment for DDR3/DDR2 (2) HMC Pin Assignment for LPDDR2 N19 M20 R19 L17 K18 J17 N17 M18 T18 R17 P18 L15 K16 K14 J15 N15 M16 M14 T16 T14 R15 P16 P14 L13 J13 N13 R13 A4 A3 AB7 AA12 C24 F14 AA9 W22 F8 E8 Y7 AC6 V11 AA10 AD9 U8 U18 AE22 AA20 AD19 Y17 W14 AC16 AF15 AB13 AE12 V21 AB23 N26 T25 W24 R22 C26 F25 J24 E22 M23 H21 B23 A20 D19 G18 C16 F15 B13 E12 A10 H11 C6 D9 G8 Pin List DF27 Page 22 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number 3A 3B 4A 5A 5B 6A 7A 8A VREF VREFB3AN0 VREFB3BN0 VREFB4AN0 VREFB5AN0 VREFB5BN0 VREFB6AN0 VREFB7AN0 VREFB8AN0 Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel VCCIO8A VCCPD3A VCCPD3B4A VCCPD3B4A VCCPD3B4A VCCPD3B4A VCCPD3B4A VCCPD5A VCCPD5B VCCPD5B VCCPD6A VCCPD6A VCCPD7A8A VCCPD7A8A VCCPD7A8A VCCPD7A8A VCCPD7A8A VREFB3AN0 VREFB3BN0 VREFB4AN0 VREFB5AN0 VREFB5BN0 VREFB6AN0 VREFB7AN0 VREFB8AN0 VCCH_GXBL VCCH_GXBL VCCH_GXBL VCCL_GXBL VCCL_GXBL VCCL_GXBL RREF_TL VCCA_FPLL VCCA_FPLL VCCA_FPLL VCCA_FPLL VCC_AUX VCC_AUX VCC_AUX VCC_AUX VCC_AUX VCC_AUX VCCE_GXBL VCCE_GXBL VCCE_GXBL VCCE_GXBL VCCE_GXBL VCCE_GXBL Emulated LVDS Output Channel F672 DQS for X8 DQS for X16 HMC Pin Assignment for DDR3/DDR2 (2) HMC Pin Assignment for LPDDR2 K7 AB9 AA17 AA11 AA19 AB21 AA13 U21 N22 R21 J22 L21 F19 F17 F13 F11 F9 AC7 AC12 AD15 W23 P25 L26 B16 C8 R3 T4 L3 J3 N3 U3 B1 W7 J6 Y21 G21 G9 E14 G19 AB20 AB14 AA8 U5 K4 N5 M4 R5 P4 Notes: (1) For more information about pin definition and pin connection guidelines, refer to the Cyclone V Device Family Pin Connection Guidelines. (2) RESET pin is only applicable for DDR3 device. PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Pin List DF27 Page 23 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number GXB_L3 GXB_L3 GXB_L3 GXB_L3 GXB_L3 GXB_L3 GXB_L3 GXB_L3 GXB_L3 GXB_L3 GXB_L3 GXB_L3 GXB_L3 GXB_L3 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A VREF Pin Name/Function VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 REFCLK3Ln REFCLK3Lp GXB_TX_L11n GXB_TX_L11p GXB_RX_L11p,GXB_REFCLK_L11p GXB_RX_L11n,GXB_REFCLK_L11n GXB_TX_L10n GXB_TX_L10p GXB_RX_L10p,GXB_REFCLK_L10p GXB_RX_L10n,GXB_REFCLK_L10n GXB_TX_L9n GXB_TX_L9p GXB_RX_L9p,GXB_REFCLK_L9p GXB_RX_L9n,GXB_REFCLK_L9n GXB_TX_L8n GXB_TX_L8p GXB_RX_L8p,GXB_REFCLK_L8p GXB_RX_L8n,GXB_REFCLK_L8n GXB_TX_L7n GXB_TX_L7p GXB_RX_L7p,GXB_REFCLK_L7p GXB_RX_L7n,GXB_REFCLK_L7n GXB_TX_L6n GXB_TX_L6p GXB_RX_L6p,GXB_REFCLK_L6p GXB_RX_L6n,GXB_REFCLK_L6n REFCLK2Lp REFCLK2Ln REFCLK1Ln REFCLK1Lp GXB_TX_L5n GXB_TX_L5p GXB_RX_L5p,GXB_REFCLK_L5p GXB_RX_L5n,GXB_REFCLK_L5n GXB_TX_L4n GXB_TX_L4p GXB_RX_L4p,GXB_REFCLK_L4p GXB_RX_L4n,GXB_REFCLK_L4n GXB_TX_L3n GXB_TX_L3p GXB_RX_L3p,GXB_REFCLK_L3p GXB_RX_L3n,GXB_REFCLK_L3n GXB_TX_L2n GXB_TX_L2p GXB_RX_L2p,GXB_REFCLK_L2p GXB_RX_L2n,GXB_REFCLK_L2n GXB_TX_L1n GXB_TX_L1p GXB_RX_L1p,GXB_REFCLK_L1p GXB_RX_L1n,GXB_REFCLK_L1n GXB_TX_L0n GXB_TX_L0p GXB_RX_L0p,GXB_REFCLK_L0p GXB_RX_L0n,GXB_REFCLK_L0n REFCLK0Lp REFCLK0Ln TDO nCSO TMS AS_DATA3 TCK AS_DATA2 TDI AS_DATA1 DCLK AS_DATA0,ASDO IO IO IO IO IO IO IO IO IO IO IO IO PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Optional Function(s) Configuration Function TDO DATA4 TMS DATA3 TCK DATA2 TDI DATA1 DCLK DATA0 DATA6 DATA5 DATA8 DATA7 DATA10 DATA9 DATA12 DATA11 DATA14 DATA13 CLKUSR DATA15 Dedicated Tx/Rx Channel DIFFIO_RX_B1n DIFFIO_TX_B2n DIFFIO_RX_B1p DIFFIO_TX_B2p DIFFIO_RX_B3n DIFFIO_TX_B4n DIFFIO_RX_B3p DIFFIO_TX_B4p DIFFIO_RX_B5n DIFFIO_TX_B6n DIFFIO_RX_B5p DIFFIO_TX_B6p Pin List EF31 Emulated LVDS Output Channel F896 DIFFOUT_B1n DIFFOUT_B2n DIFFOUT_B1p DIFFOUT_B2p DIFFOUT_B3n DIFFOUT_B4n DIFFOUT_B3p DIFFOUT_B4p DIFFOUT_B5n DIFFOUT_B6n DIFFOUT_B5p DIFFOUT_B6p L7 K8 D3 D4 E2 E1 F3 F4 G2 G1 H3 H4 J2 J1 K3 K4 L2 L1 M3 M4 N2 N1 P3 P4 R2 R1 P8 N7 R7 R8 T3 T4 U2 U1 V3 V4 W2 W1 Y3 Y4 AA2 AA1 AB3 AB4 AC2 AC1 AD3 AD4 AE2 AE1 AF3 AF4 AG2 AG1 W8 W7 W9 AA7 V7 AB7 AC7 AE7 U7 AE5 T7 AG5 U12 AA10 U11 Y10 Y11 AD9 AA11 AC9 R10 W10 T11 V9 DQS for X8 DQS for X16 HMC Pin Assignment for DDR3/DDR2 (2) HMC Pin Assignment for LPDDR2 DQ1B DQ1B DQ1B DQSn1B DQ1B DQS1B DQ1B DQ1B DQ1B DQ1B Page 24 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Optional Function(s) CLK0n,FPLL_BL_FBn CLK0p,FPLL_BL_FBp FPLL_BL_CLKOUT1,FPLL_BL_CLKOUTn FPLL_BL_CLKOUT0,FPLL_BL_CLKOUTp,FPLL_BL_FB CLK1n CLK1p RZQ_0 Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F896 PR_DONE PR_READY PR_ERROR DIFFIO_RX_B7n DIFFIO_TX_B8n DIFFIO_RX_B7p DIFFIO_TX_B8p DIFFIO_TX_B9n DIFFIO_RX_B10n DIFFIO_TX_B9p DIFFIO_RX_B10p DIFFIO_RX_B11n DIFFIO_TX_B12n DIFFIO_RX_B11p DIFFIO_TX_B12p DIFFIO_TX_B13n DIFFIO_RX_B14n DIFFIO_TX_B13p DIFFIO_RX_B14p DIFFIO_RX_B15n DIFFIO_TX_B16n DIFFIO_RX_B15p DIFFIO_TX_B16p DIFFIO_TX_B25n DIFFIO_RX_B26n DIFFIO_TX_B25p DIFFIO_RX_B26p DIFFIO_RX_B27n DIFFIO_TX_B28n DIFFIO_RX_B27p DIFFIO_TX_B28p DIFFIO_TX_B29n DIFFIO_RX_B30n DIFFIO_TX_B29p DIFFIO_RX_B30p DIFFIO_RX_B31n DIFFIO_TX_B32n DIFFIO_RX_B31p DIFFIO_TX_B32p DIFFIO_TX_B33n DIFFIO_RX_B34n DIFFIO_TX_B33p DIFFIO_RX_B34p DIFFIO_RX_B35n DIFFIO_TX_B36n DIFFIO_RX_B35p DIFFIO_TX_B36p DIFFIO_TX_B37n DIFFIO_RX_B38n DIFFIO_TX_B37p DIFFIO_RX_B38p DIFFIO_RX_B39n DIFFIO_TX_B40n DIFFIO_RX_B39p DIFFIO_TX_B40p DIFFIO_TX_B41n DIFFIO_RX_B42n DIFFIO_TX_B41p DIFFIO_RX_B42p DIFFIO_RX_B43n DIFFIO_TX_B44n DIFFIO_RX_B43p DIFFIO_TX_B44p DIFFIO_TX_B45n DIFFIO_RX_B46n DIFFIO_TX_B45p DIFFIO_RX_B46p DIFFIO_RX_B47n DIFFIO_TX_B48n DIFFIO_RX_B47p DIFFIO_TX_B48p DIFFIO_TX_B49n DIFFIO_RX_B50n DIFFIO_TX_B49p DIFFIO_RX_B50p DIFFIO_RX_B51n DIFFIO_TX_B52n DIFFIO_RX_B51p DIFFIO_TX_B52p DIFFIO_TX_B53n DIFFIO_RX_B54n DIFFOUT_B7n DIFFOUT_B8n DIFFOUT_B7p DIFFOUT_B8p DIFFOUT_B9n DIFFOUT_B10n DIFFOUT_B9p DIFFOUT_B10p DIFFOUT_B11n DIFFOUT_B12n DIFFOUT_B11p DIFFOUT_B12p DIFFOUT_B13n DIFFOUT_B14n DIFFOUT_B13p DIFFOUT_B14p DIFFOUT_B15n DIFFOUT_B16n DIFFOUT_B15p DIFFOUT_B16p DIFFOUT_B25n DIFFOUT_B26n DIFFOUT_B25p DIFFOUT_B26p DIFFOUT_B27n DIFFOUT_B28n DIFFOUT_B27p DIFFOUT_B28p DIFFOUT_B29n DIFFOUT_B30n DIFFOUT_B29p DIFFOUT_B30p DIFFOUT_B31n DIFFOUT_B32n DIFFOUT_B31p DIFFOUT_B32p DIFFOUT_B33n DIFFOUT_B34n DIFFOUT_B33p DIFFOUT_B34p DIFFOUT_B35n DIFFOUT_B36n DIFFOUT_B35p DIFFOUT_B36p DIFFOUT_B37n DIFFOUT_B38n DIFFOUT_B37p DIFFOUT_B38p DIFFOUT_B39n DIFFOUT_B40n DIFFOUT_B39p DIFFOUT_B40p DIFFOUT_B41n DIFFOUT_B42n DIFFOUT_B41p DIFFOUT_B42p DIFFOUT_B43n DIFFOUT_B44n DIFFOUT_B43p DIFFOUT_B44p DIFFOUT_B45n DIFFOUT_B46n DIFFOUT_B45p DIFFOUT_B46p DIFFOUT_B47n DIFFOUT_B48n DIFFOUT_B47p DIFFOUT_B48p DIFFOUT_B49n DIFFOUT_B50n DIFFOUT_B49p DIFFOUT_B50p DIFFOUT_B51n DIFFOUT_B52n DIFFOUT_B51p DIFFOUT_B52p DIFFOUT_B53n DIFFOUT_B54n V10 AF6 V11 AF7 AB9 AH6 AA9 AG6 U8 AG8 T9 AF8 AB8 AH5 AA8 AH4 U9 AH7 T10 AG7 AF10 AD13 AE10 AD12 W12 AJ2 V12 AJ1 AK3 AE13 AJ3 AE12 AB13 AJ5 AB12 AJ4 AK6 AG12 AK5 AF13 AA13 AK7 Y12 AJ7 AK8 AG11 AJ8 AF11 AC14 AG9 AB14 AF9 AJ9 AJ10 AH9 AH10 AA14 AK11 Y13 AK10 AH12 AG14 AH11 AG13 AA15 AK12 Y15 AJ12 AK13 AF15 AJ14 AE16 AA16 AH15 Y16 AH14 AK15 AE17 Pin List EF31 DQS for X8 DQS for X16 HMC Pin Assignment for DDR3/DDR2 (2) HMC Pin Assignment for LPDDR2 GND DQ1B DQ1B DQ2B DQ2B DQ2B DQSn2B DQ2B DQS2B DQ2B DQ2B DQ2B DQ2B DQ2B DQ2B DQ3B DQ3B DQ3B DQSn3B DQ3B DQS3B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ3B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DQ1B DQ3B DQ1B DQ3B DQ1B DQ4B DQ4B DQ4B DQSn4B DQ4B DQS4B DQ1B DQ1B DQ1B DQSn1B DQ1B DQS1B DQ4B DQ4B DQ4B DQ4B DQ1B DQ1B DQ1B DQ1B GND B_A_15 B_WE# B_A_14 B_CS#_1 B_A_13 B_CS#_0 B_A_12 B_A_11 B_A_9 B_A_10 B_A_8 DQ4B DQ1B B_RAS# DQ4B DQ1B DQ5B DQ5B DQ5B DQ5B B_CAS# GND B_BA_2 B_BA_0 B_BA_1 B_CK# B_A_7 B_CK B_A_6 B_A_3 B_A_5 B_A_2 B_A_4 B_CK# B_CA_7 B_CK B_CA_6 B_CA_3 B_CA_5 B_CA_2 B_CA_4 DQ5B B_A_1 B_CA_1 DQ5B B_A_0 B_CA_0 DQ6B DQ6B DQ6B DQSn6B DQ6B DQS6B B_DQ_0 B_DQ_2 B_DQ_1 B_DQS#_0 B_DQ_3 B_DQS_0 B_ODT_0 B_ODT_1 B_DQ_4 B_DQ_0 B_DQ_2 B_DQ_1 B_DQS#_0 B_DQ_3 B_DQS_0 B_ODT_0 B_ODT_1 B_DQ_4 DQ5B DQ5B DQ5B DQSn5B DQ5B DQS5B DQ6B DQ6B B_CS#_1 B_CS#_0 B_CA_9 B_CA_8 GND Page 25 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 5A 5A 5A 5A 5A 5A 5A 5A VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Optional Function(s) Configuration Function CLK2n CLK2p CLK3n CLK3p RZQ_1 INIT_DONE PR_REQUEST CRC_ERROR nCEO CvP_CONFDONE Dedicated Tx/Rx Channel Emulated LVDS Output Channel F896 DQS for X8 DIFFIO_TX_B53p DIFFIO_RX_B54p DIFFIO_RX_B55n DIFFIO_TX_B56n DIFFIO_RX_B55p DIFFIO_TX_B56p DIFFIO_TX_B57n DIFFIO_RX_B58n DIFFIO_TX_B57p DIFFIO_RX_B58p DIFFIO_RX_B59n DIFFIO_TX_B60n DIFFIO_RX_B59p DIFFIO_TX_B60p DIFFIO_TX_B61n DIFFIO_RX_B62n DIFFIO_TX_B61p DIFFIO_RX_B62p DIFFIO_RX_B63n DIFFIO_TX_B64n DIFFIO_RX_B63p DIFFIO_TX_B64p DIFFIO_TX_B65n DIFFIO_RX_B66n DIFFIO_TX_B65p DIFFIO_RX_B66p DIFFIO_RX_B67n DIFFIO_TX_B68n DIFFIO_RX_B67p DIFFIO_TX_B68p DIFFIO_TX_B69n DIFFIO_RX_B70n DIFFIO_TX_B69p DIFFIO_RX_B70p DIFFIO_RX_B71n DIFFIO_TX_B72n DIFFIO_RX_B71p DIFFIO_TX_B72p DIFFIO_TX_B73n DIFFIO_RX_B74n DIFFIO_TX_B73p DIFFIO_RX_B74p DIFFIO_RX_B75n DIFFIO_TX_B76n DIFFIO_RX_B75p DIFFIO_TX_B76p DIFFIO_TX_B77n DIFFIO_RX_B78n DIFFIO_TX_B77p DIFFIO_RX_B78p DIFFIO_RX_B79n DIFFIO_TX_B80n DIFFIO_RX_B79p DIFFIO_TX_B80p DIFFIO_TX_B81n DIFFIO_RX_B82n DIFFIO_TX_B81p DIFFIO_RX_B82p DIFFIO_RX_B83n DIFFIO_TX_B84n DIFFIO_RX_B83p DIFFIO_TX_B84p DIFFIO_TX_B85n DIFFIO_RX_B86n DIFFIO_TX_B85p DIFFIO_RX_B86p DIFFIO_RX_B87n DIFFIO_TX_B88n DIFFIO_RX_B87p DIFFIO_TX_B88p DIFFIO_TX_R1p DIFFIO_RX_R2p DIFFIO_TX_R1n DIFFIO_RX_R2n DIFFIO_TX_R3p DIFFIO_RX_R4p DIFFIO_TX_R3n DIFFIO_RX_R4n DIFFOUT_B53p DIFFOUT_B54p DIFFOUT_B55n DIFFOUT_B56n DIFFOUT_B55p DIFFOUT_B56p DIFFOUT_B57n DIFFOUT_B58n DIFFOUT_B57p DIFFOUT_B58p DIFFOUT_B59n DIFFOUT_B60n DIFFOUT_B59p DIFFOUT_B60p DIFFOUT_B61n DIFFOUT_B62n DIFFOUT_B61p DIFFOUT_B62p DIFFOUT_B63n DIFFOUT_B64n DIFFOUT_B63p DIFFOUT_B64p DIFFOUT_B65n DIFFOUT_B66n DIFFOUT_B65p DIFFOUT_B66p DIFFOUT_B67n DIFFOUT_B68n DIFFOUT_B67p DIFFOUT_B68p DIFFOUT_B69n DIFFOUT_B70n DIFFOUT_B69p DIFFOUT_B70p DIFFOUT_B71n DIFFOUT_B72n DIFFOUT_B71p DIFFOUT_B72p DIFFOUT_B73n DIFFOUT_B74n DIFFOUT_B73p DIFFOUT_B74p DIFFOUT_B75n DIFFOUT_B76n DIFFOUT_B75p DIFFOUT_B76p DIFFOUT_B77n DIFFOUT_B78n DIFFOUT_B77p DIFFOUT_B78p DIFFOUT_B79n DIFFOUT_B80n DIFFOUT_B79p DIFFOUT_B80p DIFFOUT_B81n DIFFOUT_B82n DIFFOUT_B81p DIFFOUT_B82p DIFFOUT_B83n DIFFOUT_B84n DIFFOUT_B83p DIFFOUT_B84p DIFFOUT_B85n DIFFOUT_B86n DIFFOUT_B85p DIFFOUT_B86p DIFFOUT_B87n DIFFOUT_B88n DIFFOUT_B87p DIFFOUT_B88p DIFFOUT_R1p DIFFOUT_R2p DIFFOUT_R1n DIFFOUT_R2n DIFFOUT_R3p DIFFOUT_R4p DIFFOUT_R3n DIFFOUT_R4n AJ15 AD17 AC15 AF14 AB16 AE15 AH17 AK17 AG17 AK16 Y18 AJ18 Y17 AJ17 AK18 AG16 AJ19 AF16 AB18 AH20 AB17 AH19 AK20 AE18 AJ20 AD18 AA20 AK22 Y20 AK21 AJ22 AF19 AH21 AF18 AA19 AK23 AA18 AJ23 AJ24 AG19 AH24 AG18 AC19 AK25 AB19 AJ25 AH25 AE20 AG24 AD19 AB21 AK26 AA21 AJ27 AK28 AG21 AK27 AF20 AD20 AH26 AC21 AG26 AF23 AG22 AE22 AF21 AC22 AH22 AB22 AG23 AD23 W22 AC24 Y21 AD24 Y25 AD25 Y26 Pin List EF31 DQS for X16 DQ6B DQ6B HMC Pin Assignment for DDR3/DDR2 (2) B_DQ_6 B_DQ_5 HMC Pin Assignment for LPDDR2 B_DQ_6 B_DQ_5 DQ6B B_DQ_7 B_DQ_7 DQ6B B_DM_0 GND B_DQ_8 B_DQ_10 B_DQ_9 B_DQS#_1 B_DQ_11 B_DQS_1 B_CKE_1 B_CKE_0 B_DQ_12 B_DQ_14 B_DQ_13 DQ7B DQ7B DQ7B DQSn7B DQ7B DQS7B DQ2B DQ2B DQ2B DQ2B DQ2B DQ2B DQ7B DQ7B DQ7B DQ7B DQ2B DQ2B DQ2B DQ2B B_DM_0 GND B_DQ_8 B_DQ_10 B_DQ_9 B_DQS#_1 B_DQ_11 B_DQS_1 B_CKE_1 B_CKE_0 B_DQ_12 B_DQ_14 B_DQ_13 DQ7B DQ2B B_DQ_15 B_DQ_15 DQ7B DQ2B DQ8B DQ8B DQ8B DQSn8B DQ8B DQS8B DQ2B DQ2B DQ2B DQSn2B DQ2B DQS2B DQ8B DQ8B DQ8B DQ8B DQ2B DQ2B DQ2B DQ2B DQ8B DQ2B DQ8B DQ2B DQ9B DQ9B DQ9B DQSn9B DQ9B DQS9B DQ3B DQ3B DQ3B DQ3B DQ3B DQ3B DQ9B DQ9B DQ9B DQ9B DQ3B DQ3B DQ3B DQ3B DQ9B DQ3B DQ9B DQ3B DQ10B DQ10B DQ10B DQSn10B DQ10B DQS10B DQ3B DQ3B DQ3B DQSn3B DQ3B DQS3B DQ10B DQ10B DQ10B DQ10B DQ3B DQ3B DQ3B DQ3B DQ10B DQ3B DQ10B DQ1R DQ3B B_DM_1 GND B_DQ_16 B_DQ_18 B_DQ_17 B_DQS#_2 B_DQ_19 B_DQS_2 B_RESET# GND B_DQ_20 B_DQ_22 B_DQ_21 GND B_DQ_23 GND B_DM_2 GND B_DQ_24 B_DQ_26 B_DQ_25 B_DQS#_3 B_DQ_27 B_DQS_3 GND GND B_DQ_28 B_DQ_30 B_DQ_29 GND B_DQ_31 GND B_DM_3 GND B_DQ_32 B_DQ_34 B_DQ_33 B_DQS#_4 B_DQ_35 B_DQS_4 GND GND B_DQ_36 B_DQ_38 B_DQ_37 GND B_DQ_39 GND B_DM_4 B_DM_1 GND B_DQ_16 B_DQ_18 B_DQ_17 B_DQS#_2 B_DQ_19 B_DQS_2 B_RESET# GND B_DQ_20 B_DQ_22 B_DQ_21 GND B_DQ_23 GND B_DM_2 GND B_DQ_24 B_DQ_26 B_DQ_25 B_DQS#_3 B_DQ_27 B_DQS_3 GND GND B_DQ_28 B_DQ_30 B_DQ_29 GND B_DQ_31 GND B_DM_3 GND B_DQ_32 B_DQ_34 B_DQ_33 B_DQS#_4 B_DQ_35 B_DQS_4 GND GND B_DQ_36 B_DQ_38 B_DQ_37 GND B_DQ_39 GND B_DM_4 DQ1R DQ1R DQ1R DQ1R DQ1R Page 26 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 6A 6A 6A 6A 6A 6A VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Optional Function(s) CLK7p,FPLL_BR_FBp CLK7n,FPLL_BR_FBn CLK6p CLK6n FPLL_BR_CLKOUT0,FPLL_BR_CLKOUTp,FPLL_BR_FB FPLL_BR_CLKOUT1,FPLL_BR_CLKOUTn CLK5p CLK5n FPLL_TR_CLKOUT0,FPLL_TR_CLKOUTp,FPLL_TR_FB Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F896 DEV_OE nPERSTL0 DEV_CLRn nPERSTL1 DIFFIO_TX_R5p DIFFIO_RX_R6p DIFFIO_TX_R5n DIFFIO_RX_R6n DIFFIO_TX_R7p DIFFIO_RX_R8p DIFFIO_TX_R7n DIFFIO_RX_R8n DIFFIO_RX_R17p DIFFIO_TX_R18p DIFFIO_RX_R17n DIFFIO_TX_R18n DIFFIO_RX_R19p DIFFIO_TX_R20p DIFFIO_RX_R19n DIFFIO_TX_R20n DIFFIO_RX_R21p DIFFIO_TX_R22p DIFFIO_RX_R21n DIFFIO_TX_R22n DIFFIO_RX_R23p DIFFIO_TX_R24p DIFFIO_RX_R23n DIFFIO_TX_R24n DIFFIO_RX_R25p DIFFIO_TX_R26p DIFFIO_RX_R25n DIFFIO_TX_R26n DIFFIO_RX_R27p DIFFIO_TX_R28p DIFFIO_RX_R27n DIFFIO_TX_R28n DIFFIO_RX_R29p DIFFIO_TX_R30p DIFFIO_RX_R29n DIFFIO_TX_R30n DIFFIO_RX_R31p DIFFIO_TX_R32p DIFFIO_RX_R31n DIFFIO_TX_R32n DIFFIO_RX_R33p DIFFIO_TX_R34p DIFFIO_RX_R33n DIFFIO_TX_R34n DIFFIO_RX_R35p DIFFIO_TX_R36p DIFFIO_RX_R35n DIFFIO_TX_R36n DIFFIO_RX_R37p DIFFIO_TX_R38p DIFFIO_RX_R37n DIFFIO_TX_R38n DIFFIO_RX_R39p DIFFIO_TX_R40p DIFFIO_RX_R39n DIFFIO_TX_R40n DIFFIO_RX_R41p DIFFIO_TX_R42p DIFFIO_RX_R41n DIFFIO_TX_R42n DIFFIO_RX_R43p DIFFIO_TX_R44p DIFFIO_RX_R43n DIFFIO_TX_R44n DIFFIO_RX_R45p DIFFIO_TX_R46p DIFFIO_RX_R45n DIFFIO_TX_R46n DIFFIO_RX_R47p DIFFIO_TX_R48p DIFFIO_RX_R47n DIFFIO_TX_R48n DIFFIO_RX_R49p DIFFIO_TX_R50p DIFFIO_RX_R49n DIFFIO_TX_R50n DIFFIO_RX_R51p DIFFIO_TX_R52p DIFFOUT_R5p DIFFOUT_R6p DIFFOUT_R5n DIFFOUT_R6n DIFFOUT_R7p DIFFOUT_R8p DIFFOUT_R7n DIFFOUT_R8n DIFFOUT_R17p DIFFOUT_R18p DIFFOUT_R17n DIFFOUT_R18n DIFFOUT_R19p DIFFOUT_R20p DIFFOUT_R19n DIFFOUT_R20n DIFFOUT_R21p DIFFOUT_R22p DIFFOUT_R21n DIFFOUT_R22n DIFFOUT_R23p DIFFOUT_R24p DIFFOUT_R23n DIFFOUT_R24n DIFFOUT_R25p DIFFOUT_R26p DIFFOUT_R25n DIFFOUT_R26n DIFFOUT_R27p DIFFOUT_R28p DIFFOUT_R27n DIFFOUT_R28n DIFFOUT_R29p DIFFOUT_R30p DIFFOUT_R29n DIFFOUT_R30n DIFFOUT_R31p DIFFOUT_R32p DIFFOUT_R31n DIFFOUT_R32n DIFFOUT_R33p DIFFOUT_R34p DIFFOUT_R33n DIFFOUT_R34n DIFFOUT_R35p DIFFOUT_R36p DIFFOUT_R35n DIFFOUT_R36n DIFFOUT_R37p DIFFOUT_R38p DIFFOUT_R37n DIFFOUT_R38n DIFFOUT_R39p DIFFOUT_R40p DIFFOUT_R39n DIFFOUT_R40n DIFFOUT_R41p DIFFOUT_R42p DIFFOUT_R41n DIFFOUT_R42n DIFFOUT_R43p DIFFOUT_R44p DIFFOUT_R43n DIFFOUT_R44n DIFFOUT_R45p DIFFOUT_R46p DIFFOUT_R45n DIFFOUT_R46n DIFFOUT_R47p DIFFOUT_R48p DIFFOUT_R47n DIFFOUT_R48n DIFFOUT_R49p DIFFOUT_R50p DIFFOUT_R49n DIFFOUT_R50n DIFFOUT_R51p DIFFOUT_R52p AB26 Y23 AA26 W24 AC26 Y22 AC27 AA23 AA24 AE23 AA25 AF24 AE27 AE25 AD27 AE26 V21 AF25 V22 AF26 Y27 AH27 W27 AG27 V24 AJ28 V25 AJ29 AA28 AH29 Y28 AG29 V26 AJ30 U26 AH30 AE30 AG28 AD30 AF28 U21 AF29 U22 AF30 V27 AE28 W28 AD28 U27 AD29 U28 AC29 AA29 AB27 AA30 AB28 U23 AB29 T24 AC30 T28 Y30 T29 W30 T25 V29 R26 W29 T30 U29 R30 V30 T23 P28 R23 N29 P29 M29 Pin List EF31 DQS for X8 DQS for X16 HMC Pin Assignment for DDR3/DDR2 (2) HMC Pin Assignment for LPDDR2 DQS1R DQ1R DQSn1R DQ1R DQ1R DQ1R DQ2R DQ2R DQ2R DQ2R DQ2R DQ2R DQS2R DQSn2R DQ2R DQ2R DQ2R DQ2R DQ3R DQ1R DQ3R DQ3R DQ3R DQ3R DQ3R DQS3R DQ1R DQ1R DQ1R DQ1R DQ1R DQS1R DQSn3R DQ3R DQ3R DQ3R DQ3R DQSn1R DQ1R DQ1R DQ1R DQ1R DQ4R DQ1R DQ4R DQ4R DQ4R DQ4R DQ4R DQS4R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQSn4R DQ4R DQ4R DQ4R DQ4R DQ1R DQ1R DQ1R DQ1R DQ1R DQ5R DQ5R DQ5R DQ5R DQ5R DQ5R DQS5R DQSn5R DQ5R DQ5R DQ5R DQ5R DQ6R DQ6R DQ6R DQ6R Page 27 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 7A 7A 7A 7A VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO GND IO IO IO VREFB7AN0 VREFB7AN0 VREFB7AN0 PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Optional Function(s) FPLL_TR_CLKOUT1,FPLL_TR_CLKOUTn CLK4p,FPLL_TR_FBp CLK4n,FPLL_TR_FBn Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F896 DQS for X8 DIFFIO_RX_R51n DIFFIO_TX_R52n DIFFIO_RX_R53p DIFFIO_TX_R54p DIFFIO_RX_R53n DIFFIO_TX_R54n DIFFIO_RX_R55p DIFFIO_TX_R56p DIFFIO_RX_R55n DIFFIO_TX_R56n DIFFIO_RX_R57p DIFFIO_TX_R58p DIFFIO_RX_R57n DIFFIO_TX_R58n DIFFIO_RX_R59p DIFFIO_TX_R60p DIFFIO_RX_R59n DIFFIO_TX_R60n DIFFIO_RX_R61p DIFFIO_TX_R62p DIFFIO_RX_R61n DIFFIO_TX_R62n DIFFIO_RX_R63p DIFFIO_TX_R64p DIFFIO_RX_R63n DIFFIO_TX_R64n DIFFIO_RX_R65p DIFFIO_TX_R66p DIFFIO_RX_R65n DIFFIO_TX_R66n DIFFIO_RX_R67p DIFFIO_TX_R68p DIFFIO_RX_R67n DIFFIO_TX_R68n DIFFIO_RX_R69p DIFFIO_TX_R70p DIFFIO_RX_R69n DIFFIO_TX_R70n DIFFIO_RX_R71p DIFFIO_TX_R72p DIFFIO_RX_R71n DIFFIO_TX_R72n DIFFIO_RX_R73p DIFFIO_TX_R74p DIFFIO_RX_R73n DIFFIO_TX_R74n DIFFIO_RX_R75p DIFFIO_TX_R76p DIFFIO_RX_R75n DIFFIO_TX_R76n DIFFIO_RX_R77p DIFFIO_TX_R78p DIFFIO_RX_R77n DIFFIO_TX_R78n DIFFIO_RX_R79p DIFFIO_TX_R80p DIFFIO_RX_R79n DIFFIO_TX_R80n DIFFIO_RX_R81p DIFFIO_TX_R82p DIFFIO_RX_R81n DIFFIO_TX_R82n DIFFIO_RX_R83p DIFFIO_TX_R84p DIFFIO_RX_R83n DIFFIO_TX_R84n DIFFIO_RX_R85p DIFFIO_TX_R86p DIFFIO_RX_R85n DIFFIO_TX_R86n DIFFIO_RX_R87p DIFFIO_TX_R88p DIFFIO_RX_R87n DIFFIO_TX_R88n DIFFOUT_R51n DIFFOUT_R52n DIFFOUT_R53p DIFFOUT_R54p DIFFOUT_R53n DIFFOUT_R54n DIFFOUT_R55p DIFFOUT_R56p DIFFOUT_R55n DIFFOUT_R56n DIFFOUT_R57p DIFFOUT_R58p DIFFOUT_R57n DIFFOUT_R58n DIFFOUT_R59p DIFFOUT_R60p DIFFOUT_R59n DIFFOUT_R60n DIFFOUT_R61p DIFFOUT_R62p DIFFOUT_R61n DIFFOUT_R62n DIFFOUT_R63p DIFFOUT_R64p DIFFOUT_R63n DIFFOUT_R64n DIFFOUT_R65p DIFFOUT_R66p DIFFOUT_R65n DIFFOUT_R66n DIFFOUT_R67p DIFFOUT_R68p DIFFOUT_R67n DIFFOUT_R68n DIFFOUT_R69p DIFFOUT_R70p DIFFOUT_R69n DIFFOUT_R70n DIFFOUT_R71p DIFFOUT_R72p DIFFOUT_R71n DIFFOUT_R72n DIFFOUT_R73p DIFFOUT_R74p DIFFOUT_R73n DIFFOUT_R74n DIFFOUT_R75p DIFFOUT_R76p DIFFOUT_R75n DIFFOUT_R76n DIFFOUT_R77p DIFFOUT_R78p DIFFOUT_R77n DIFFOUT_R78n DIFFOUT_R79p DIFFOUT_R80p DIFFOUT_R79n DIFFOUT_R80n DIFFOUT_R81p DIFFOUT_R82p DIFFOUT_R81n DIFFOUT_R82n DIFFOUT_R83p DIFFOUT_R84p DIFFOUT_R83n DIFFOUT_R84n DIFFOUT_R85p DIFFOUT_R86p DIFFOUT_R85n DIFFOUT_R86n DIFFOUT_R87p DIFFOUT_R88p DIFFOUT_R87n DIFFOUT_R88n DQ6R DQ6R DQS6R DIFFIO_RX_T9p DIFFIO_TX_T10p DIFFIO_RX_T9n DIFFOUT_T9p DIFFOUT_T10p DIFFOUT_T9n P30 N30 P25 L28 R25 K28 R27 M27 R28 M28 P22 K25 P23 K26 N26 L29 N27 L30 N24 K30 N25 J30 L25 G27 L26 G28 R21 J28 R22 J29 K27 H29 J27 H30 N22 H27 M23 G26 F25 F30 F26 E30 R20 G29 T21 F29 L23 D30 L24 C30 N21 F28 M22 E28 K21 C29 K22 B29 M21 B28 L21 A29 H25 D28 H26 D29 P20 E27 N20 D27 J22 H24 J23 J25 G24 H21 E26 G21 Pin List EF31 DQS for X16 HMC Pin Assignment for DDR3/DDR2 (2) HMC Pin Assignment for LPDDR2 GND T_DM_4 GND GND T_DM_4 GND DQSn6R DQ6R DQ6R DQ6R DQ6R DQ7R DQ2R DQ7R DQ7R DQ7R DQ7R DQ7R DQS7R DQ2R DQ2R DQ2R DQ2R DQ2R DQS2R DQSn7R DQ7R DQ7R DQ7R DQ7R DQSn2R DQ2R DQ2R DQ2R DQ2R DQ8R DQ2R DQ8R DQ8R DQ8R DQ8R DQ8R DQS8R DQ2R DQ2R DQ2R DQ2R DQ2R DQ2R DQSn8R DQ8R DQ8R DQ8R DQ8R DQ2R DQ2R DQ2R DQ2R DQ2R DQ9R DQ3R DQ9R DQ9R DQ9R DQ9R DQ9R DQS9R DQ3R DQ3R DQ3R DQ3R DQ3R DQS3R DQSn9R DQ9R DQ9R DQ9R DQ9R DQSn3R DQ3R DQ3R DQ3R DQ3R DQ10R DQ3R DQ10R DQ10R DQ10R DQ10R DQ10R DQS10R DQ3R DQ3R DQ3R DQ3R DQ3R DQ3R DQSn10R DQ10R DQ10R DQ10R DQ10R DQ3R DQ3R DQ3R DQ3R DQ3R DQ1T DQ1T Page 28 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 8A VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB8AN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Optional Function(s) CLK11p CLK11n CLK10p CLK10n RZQ_2 CLK9p Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F896 DQS for X8 DQS for X16 DIFFIO_TX_T10n DIFFIO_RX_T11p DIFFIO_TX_T12p DIFFIO_RX_T11n DIFFIO_TX_T12n DIFFIO_RX_T13p DIFFIO_TX_T14p DIFFIO_RX_T13n DIFFIO_TX_T14n DIFFIO_RX_T15p DIFFIO_TX_T16p DIFFIO_RX_T15n DIFFIO_TX_T16n DIFFIO_RX_T17p DIFFIO_TX_T18p DIFFIO_RX_T17n DIFFIO_TX_T18n DIFFIO_RX_T19p DIFFIO_TX_T20p DIFFIO_RX_T19n DIFFIO_TX_T20n DIFFIO_RX_T21p DIFFIO_TX_T22p DIFFIO_RX_T21n DIFFIO_TX_T22n DIFFIO_RX_T23p DIFFIO_TX_T24p DIFFIO_RX_T23n DIFFIO_TX_T24n DIFFIO_RX_T25p DIFFIO_TX_T26p DIFFIO_RX_T25n DIFFIO_TX_T26n DIFFIO_RX_T27p DIFFIO_TX_T28p DIFFIO_RX_T27n DIFFIO_TX_T28n DIFFIO_RX_T29p DIFFIO_TX_T30p DIFFIO_RX_T29n DIFFIO_TX_T30n DIFFIO_RX_T31p DIFFIO_TX_T32p DIFFIO_RX_T31n DIFFIO_TX_T32n DIFFIO_RX_T33p DIFFIO_TX_T34p DIFFIO_RX_T33n DIFFIO_TX_T34n DIFFIO_RX_T35p DIFFIO_TX_T36p DIFFIO_RX_T35n DIFFIO_TX_T36n DIFFIO_RX_T37p DIFFIO_TX_T38p DIFFIO_RX_T37n DIFFIO_TX_T38n DIFFIO_RX_T39p DIFFIO_TX_T40p DIFFIO_RX_T39n DIFFIO_TX_T40n DIFFIO_RX_T41p DIFFIO_TX_T42p DIFFIO_RX_T41n DIFFIO_TX_T42n DIFFIO_RX_T43p DIFFIO_TX_T44p DIFFIO_RX_T43n DIFFIO_TX_T44n DIFFIO_RX_T45p DIFFIO_TX_T46p DIFFIO_RX_T45n DIFFIO_TX_T46n DIFFIO_RX_T47p DIFFIO_TX_T48p DIFFIO_RX_T47n DIFFIO_TX_T48n DIFFIO_RX_T49p DIFFOUT_T10n DIFFOUT_T11p DIFFOUT_T12p DIFFOUT_T11n DIFFOUT_T12n DIFFOUT_T13p DIFFOUT_T14p DIFFOUT_T13n DIFFOUT_T14n DIFFOUT_T15p DIFFOUT_T16p DIFFOUT_T15n DIFFOUT_T16n DIFFOUT_T17p DIFFOUT_T18p DIFFOUT_T17n DIFFOUT_T18n DIFFOUT_T19p DIFFOUT_T20p DIFFOUT_T19n DIFFOUT_T20n DIFFOUT_T21p DIFFOUT_T22p DIFFOUT_T21n DIFFOUT_T22n DIFFOUT_T23p DIFFOUT_T24p DIFFOUT_T23n DIFFOUT_T24n DIFFOUT_T25p DIFFOUT_T26p DIFFOUT_T25n DIFFOUT_T26n DIFFOUT_T27p DIFFOUT_T28p DIFFOUT_T27n DIFFOUT_T28n DIFFOUT_T29p DIFFOUT_T30p DIFFOUT_T29n DIFFOUT_T30n DIFFOUT_T31p DIFFOUT_T32p DIFFOUT_T31n DIFFOUT_T32n DIFFOUT_T33p DIFFOUT_T34p DIFFOUT_T33n DIFFOUT_T34n DIFFOUT_T35p DIFFOUT_T36p DIFFOUT_T35n DIFFOUT_T36n DIFFOUT_T37p DIFFOUT_T38p DIFFOUT_T37n DIFFOUT_T38n DIFFOUT_T39p DIFFOUT_T40p DIFFOUT_T39n DIFFOUT_T40n DIFFOUT_T41p DIFFOUT_T42p DIFFOUT_T41n DIFFOUT_T42n DIFFOUT_T43p DIFFOUT_T44p DIFFOUT_T43n DIFFOUT_T44n DIFFOUT_T45p DIFFOUT_T46p DIFFOUT_T45n DIFFOUT_T46n DIFFOUT_T47p DIFFOUT_T48p DIFFOUT_T47n DIFFOUT_T48n DIFFOUT_T49p E25 G22 C27 G23 C26 L20 B27 L19 A28 E22 B26 E21 A26 J20 D25 H20 C25 C21 D23 C20 C22 K20 E23 J19 D22 D20 A25 C19 A24 F20 C24 E20 B24 F19 B23 E18 A23 L18 B22 K18 B21 D19 A21 D18 A20 H19 B19 J18 A19 G18 B18 F18 A18 K16 D14 L16 C14 C17 A16 B17 A15 H17 B14 G17 A14 E17 D12 D17 C12 K17 B13 J17 A13 C16 C11 C15 B12 L15 DQ1T DQ1T DQ1T DQ1T DQ1T DQS1T DQ1T DQ1T DQ1T DQ1T DQ1T DQS1T DQSn1T DQ1T DQ1T DQ1T DQ1T DQSn1T DQ1T DQ1T DQ1T DQ1T Pin List EF31 HMC Pin Assignment for DDR3/DDR2 (2) T_DQ_39 T_DQ_37 T_DQ_38 T_DQ_36 GND T_DQS_4 GND T_DQS#_4 T_DQ_35 T_DQ_33 T_DQ_34 T_DQ_32 GND GND T_DM_3 GND T_DQ_31 T_DQ_29 T_DQ_30 T_DQ_28 GND T_DQS_3 GND T_DQS#_3 T_DQ_27 T_DQ_25 T_DQ_26 T_DQ_24 GND GND T_DM_2 GND T_DQ_23 T_DQ_21 T_DQ_22 T_DQ_20 GND T_DQS_2 T_RESET# T_DQS#_2 T_DQ_19 T_DQ_17 T_DQ_18 T_DQ_16 GND HMC Pin Assignment for LPDDR2 T_DQ_39 T_DQ_37 T_DQ_38 T_DQ_36 GND T_DQS_4 GND T_DQS#_4 T_DQ_35 T_DQ_33 T_DQ_34 T_DQ_32 GND GND T_DM_3 GND T_DQ_31 T_DQ_29 T_DQ_30 T_DQ_28 GND T_DQS_3 GND T_DQS#_3 T_DQ_27 T_DQ_25 T_DQ_26 T_DQ_24 GND GND T_DM_2 GND T_DQ_23 T_DQ_21 T_DQ_22 T_DQ_20 GND T_DQS_2 T_RESET# T_DQS#_2 T_DQ_19 T_DQ_17 T_DQ_18 T_DQ_16 GND DQ2T DQ1T DQ2T DQ2T DQ2T DQ2T DQ2T DQS2T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQSn2T DQ2T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQ1T DQ1T DQ3T DQ2T DQ3T DQ3T DQ3T DQ3T DQ3T DQS3T DQ2T DQ2T DQ2T DQ2T DQ2T DQS2T DQSn3T DQ3T DQ3T DQ3T DQ3T DQSn2T DQ2T DQ2T DQ2T DQ2T DQ4T DQ2T T_DM_1 T_DM_1 DQ4T DQ4T DQ4T DQ4T DQ4T DQS4T DQ2T DQ2T DQ2T DQ2T DQ2T DQ2T DQSn4T DQ4T DQ4T DQ4T DQ4T DQ2T DQ2T DQ2T DQ2T DQ2T T_DQ_15 T_DQ_13 T_DQ_14 T_DQ_12 T_CKE_0 T_DQS_1 T_CKE_1 T_DQS#_1 T_DQ_11 T_DQ_9 T_DQ_10 T_DQ_8 GND T_DQ_15 T_DQ_13 T_DQ_14 T_DQ_12 T_CKE_0 T_DQS_1 T_CKE_1 T_DQS#_1 T_DQ_11 T_DQ_9 T_DQ_10 T_DQ_8 GND DQ5T T_DM_0 T_DM_0 DQ5T DQ5T DQ5T DQ5T DQ5T DQS5T T_DQ_7 T_DQ_5 T_DQ_6 T_DQ_4 T_ODT_1 T_DQS_0 T_ODT_0 T_DQS#_0 T_DQ_3 T_DQ_1 T_DQ_2 T_DQ_0 T_DQ_7 T_DQ_5 T_DQ_6 T_DQ_4 T_ODT_1 T_DQS_0 T_ODT_0 T_DQS#_0 T_DQ_3 T_DQ_1 T_DQ_2 T_DQ_0 DQSn5T DQ5T DQ5T DQ5T DQ5T Page 29 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Optional Function(s) CLK9n FPLL_TL_CLKOUT0,FPLL_TL_CLKOUTp,FPLL_TL_FB FPLL_TL_CLKOUT1,FPLL_TL_CLKOUTn CLK8p,FPLL_TL_FBp CLK8n,FPLL_TL_FBn Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F896 DQS for X8 DIFFIO_TX_T50p DIFFIO_RX_T49n DIFFIO_TX_T50n DIFFIO_RX_T51p DIFFIO_TX_T52p DIFFIO_RX_T51n DIFFIO_TX_T52n DIFFIO_RX_T53p DIFFIO_TX_T54p DIFFIO_RX_T53n DIFFIO_TX_T54n DIFFIO_RX_T55p DIFFIO_TX_T56p DIFFIO_RX_T55n DIFFIO_TX_T56n DIFFIO_RX_T57p DIFFIO_TX_T58p DIFFIO_RX_T57n DIFFIO_TX_T58n DIFFIO_RX_T59p DIFFIO_TX_T60p DIFFIO_RX_T59n DIFFIO_TX_T60n DIFFIO_RX_T61p DIFFIO_TX_T62p DIFFIO_RX_T61n DIFFIO_TX_T62n DIFFIO_RX_T63p DIFFIO_TX_T64p DIFFIO_RX_T63n DIFFIO_TX_T64n DIFFIO_RX_T65p DIFFIO_TX_T66p DIFFIO_RX_T65n DIFFIO_TX_T66n DIFFIO_RX_T67p DIFFIO_TX_T68p DIFFIO_RX_T67n DIFFIO_TX_T68n DIFFIO_RX_T69p DIFFIO_TX_T70p DIFFIO_RX_T69n DIFFIO_TX_T70n DIFFIO_RX_T71p DIFFIO_TX_T72p DIFFIO_RX_T71n DIFFIO_TX_T72n DIFFIO_RX_T73p DIFFIO_TX_T74p DIFFIO_RX_T73n DIFFIO_TX_T74n DIFFIO_RX_T75p DIFFIO_TX_T76p DIFFIO_RX_T75n DIFFIO_TX_T76n DIFFIO_RX_T77p DIFFIO_TX_T78p DIFFIO_RX_T77n DIFFIO_TX_T78n DIFFIO_RX_T79p DIFFIO_TX_T80p DIFFIO_RX_T79n DIFFIO_TX_T80n DIFFIO_RX_T81p DIFFIO_TX_T82p DIFFIO_RX_T81n DIFFIO_TX_T82n DIFFIO_RX_T83p DIFFIO_TX_T84p DIFFIO_RX_T83n DIFFIO_TX_T84n DIFFIO_RX_T85p DIFFIO_TX_T86p DIFFIO_RX_T85n DIFFIO_TX_T86n DIFFIO_RX_T87p DIFFIO_TX_T88p DIFFIO_RX_T87n DIFFOUT_T50p DIFFOUT_T49n DIFFOUT_T50n DIFFOUT_T51p DIFFOUT_T52p DIFFOUT_T51n DIFFOUT_T52n DIFFOUT_T53p DIFFOUT_T54p DIFFOUT_T53n DIFFOUT_T54n DIFFOUT_T55p DIFFOUT_T56p DIFFOUT_T55n DIFFOUT_T56n DIFFOUT_T57p DIFFOUT_T58p DIFFOUT_T57n DIFFOUT_T58n DIFFOUT_T59p DIFFOUT_T60p DIFFOUT_T59n DIFFOUT_T60n DIFFOUT_T61p DIFFOUT_T62p DIFFOUT_T61n DIFFOUT_T62n DIFFOUT_T63p DIFFOUT_T64p DIFFOUT_T63n DIFFOUT_T64n DIFFOUT_T65p DIFFOUT_T66p DIFFOUT_T65n DIFFOUT_T66n DIFFOUT_T67p DIFFOUT_T68p DIFFOUT_T67n DIFFOUT_T68n DIFFOUT_T69p DIFFOUT_T70p DIFFOUT_T69n DIFFOUT_T70n DIFFOUT_T71p DIFFOUT_T72p DIFFOUT_T71n DIFFOUT_T72n DIFFOUT_T73p DIFFOUT_T74p DIFFOUT_T73n DIFFOUT_T74n DIFFOUT_T75p DIFFOUT_T76p DIFFOUT_T75n DIFFOUT_T76n DIFFOUT_T77p DIFFOUT_T78p DIFFOUT_T77n DIFFOUT_T78n DIFFOUT_T79p DIFFOUT_T80p DIFFOUT_T79n DIFFOUT_T80n DIFFOUT_T81p DIFFOUT_T82p DIFFOUT_T81n DIFFOUT_T82n DIFFOUT_T83p DIFFOUT_T84p DIFFOUT_T83n DIFFOUT_T84n DIFFOUT_T85p DIFFOUT_T86p DIFFOUT_T85n DIFFOUT_T86n DIFFOUT_T87p DIFFOUT_T88p DIFFOUT_T87n B11 K15 A11 F16 F9 E16 E10 M9 D9 M8 C10 F15 A10 E15 A9 L14 C9 L13 B8 E12 B7 D13 A8 J15 B6 H15 A6 E11 C7 D10 C6 L10 F13 L9 E13 G14 A5 F14 A4 J14 J7 H14 H7 L11 J9 K11 H9 P12 G9 N12 F8 H12 E8 G12 D8 K13 A3 J13 A2 P10 D7 N11 D6 R12 E7 R11 E6 K12 K10 J12 J10 N10 G6 N9 F6 M12 G8 M11 DQ6T Pin List EF31 DQS for X16 DQ6T DQ6T DQ6T DQ6T DQ6T DQS6T DQSn6T DQ6T DQ6T DQ6T DQ6T HMC Pin Assignment for DDR3/DDR2 (2) T_A_0 HMC Pin Assignment for LPDDR2 T_CA_0 T_A_1 T_A_4 T_A_2 T_A_5 T_A_3 T_CK T_A_6 T_CK# T_A_7 T_BA_1 T_BA_0 T_BA_2 GND T_CA_1 T_CA_4 T_CA_2 T_CA_5 T_CA_3 T_CK T_CA_6 T_CK# T_CA_7 DQ7T T_CAS# DQ7T DQ7T DQ7T DQ7T DQ7T DQS7T T_RAS# T_A_8 T_A_10 T_A_9 T_A_11 T_CS#_0 T_A_12 T_CS#_1 T_A_13 T_A_14 T_WE# T_A_15 GND DQSn7T DQ7T DQ7T DQ7T DQ7T GND T_CA_8 T_CA_9 T_CS#_0 T_CS#_1 GND DQ8T DQ8T DQ8T DQ8T DQ8T DQ8T DQS8T DQSn8T DQ8T DQ8T DQ8T DQ8T DQ9T DQ3T DQ9T DQ9T DQ9T DQ9T DQ9T DQS9T DQ3T DQ3T DQ3T DQ3T DQ3T DQS3T DQSn9T DQ9T DQ9T DQ9T DQ9T DQSn3T DQ3T DQ3T DQ3T DQ3T DQ10T DQ3T DQ10T DQ10T DQ10T DQ10T DQ10T DQS10T DQ3T DQ3T DQ3T DQ3T DQ3T DQ3T DQSn10T DQ10T DQ10T DQ10T DQ10T DQ3T DQ3T DQ3T DQ3T DQ3T Page 30 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function 8A 9A 9A 9A 9A 9A 9A 9A 9A 9A 9A VREFB8AN0 IO MSEL0 CONF_DONE MSEL1 nSTATUS nCE MSEL2 MSEL3 nCONFIG MSEL4 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F896 DIFFIO_TX_T88n DIFFOUT_T88n G7 T8 L8 P9 K7 H6 G5 P7 C5 M7 E5 F22 AK2 AK14 AK24 AK29 AJ6 AJ11 AJ21 AH1 AH2 AH3 AH8 AH18 AH28 AG3 AG4 AG15 AG25 AF1 AF2 AF5 AF12 AF22 AE3 AE4 AE6 AE9 AE19 AE29 AD1 AD2 AD5 AD7 AD16 AD26 AC3 AC4 AC6 AC13 AC23 AB1 AB2 AB5 AB10 AB20 AB30 AA3 AA4 AA6 AA17 AA27 Y1 Y2 Y5 Y7 Y14 Y24 W3 W4 W6 W11 W13 W15 W17 W19 W21 V1 MSEL0 CONF_DONE MSEL1 nSTATUS nCE MSEL2 MSEL3 nCONFIG MSEL4 Pin List EF31 DQS for X8 DQS for X16 HMC Pin Assignment for DDR3/DDR2 (2) HMC Pin Assignment for LPDDR2 Page 31 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Emulated LVDS Output Channel F896 DQS for X8 DQS for X16 HMC Pin Assignment for DDR3/DDR2 (2) HMC Pin Assignment for LPDDR2 V2 V5 V8 V14 V16 V18 V20 V23 V28 U3 U4 U6 U13 U15 U17 U19 U25 T1 T2 T5 T12 T14 T16 T18 T20 T22 R3 R4 R6 R9 R13 R15 R17 R19 R29 P1 P2 P5 P11 P14 P16 P18 P26 N3 N4 N6 N8 N13 N15 N17 N19 N23 M1 M2 M5 M10 M14 M16 M18 M20 M30 L3 L4 L6 L17 L27 K1 K2 K5 K9 K14 K24 J3 J4 J6 J11 J21 H1 Pin List EF31 Page 32 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC DNU DNU DNU DNU DNU DNU VCCPGM VCCPGM VCCPGM VCCBAT VCCIO3A PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Emulated LVDS Output Channel F896 DQS for X8 DQS for X16 HMC Pin Assignment for DDR3/DDR2 (2) HMC Pin Assignment for LPDDR2 H2 H5 H8 H11 H18 H28 G3 G4 G15 G25 F1 F2 F5 F12 E3 E4 E9 E19 E29 D1 D2 D5 D16 D26 C2 C3 C4 C13 C23 B1 B2 B10 B20 B30 A12 A17 A27 M15 W14 W16 W18 W20 V13 V15 V17 V19 U14 U16 U18 U20 T13 T15 T17 T19 R14 R16 R18 P13 P15 P17 P19 N14 N16 N18 M13 M17 M19 B4 B3 AD8 AD14 F24 D15 AC11 AB24 F10 H10 U10 Pin List EF31 Page 33 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel VCCIO3A VCCIO3A VCCIO3A VCCIO3B VCCIO3B VCCIO3B VCCIO3B VCCIO3B VCCIO3B VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO5A VCCIO5A VCCIO5A VCCIO5A VCCIO5B VCCIO5B VCCIO5B VCCIO5B VCCIO5B VCCIO5B VCCIO6A VCCIO6A VCCIO6A VCCIO6A VCCIO6A VCCIO6A VCCIO6A VCCIO6A VCCIO6A VCCIO6A VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCPD3A VCCPD3A VCCPD3B4A VCCPD3B4A VCCPD3B4A VCCPD3B4A VCCPD3B4A VCCPD3B4A VCCPD5A VCCPD5A VCCPD5B VCCPD5B VCCPD6A VCCPD6A VCCPD6A VCCPD7A8A VCCPD7A8A VCCPD7A8A VCCPD7A8A PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Emulated LVDS Output Channel F896 DQS for X8 DQS for X16 HMC Pin Assignment for DDR3/DDR2 (2) HMC Pin Assignment for LPDDR2 AD11 AC8 Y9 AA12 AK4 AK9 AH13 AG10 AE14 AK19 AJ16 AJ26 AH23 AG20 AF17 AD21 AC18 AB15 Y19 AF27 AE24 AB25 AA22 AG30 AC28 Y29 W26 U30 T27 R24 P21 N28 M25 L22 K29 J26 G30 F27 C28 K19 H23 G20 F17 E24 D21 C18 B15 B25 A22 A7 L12 J16 H13 G10 F7 E14 D11 C8 B5 AD10 AB11 AC20 AE11 AE21 AD15 AC12 AC17 W23 W25 U24 T26 P24 M24 K23 D24 G13 G16 G19 Pin List EF31 Page 34 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number 3A 3B 4A 5A 5B 6A 7A 8A VREF VREFB3AN0 VREFB3BN0 VREFB4AN0 VREFB5AN0 VREFB5BN0 VREFB6AN0 VREFB7AN0 VREFB8AN0 Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel VCCPD7A8A VCCPD7A8A VCCPD7A8A VREFB3AN0 VREFB3BN0 VREFB4AN0 VREFB5AN0 VREFB5BN0 VREFB6AN0 VREFB7AN0 VREFB8AN0 VCCH_GXBL VCCH_GXBL VCCH_GXBL VCCH_GXBL VCCL_GXBL VCCL_GXBL VCCL_GXBL VCCL_GXBL RREF_TL VCCA_FPLL VCCA_FPLL VCCA_FPLL VCCA_FPLL VCC_AUX VCC_AUX VCC_AUX VCC_AUX VCC_AUX VCC_AUX VCCE_GXBL VCCE_GXBL VCCE_GXBL VCCE_GXBL VCCE_GXBL VCCE_GXBL VCCE_GXBL VCCE_GXBL Emulated LVDS Output Channel F896 DQS for X8 DQS for X16 HMC Pin Assignment for DDR3/DDR2 (2) HMC Pin Assignment for LPDDR2 F11 F21 F23 AE8 AJ13 AH16 AC25 P27 M26 B16 B9 AB6 V6 P6 K6 AC5 W5 R5 L5 C1 Y8 J8 AB23 J24 G11 AC10 AD22 AC16 H16 H22 AD6 AA5 Y6 U5 T6 N5 M6 J5 Notes: (1) For more information about pin definition and pin connection guidelines, refer to the Cyclone V Device Family Pin Connection Guidelines. (2) RESET pin is only applicable for DDR3 device. PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Pin List EF31 Page 35 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number GXB_L3 GXB_L3 GXB_L3 GXB_L3 GXB_L3 GXB_L3 GXB_L3 GXB_L3 GXB_L3 GXB_L3 GXB_L3 GXB_L3 GXB_L3 GXB_L3 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. VREF Pin Name/Function VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 REFCLK3Ln REFCLK3Lp GXB_TX_L11n GXB_TX_L11p GXB_RX_L11p,GXB_REFCLK_L11p GXB_RX_L11n,GXB_REFCLK_L11n GXB_TX_L10n GXB_TX_L10p GXB_RX_L10p,GXB_REFCLK_L10p GXB_RX_L10n,GXB_REFCLK_L10n GXB_TX_L9n GXB_TX_L9p GXB_RX_L9p,GXB_REFCLK_L9p GXB_RX_L9n,GXB_REFCLK_L9n GXB_TX_L8n GXB_TX_L8p GXB_RX_L8p,GXB_REFCLK_L8p GXB_RX_L8n,GXB_REFCLK_L8n GXB_TX_L7n GXB_TX_L7p GXB_RX_L7p,GXB_REFCLK_L7p GXB_RX_L7n,GXB_REFCLK_L7n GXB_TX_L6n GXB_TX_L6p GXB_RX_L6p,GXB_REFCLK_L6p GXB_RX_L6n,GXB_REFCLK_L6n REFCLK2Lp REFCLK2Ln REFCLK1Ln REFCLK1Lp GXB_TX_L5n GXB_TX_L5p GXB_RX_L5p,GXB_REFCLK_L5p GXB_RX_L5n,GXB_REFCLK_L5n GXB_TX_L4n GXB_TX_L4p GXB_RX_L4p,GXB_REFCLK_L4p GXB_RX_L4n,GXB_REFCLK_L4n GXB_TX_L3n GXB_TX_L3p GXB_RX_L3p,GXB_REFCLK_L3p GXB_RX_L3n,GXB_REFCLK_L3n GXB_TX_L2n GXB_TX_L2p GXB_RX_L2p,GXB_REFCLK_L2p GXB_RX_L2n,GXB_REFCLK_L2n GXB_TX_L1n GXB_TX_L1p GXB_RX_L1p,GXB_REFCLK_L1p GXB_RX_L1n,GXB_REFCLK_L1n GXB_TX_L0n GXB_TX_L0p GXB_RX_L0p,GXB_REFCLK_L0p GXB_RX_L0n,GXB_REFCLK_L0n REFCLK0Lp REFCLK0Ln TDO nCSO TMS AS_DATA3 TCK AS_DATA2 TDI AS_DATA1 DCLK AS_DATA0,ASDO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function TDO DATA4 TMS DATA3 TCK DATA2 TDI DATA1 DCLK DATA0 DATA6 DATA5 DATA8 DATA7 DATA10 DATA9 DATA12 DATA11 DATA14 DATA13 CLKUSR DATA15 PR_DONE Dedicated Tx/Rx Channel DIFFIO_RX_B1n DIFFIO_TX_B2n DIFFIO_RX_B1p DIFFIO_TX_B2p DIFFIO_RX_B3n DIFFIO_TX_B4n DIFFIO_RX_B3p DIFFIO_TX_B4p DIFFIO_RX_B5n DIFFIO_TX_B6n DIFFIO_RX_B5p DIFFIO_TX_B6p DIFFIO_RX_B7n Pin List EF35 Emulated LVDS Output Channel F1152 DIFFOUT_B1n DIFFOUT_B2n DIFFOUT_B1p DIFFOUT_B2p DIFFOUT_B3n DIFFOUT_B4n DIFFOUT_B3p DIFFOUT_B4p DIFFOUT_B5n DIFFOUT_B6n DIFFOUT_B5p DIFFOUT_B6p DIFFOUT_B7n P10 R11 F3 F4 G2 G1 H3 H4 J2 J1 K3 K4 L2 L1 M3 M4 N2 N1 P3 P4 R2 R1 T3 T4 U2 U1 U11 T10 V10 W11 V3 V4 W2 W1 Y3 Y4 AA2 AA1 AB3 AB4 AC2 AC1 AD3 AD4 AE2 AE1 AF3 AF4 AG2 AG1 AH3 AH4 AJ2 AJ1 AA11 AB10 AF11 AG10 AG11 AJ6 AK5 AH8 AE10 AJ7 AF10 AH9 AD11 AM4 AD12 AM5 AJ11 AL7 AH12 AK7 AG13 AL8 AF13 AK8 AC12 DQS for X8 DQS for X16 HMC Pin Assignment HMC Pin Assignment for DDR3/DDR2 (2) for LPDDR2 DQ1B DQ1B DQ1B DQSn1B DQ1B DQS1B DQ1B DQ1B DQ1B DQ1B Page 36 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Optional Function(s) CLK0n,FPLL_BL_FBn CLK0p,FPLL_BL_FBp FPLL_BL_CLKOUT1,FPLL_BL_CLKOUTn FPLL_BL_CLKOUT0,FPLL_BL_CLKOUTp,FPLL_BL_FB Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F1152 DQS for X8 PR_READY PR_ERROR DIFFIO_TX_B8n DIFFIO_RX_B7p DIFFIO_TX_B8p DIFFIO_TX_B9n DIFFIO_RX_B10n DIFFIO_TX_B9p DIFFIO_RX_B10p DIFFIO_RX_B11n DIFFIO_TX_B12n DIFFIO_RX_B11p DIFFIO_TX_B12p DIFFIO_TX_B13n DIFFIO_RX_B14n DIFFIO_TX_B13p DIFFIO_RX_B14p DIFFIO_RX_B15n DIFFIO_TX_B16n DIFFIO_RX_B15p DIFFIO_TX_B16p DIFFIO_TX_B17n DIFFIO_RX_B18n DIFFIO_TX_B17p DIFFIO_RX_B18p DIFFIO_RX_B19n DIFFIO_TX_B20n DIFFIO_RX_B19p DIFFIO_TX_B20p DIFFIO_TX_B21n DIFFIO_RX_B22n DIFFIO_TX_B21p DIFFIO_RX_B22p DIFFIO_RX_B23n DIFFIO_TX_B24n DIFFIO_RX_B23p DIFFIO_TX_B24p DIFFIO_TX_B25n DIFFIO_RX_B26n DIFFIO_TX_B25p DIFFIO_RX_B26p DIFFIO_RX_B27n DIFFIO_TX_B28n DIFFIO_RX_B27p DIFFIO_TX_B28p DIFFIO_TX_B29n DIFFIO_RX_B30n DIFFIO_TX_B29p DIFFIO_RX_B30p DIFFIO_RX_B31n DIFFIO_TX_B32n DIFFIO_RX_B31p DIFFIO_TX_B32p DIFFIO_TX_B33n DIFFIO_RX_B34n DIFFIO_TX_B33p DIFFIO_RX_B34p DIFFIO_RX_B35n DIFFIO_TX_B36n DIFFIO_RX_B35p DIFFIO_TX_B36p DIFFIO_TX_B37n DIFFIO_RX_B38n DIFFIO_TX_B37p DIFFIO_RX_B38p DIFFIO_RX_B39n DIFFIO_TX_B40n DIFFIO_RX_B39p DIFFIO_TX_B40p DIFFIO_TX_B41n DIFFIO_RX_B42n DIFFIO_TX_B41p DIFFIO_RX_B42p DIFFIO_RX_B43n DIFFIO_TX_B44n DIFFIO_RX_B43p DIFFIO_TX_B44p DIFFIO_TX_B45n DIFFIO_RX_B46n DIFFIO_TX_B45p DIFFIO_RX_B46p DIFFOUT_B8n DIFFOUT_B7p DIFFOUT_B8p DIFFOUT_B9n DIFFOUT_B10n DIFFOUT_B9p DIFFOUT_B10p DIFFOUT_B11n DIFFOUT_B12n DIFFOUT_B11p DIFFOUT_B12p DIFFOUT_B13n DIFFOUT_B14n DIFFOUT_B13p DIFFOUT_B14p DIFFOUT_B15n DIFFOUT_B16n DIFFOUT_B15p DIFFOUT_B16p DIFFOUT_B17n DIFFOUT_B18n DIFFOUT_B17p DIFFOUT_B18p DIFFOUT_B19n DIFFOUT_B20n DIFFOUT_B19p DIFFOUT_B20p DIFFOUT_B21n DIFFOUT_B22n DIFFOUT_B21p DIFFOUT_B22p DIFFOUT_B23n DIFFOUT_B24n DIFFOUT_B23p DIFFOUT_B24p DIFFOUT_B25n DIFFOUT_B26n DIFFOUT_B25p DIFFOUT_B26p DIFFOUT_B27n DIFFOUT_B28n DIFFOUT_B27p DIFFOUT_B28p DIFFOUT_B29n DIFFOUT_B30n DIFFOUT_B29p DIFFOUT_B30p DIFFOUT_B31n DIFFOUT_B32n DIFFOUT_B31p DIFFOUT_B32p DIFFOUT_B33n DIFFOUT_B34n DIFFOUT_B33p DIFFOUT_B34p DIFFOUT_B35n DIFFOUT_B36n DIFFOUT_B35p DIFFOUT_B36p DIFFOUT_B37n DIFFOUT_B38n DIFFOUT_B37p DIFFOUT_B38p DIFFOUT_B39n DIFFOUT_B40n DIFFOUT_B39p DIFFOUT_B40p DIFFOUT_B41n DIFFOUT_B42n DIFFOUT_B41p DIFFOUT_B42p DIFFOUT_B43n DIFFOUT_B44n DIFFOUT_B43p DIFFOUT_B44p DIFFOUT_B45n DIFFOUT_B46n DIFFOUT_B45p DIFFOUT_B46p AK9 AC13 AJ9 AM6 AK10 AL6 AJ10 AB13 AN4 AB14 AN5 AP5 AJ12 AP6 AH13 AE14 AP7 AD14 AN7 AN8 AH14 AM8 AG14 AC14 AN9 AD15 AM9 AM10 AK14 AL10 AJ14 AB15 AK12 AA15 AK13 AM11 AM15 AL11 AL15 AG15 AP9 AG16 AP10 AP11 AK15 AN11 AJ15 AD16 AL13 AC16 AL12 AP12 AN14 AN12 AM14 AB16 AN13 AA16 AM13 AM16 AJ16 AL16 AH16 AC17 AP14 AD17 AP15 AP16 AP17 AN16 AN17 AA17 AL17 AA18 AK17 AN18 AJ17 AM18 AH17 DQ1B Pin List EF35 DQS for X16 HMC Pin Assignment HMC Pin Assignment for DDR3/DDR2 (2) for LPDDR2 DQ1B DQ2B DQ2B DQ2B DQSn2B DQ2B DQS2B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ2B DQ2B DQ2B DQ2B DQ1B DQ1B DQ1B DQ1B DQ2B DQ1B DQ2B DQ1B DQ3B DQ3B DQ3B DQSn3B DQ3B DQS3B DQ1B DQ1B DQ1B DQSn1B DQ1B DQS1B DQ3B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DQ1B DQ3B DQ1B DQ3B DQ1B DQ4B DQ4B DQ4B DQSn4B DQ4B DQS4B DQ2B DQ2B DQ2B DQ2B DQ2B DQ2B DQ4B DQ4B DQ4B DQ4B DQ2B DQ2B DQ2B DQ2B DQ4B DQ2B DQ4B DQ2B DQ5B DQ5B DQ5B DQSn5B DQ5B DQS5B DQ2B DQ2B DQ2B DQSn2B DQ2B DQS2B DQ5B DQ5B DQ5B DQ5B DQ2B DQ2B DQ2B DQ2B GND B_A_15 B_WE# B_A_14 B_CS#_1 B_A_13 B_CS#_0 B_A_12 B_A_11 B_A_9 B_A_10 B_A_8 DQ5B DQ2B B_RAS# DQ5B DQ2B B_CAS# GND B_BA_2 B_BA_0 B_BA_1 B_CK# B_A_7 B_CK B_A_6 B_A_3 B_A_5 B_A_2 B_A_4 DQ6B DQ6B DQ6B DQSn6B DQ6B DQS6B DQ6B DQ6B DQ6B DQ6B GND B_CS#_1 B_CS#_0 B_CA_9 B_CA_8 GND B_CK# B_CA_7 B_CK B_CA_6 B_CA_3 B_CA_5 B_CA_2 B_CA_4 Page 37 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function Optional Function(s) 3B 3B 3B 3B 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO CLK1n PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. CLK1p RZQ_0 CLK2n CLK2p CLK3n CLK3p Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F1152 DIFFIO_RX_B47n DIFFIO_TX_B48n DIFFIO_RX_B47p DIFFIO_TX_B48p DIFFIO_TX_B49n DIFFIO_RX_B50n DIFFIO_TX_B49p DIFFIO_RX_B50p DIFFIO_RX_B51n DIFFIO_TX_B52n DIFFIO_RX_B51p DIFFIO_TX_B52p DIFFIO_TX_B53n DIFFIO_RX_B54n DIFFIO_TX_B53p DIFFIO_RX_B54p DIFFIO_RX_B55n DIFFIO_TX_B56n DIFFIO_RX_B55p DIFFIO_TX_B56p DIFFIO_TX_B57n DIFFIO_RX_B58n DIFFIO_TX_B57p DIFFIO_RX_B58p DIFFIO_RX_B59n DIFFIO_TX_B60n DIFFIO_RX_B59p DIFFIO_TX_B60p DIFFIO_TX_B61n DIFFIO_RX_B62n DIFFIO_TX_B61p DIFFIO_RX_B62p DIFFIO_RX_B63n DIFFIO_TX_B64n DIFFIO_RX_B63p DIFFIO_TX_B64p DIFFIO_TX_B65n DIFFIO_RX_B66n DIFFIO_TX_B65p DIFFIO_RX_B66p DIFFIO_RX_B67n DIFFIO_TX_B68n DIFFIO_RX_B67p DIFFIO_TX_B68p DIFFIO_TX_B69n DIFFIO_RX_B70n DIFFIO_TX_B69p DIFFIO_RX_B70p DIFFIO_RX_B71n DIFFIO_TX_B72n DIFFIO_RX_B71p DIFFIO_TX_B72p DIFFIO_TX_B73n DIFFIO_RX_B74n DIFFIO_TX_B73p DIFFIO_RX_B74p DIFFIO_RX_B75n DIFFIO_TX_B76n DIFFIO_RX_B75p DIFFIO_TX_B76p DIFFIO_TX_B77n DIFFIO_RX_B78n DIFFIO_TX_B77p DIFFIO_RX_B78p DIFFIO_RX_B79n DIFFIO_TX_B80n DIFFIO_RX_B79p DIFFIO_TX_B80p DIFFIO_TX_B81n DIFFIO_RX_B82n DIFFIO_TX_B81p DIFFIO_RX_B82p DIFFIO_RX_B83n DIFFIO_TX_B84n DIFFIO_RX_B83p DIFFIO_TX_B84p DIFFIO_TX_B85n DIFFIO_RX_B86n DIFFIO_TX_B85p DIFFOUT_B47n DIFFOUT_B48n DIFFOUT_B47p DIFFOUT_B48p DIFFOUT_B49n DIFFOUT_B50n DIFFOUT_B49p DIFFOUT_B50p DIFFOUT_B51n DIFFOUT_B52n DIFFOUT_B51p DIFFOUT_B52p DIFFOUT_B53n DIFFOUT_B54n DIFFOUT_B53p DIFFOUT_B54p DIFFOUT_B55n DIFFOUT_B56n DIFFOUT_B55p DIFFOUT_B56p DIFFOUT_B57n DIFFOUT_B58n DIFFOUT_B57p DIFFOUT_B58p DIFFOUT_B59n DIFFOUT_B60n DIFFOUT_B59p DIFFOUT_B60p DIFFOUT_B61n DIFFOUT_B62n DIFFOUT_B61p DIFFOUT_B62p DIFFOUT_B63n DIFFOUT_B64n DIFFOUT_B63p DIFFOUT_B64p DIFFOUT_B65n DIFFOUT_B66n DIFFOUT_B65p DIFFOUT_B66p DIFFOUT_B67n DIFFOUT_B68n DIFFOUT_B67p DIFFOUT_B68p DIFFOUT_B69n DIFFOUT_B70n DIFFOUT_B69p DIFFOUT_B70p DIFFOUT_B71n DIFFOUT_B72n DIFFOUT_B71p DIFFOUT_B72p DIFFOUT_B73n DIFFOUT_B74n DIFFOUT_B73p DIFFOUT_B74p DIFFOUT_B75n DIFFOUT_B76n DIFFOUT_B75p DIFFOUT_B76p DIFFOUT_B77n DIFFOUT_B78n DIFFOUT_B77p DIFFOUT_B78p DIFFOUT_B79n DIFFOUT_B80n DIFFOUT_B79p DIFFOUT_B80p DIFFOUT_B81n DIFFOUT_B82n DIFFOUT_B81p DIFFOUT_B82p DIFFOUT_B83n DIFFOUT_B84n DIFFOUT_B83p DIFFOUT_B84p DIFFOUT_B85n DIFFOUT_B86n DIFFOUT_B85p AB18 AL18 AC18 AK18 AP19 AN19 AP20 AM19 AC19 AP21 AB19 AN21 AK19 AH19 AJ19 AG19 AG18 AM21 AF18 AL21 AP22 AM20 AN22 AL20 AE19 AN23 AD19 AM23 AP26 AP24 AN26 AP25 AE20 AN24 AD20 AM24 AL22 AP27 AK22 AN27 AK20 AJ21 AJ20 AJ22 AP29 AH21 AP30 AH22 AB20 AN28 AB21 AM28 AM25 AL23 AL25 AK23 AA20 AM26 Y20 AL26 AP31 AK24 AN31 AJ24 AG21 AL28 AF22 AL27 AP32 AH23 AN32 AG23 AD21 AN29 AC21 AM29 AK27 AK25 AK28 Pin List EF35 DQS for X8 DQS for X16 HMC Pin Assignment HMC Pin Assignment for DDR3/DDR2 (2) for LPDDR2 DQ6B B_A_1 B_CA_1 DQ6B B_A_0 B_CA_0 DQ7B DQ7B DQ7B DQSn7B DQ7B DQS7B DQ7B DQ7B DQ7B DQ7B B_DQ_0 B_DQ_2 B_DQ_1 B_DQS#_0 B_DQ_3 B_DQS_0 B_ODT_0 B_ODT_1 B_DQ_4 B_DQ_6 B_DQ_5 B_DQ_0 B_DQ_2 B_DQ_1 B_DQS#_0 B_DQ_3 B_DQS_0 B_ODT_0 B_ODT_1 B_DQ_4 B_DQ_6 B_DQ_5 DQ7B B_DQ_7 B_DQ_7 DQ7B B_DM_0 GND B_DQ_8 B_DQ_10 B_DQ_9 B_DQS#_1 B_DQ_11 B_DQS_1 B_CKE_1 B_CKE_0 B_DQ_12 B_DQ_14 B_DQ_13 DQ8B DQ8B DQ8B DQSn8B DQ8B DQS8B DQ3B DQ3B DQ3B DQ3B DQ3B DQ3B DQ8B DQ8B DQ8B DQ8B DQ3B DQ3B DQ3B DQ3B B_DM_0 GND B_DQ_8 B_DQ_10 B_DQ_9 B_DQS#_1 B_DQ_11 B_DQS_1 B_CKE_1 B_CKE_0 B_DQ_12 B_DQ_14 B_DQ_13 DQ8B DQ3B B_DQ_15 B_DQ_15 DQ8B DQ3B DQ9B DQ9B DQ9B DQSn9B DQ9B DQS9B DQ3B DQ3B DQ3B DQSn3B DQ3B DQS3B DQ9B DQ9B DQ9B DQ9B DQ3B DQ3B DQ3B DQ3B DQ9B DQ3B DQ9B DQ3B DQ10B DQ10B DQ10B DQSn10B DQ10B DQS10B DQ4B DQ4B DQ4B DQ4B DQ4B DQ4B DQ10B DQ10B DQ10B DQ10B DQ4B DQ4B DQ4B DQ4B DQ10B DQ4B DQ10B DQ4B DQ11B DQ11B DQ11B DQSn11B DQ11B DQS11B DQ4B DQ4B DQ4B DQSn4B DQ4B DQS4B DQ11B DQ11B DQ11B DQ4B DQ4B DQ4B B_DM_1 GND B_DQ_16 B_DQ_18 B_DQ_17 B_DQS#_2 B_DQ_19 B_DQS_2 B_RESET# GND B_DQ_20 B_DQ_22 B_DQ_21 GND B_DQ_23 GND B_DM_2 GND B_DQ_24 B_DQ_26 B_DQ_25 B_DQS#_3 B_DQ_27 B_DQS_3 GND GND B_DQ_28 B_DQ_30 B_DQ_29 GND B_DQ_31 GND B_DM_3 GND B_DQ_32 B_DQ_34 B_DQ_33 B_DQS#_4 B_DQ_35 B_DQS_4 GND GND B_DQ_36 B_DQ_38 B_DM_1 GND B_DQ_16 B_DQ_18 B_DQ_17 B_DQS#_2 B_DQ_19 B_DQS_2 B_RESET# GND B_DQ_20 B_DQ_22 B_DQ_21 GND B_DQ_23 GND B_DM_2 GND B_DQ_24 B_DQ_26 B_DQ_25 B_DQS#_3 B_DQ_27 B_DQS_3 GND GND B_DQ_28 B_DQ_30 B_DQ_29 GND B_DQ_31 GND B_DM_3 GND B_DQ_32 B_DQ_34 B_DQ_33 B_DQS#_4 B_DQ_35 B_DQS_4 GND GND B_DQ_36 B_DQ_38 Page 38 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Optional Function(s) Configuration Function RZQ_1 INIT_DONE PR_REQUEST CRC_ERROR nCEO CvP_CONFDONE DEV_OE nPERSTL0 DEV_CLRn nPERSTL1 Dedicated Tx/Rx Channel Emulated LVDS Output Channel F1152 DQS for X8 DQS for X16 HMC Pin Assignment HMC Pin Assignment for DDR3/DDR2 (2) for LPDDR2 DIFFIO_RX_B86p DIFFIO_RX_B87n DIFFIO_TX_B88n DIFFIO_RX_B87p DIFFIO_TX_B88p DIFFIO_TX_B89n DIFFIO_RX_B90n DIFFIO_TX_B89p DIFFIO_RX_B90p DIFFIO_RX_B91n DIFFIO_TX_B92n DIFFIO_RX_B91p DIFFIO_TX_B92p DIFFIO_TX_B93n DIFFIO_RX_B94n DIFFIO_TX_B93p DIFFIO_RX_B94p DIFFIO_RX_B95n DIFFIO_TX_B96n DIFFIO_RX_B95p DIFFIO_TX_B96p DIFFIO_TX_R1p DIFFIO_RX_R2p DIFFIO_TX_R1n DIFFIO_RX_R2n DIFFIO_TX_R3p DIFFIO_RX_R4p DIFFIO_TX_R3n DIFFIO_RX_R4n DIFFIO_TX_R5p DIFFIO_RX_R6p DIFFIO_TX_R5n DIFFIO_RX_R6n DIFFIO_TX_R7p DIFFIO_RX_R8p DIFFIO_TX_R7n DIFFIO_RX_R8n DIFFIO_RX_R9p DIFFIO_TX_R10p DIFFIO_RX_R9n DIFFIO_TX_R10n DIFFIO_RX_R11p DIFFIO_TX_R12p DIFFIO_RX_R11n DIFFIO_TX_R12n DIFFIO_RX_R13p DIFFIO_TX_R14p DIFFIO_RX_R13n DIFFIO_TX_R14n DIFFIO_RX_R15p DIFFIO_TX_R16p DIFFIO_RX_R15n DIFFIO_TX_R16n DIFFIO_RX_R17p DIFFIO_TX_R18p DIFFIO_RX_R17n DIFFIO_TX_R18n DIFFIO_RX_R19p DIFFIO_TX_R20p DIFFIO_RX_R19n DIFFIO_TX_R20n DIFFIO_RX_R21p DIFFIO_TX_R22p DIFFIO_RX_R21n DIFFIO_TX_R22n DIFFIO_RX_R23p DIFFIO_TX_R24p DIFFIO_RX_R23n DIFFIO_TX_R24n DIFFIO_RX_R25p DIFFIO_TX_R26p DIFFIO_RX_R25n DIFFIO_TX_R26n DIFFIO_RX_R27p DIFFIO_TX_R28p DIFFIO_RX_R27n DIFFIO_TX_R28n DIFFIO_RX_R29p DIFFIO_TX_R30p DIFFOUT_B86p DIFFOUT_B87n DIFFOUT_B88n DIFFOUT_B87p DIFFOUT_B88p DIFFOUT_B89n DIFFOUT_B90n DIFFOUT_B89p DIFFOUT_B90p DIFFOUT_B91n DIFFOUT_B92n DIFFOUT_B91p DIFFOUT_B92p DIFFOUT_B93n DIFFOUT_B94n DIFFOUT_B93p DIFFOUT_B94p DIFFOUT_B95n DIFFOUT_B96n DIFFOUT_B95p DIFFOUT_B96p DIFFOUT_R1p DIFFOUT_R2p DIFFOUT_R1n DIFFOUT_R2n DIFFOUT_R3p DIFFOUT_R4p DIFFOUT_R3n DIFFOUT_R4n DIFFOUT_R5p DIFFOUT_R6p DIFFOUT_R5n DIFFOUT_R6n DIFFOUT_R7p DIFFOUT_R8p DIFFOUT_R7n DIFFOUT_R8n DIFFOUT_R9p DIFFOUT_R10p DIFFOUT_R9n DIFFOUT_R10n DIFFOUT_R11p DIFFOUT_R12p DIFFOUT_R11n DIFFOUT_R12n DIFFOUT_R13p DIFFOUT_R14p DIFFOUT_R13n DIFFOUT_R14n DIFFOUT_R15p DIFFOUT_R16p DIFFOUT_R15n DIFFOUT_R16n DIFFOUT_R17p DIFFOUT_R18p DIFFOUT_R17n DIFFOUT_R18n DIFFOUT_R19p DIFFOUT_R20p DIFFOUT_R19n DIFFOUT_R20n DIFFOUT_R21p DIFFOUT_R22p DIFFOUT_R21n DIFFOUT_R22n DIFFOUT_R23p DIFFOUT_R24p DIFFOUT_R23n DIFFOUT_R24n DIFFOUT_R25p DIFFOUT_R26p DIFFOUT_R25n DIFFOUT_R26n DIFFOUT_R27p DIFFOUT_R28p DIFFOUT_R27n DIFFOUT_R28n DIFFOUT_R29p DIFFOUT_R30p AJ25 AF23 AM30 AE23 AL30 AK29 AH24 AJ29 AG24 AD22 AM31 AC22 AL31 AJ26 AG26 AH26 AG25 AE25 AJ27 AF25 AH27 AD24 AC23 AD25 AC24 AC27 AB24 AC26 AB23 AE29 AA21 AD29 AA22 AC28 Y24 AC29 Y25 AB25 AF27 AA25 AF26 AB28 AE28 AB29 AF28 AA23 AG28 Y22 AH28 AB30 AG29 AA30 AH29 AA27 AK30 AA28 AJ30 AG30 AN33 AF30 AM33 Y23 AL32 W24 AK32 AH31 AL33 AJ31 AK33 AA32 AE30 Y32 AD30 Y28 AH32 Y27 AJ32 Y29 AG31 DQ11B DQ4B DQ11B DQ4B DQ11B DQ4B B_DQ_37 GND B_DQ_39 GND B_DM_4 Pin List EF35 B_DQ_37 GND B_DQ_39 GND B_DM_4 DQ12B DQ12B DQ12B DQSn12B DQ12B DQS12B DQ12B DQ12B DQ12B DQ12B DQ12B DQ12B DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQS1R DQ1R DQSn1R DQ1R DQ1R DQ1R DQ2R DQ1R DQ2R DQ2R DQ2R DQ2R DQ2R DQS2R DQ1R DQ1R DQ1R DQ1R DQ1R DQS1R DQSn2R DQ2R DQ2R DQ2R DQ2R DQSn1R DQ1R DQ1R DQ1R DQ1R DQ3R DQ1R DQ3R DQ3R DQ3R DQ3R DQ3R DQS3R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQSn3R DQ3R DQ3R DQ3R DQ3R DQ1R DQ1R DQ1R DQ1R DQ1R DQ4R DQ2R DQ4R DQ4R DQ4R DQ4R DQ4R DQS4R DQ2R DQ2R DQ2R DQ2R DQ2R DQS2R Page 39 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 5B 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB5BN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Optional Function(s) CLK7p,FPLL_BR_FBp CLK7n,FPLL_BR_FBn CLK6p CLK6n FPLL_BR_CLKOUT0,FPLL_BR_CLKOUTp,FPLL_BR_FB FPLL_BR_CLKOUT1,FPLL_BR_CLKOUTn CLK5p CLK5n FPLL_TR_CLKOUT0,FPLL_TR_CLKOUTp,FPLL_TR_FB FPLL_TR_CLKOUT1,FPLL_TR_CLKOUTn CLK4p,FPLL_TR_FBp CLK4n,FPLL_TR_FBn Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F1152 DQS for X8 DQS for X16 DIFFIO_RX_R29n DIFFIO_TX_R30n DIFFIO_RX_R31p DIFFIO_TX_R32p DIFFIO_RX_R31n DIFFIO_TX_R32n DIFFIO_RX_R33p DIFFIO_TX_R34p DIFFIO_RX_R33n DIFFIO_TX_R34n DIFFIO_RX_R35p DIFFIO_TX_R36p DIFFIO_RX_R35n DIFFIO_TX_R36n DIFFIO_RX_R37p DIFFIO_TX_R38p DIFFIO_RX_R37n DIFFIO_TX_R38n DIFFIO_RX_R39p DIFFIO_TX_R40p DIFFIO_RX_R39n DIFFIO_TX_R40n DIFFIO_RX_R41p DIFFIO_TX_R42p DIFFIO_RX_R41n DIFFIO_TX_R42n DIFFIO_RX_R43p DIFFIO_TX_R44p DIFFIO_RX_R43n DIFFIO_TX_R44n DIFFIO_RX_R45p DIFFIO_TX_R46p DIFFIO_RX_R45n DIFFIO_TX_R46n DIFFIO_RX_R47p DIFFIO_TX_R48p DIFFIO_RX_R47n DIFFIO_TX_R48n DIFFIO_RX_R49p DIFFIO_TX_R50p DIFFIO_RX_R49n DIFFIO_TX_R50n DIFFIO_RX_R51p DIFFIO_TX_R52p DIFFIO_RX_R51n DIFFIO_TX_R52n DIFFIO_RX_R53p DIFFIO_TX_R54p DIFFIO_RX_R53n DIFFIO_TX_R54n DIFFIO_RX_R55p DIFFIO_TX_R56p DIFFIO_RX_R55n DIFFIO_TX_R56n DIFFIO_RX_R57p DIFFIO_TX_R58p DIFFIO_RX_R57n DIFFIO_TX_R58n DIFFIO_RX_R59p DIFFIO_TX_R60p DIFFIO_RX_R59n DIFFIO_TX_R60n DIFFIO_RX_R61p DIFFIO_TX_R62p DIFFIO_RX_R61n DIFFIO_TX_R62n DIFFIO_RX_R63p DIFFIO_TX_R64p DIFFIO_RX_R63n DIFFIO_TX_R64n DIFFIO_RX_R65p DIFFIO_TX_R66p DIFFIO_RX_R65n DIFFIO_TX_R66n DIFFIO_RX_R67p DIFFIO_TX_R68p DIFFIO_RX_R67n DIFFIO_TX_R68n DIFFIO_RX_R69p DIFFOUT_R29n DIFFOUT_R30n DIFFOUT_R31p DIFFOUT_R32p DIFFOUT_R31n DIFFOUT_R32n DIFFOUT_R33p DIFFOUT_R34p DIFFOUT_R33n DIFFOUT_R34n DIFFOUT_R35p DIFFOUT_R36p DIFFOUT_R35n DIFFOUT_R36n DIFFOUT_R37p DIFFOUT_R38p DIFFOUT_R37n DIFFOUT_R38n DIFFOUT_R39p DIFFOUT_R40p DIFFOUT_R39n DIFFOUT_R40n DIFFOUT_R41p DIFFOUT_R42p DIFFOUT_R41n DIFFOUT_R42n DIFFOUT_R43p DIFFOUT_R44p DIFFOUT_R43n DIFFOUT_R44n DIFFOUT_R45p DIFFOUT_R46p DIFFOUT_R45n DIFFOUT_R46n DIFFOUT_R47p DIFFOUT_R48p DIFFOUT_R47n DIFFOUT_R48n DIFFOUT_R49p DIFFOUT_R50p DIFFOUT_R49n DIFFOUT_R50n DIFFOUT_R51p DIFFOUT_R52p DIFFOUT_R51n DIFFOUT_R52n DIFFOUT_R53p DIFFOUT_R54p DIFFOUT_R53n DIFFOUT_R54n DIFFOUT_R55p DIFFOUT_R56p DIFFOUT_R55n DIFFOUT_R56n DIFFOUT_R57p DIFFOUT_R58p DIFFOUT_R57n DIFFOUT_R58n DIFFOUT_R59p DIFFOUT_R60p DIFFOUT_R59n DIFFOUT_R60n DIFFOUT_R61p DIFFOUT_R62p DIFFOUT_R61n DIFFOUT_R62n DIFFOUT_R63p DIFFOUT_R64p DIFFOUT_R63n DIFFOUT_R64n DIFFOUT_R65p DIFFOUT_R66p DIFFOUT_R65n DIFFOUT_R66n DIFFOUT_R67p DIFFOUT_R68p DIFFOUT_R67n DIFFOUT_R68n DIFFOUT_R69p Y30 AF31 AC31 AN34 AC32 AM34 W26 AA31 W27 AB31 AK34 AH33 AJ34 AG33 W29 AD31 W30 AD32 W31 AE32 V31 AF32 V28 AG34 V27 AH34 AC33 AF33 AC34 AE33 V24 AE34 V23 AD34 W32 AB33 V32 AB34 U31 Y33 U30 AA33 U28 Y34 U29 W34 U24 V33 U25 V34 R34 U34 P34 U33 T31 T33 T30 T32 T27 M34 T28 M33 U23 K34 T23 J34 N33 L33 N34 L32 R32 K33 R33 K32 R27 H34 R28 H33 T25 DQSn4R DQ4R DQ4R DQ4R DQ4R DQSn2R DQ2R DQ2R DQ2R DQ2R Pin List EF35 DQ5R DQ2R DQ5R DQ5R DQ5R DQ5R DQ5R DQS5R DQ2R DQ2R DQ2R DQ2R DQ2R DQ2R DQSn5R DQ5R DQ5R DQ5R DQ5R DQ2R DQ2R DQ2R DQ2R DQ2R HMC Pin Assignment HMC Pin Assignment for DDR3/DDR2 (2) for LPDDR2 DQ6R DQ6R DQ6R DQ6R DQ6R DQ6R DQS6R DQSn6R DQ6R DQ6R DQ6R DQ6R DQ7R DQ7R DQ7R DQ7R DQ7R DQ7R DQS7R DQSn7R DQ7R DQ7R DQ7R DQ7R DQ8R DQ3R DQ8R DQ8R DQ8R DQ8R DQ8R DQS8R DQ3R DQ3R DQ3R DQ3R DQ3R DQS3R DQSn8R DQ8R DQ8R DQ8R DQ8R DQSn3R DQ3R DQ3R DQ3R DQ3R DQ9R DQ3R DQ9R DQ9R DQ9R DQ9R DQ9R DQS9R DQ3R DQ3R DQ3R DQ3R DQ3R DQ3R Page 40 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO GND IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F1152 DIFFIO_TX_R70p DIFFIO_RX_R69n DIFFIO_TX_R70n DIFFIO_RX_R71p DIFFIO_TX_R72p DIFFIO_RX_R71n DIFFIO_TX_R72n DIFFIO_RX_R73p DIFFIO_TX_R74p DIFFIO_RX_R73n DIFFIO_TX_R74n DIFFIO_RX_R75p DIFFIO_TX_R76p DIFFIO_RX_R75n DIFFIO_TX_R76n DIFFIO_RX_R77p DIFFIO_TX_R78p DIFFIO_RX_R77n DIFFIO_TX_R78n DIFFIO_RX_R79p DIFFIO_TX_R80p DIFFIO_RX_R79n DIFFIO_TX_R80n DIFFIO_RX_R81p DIFFIO_TX_R82p DIFFIO_RX_R81n DIFFIO_TX_R82n DIFFIO_RX_R83p DIFFIO_TX_R84p DIFFIO_RX_R83n DIFFIO_TX_R84n DIFFIO_RX_R85p DIFFIO_TX_R86p DIFFIO_RX_R85n DIFFIO_TX_R86n DIFFIO_RX_R87p DIFFIO_TX_R88p DIFFIO_RX_R87n DIFFIO_TX_R88n DIFFOUT_R70p DIFFOUT_R69n DIFFOUT_R70n DIFFOUT_R71p DIFFOUT_R72p DIFFOUT_R71n DIFFOUT_R72n DIFFOUT_R73p DIFFOUT_R74p DIFFOUT_R73n DIFFOUT_R74n DIFFOUT_R75p DIFFOUT_R76p DIFFOUT_R75n DIFFOUT_R76n DIFFOUT_R77p DIFFOUT_R78p DIFFOUT_R77n DIFFOUT_R78n DIFFOUT_R79p DIFFOUT_R80p DIFFOUT_R79n DIFFOUT_R80n DIFFOUT_R81p DIFFOUT_R82p DIFFOUT_R81n DIFFOUT_R82n DIFFOUT_R83p DIFFOUT_R84p DIFFOUT_R83n DIFFOUT_R84n DIFFOUT_R85p DIFFOUT_R86p DIFFOUT_R85n DIFFOUT_R86n DIFFOUT_R87p DIFFOUT_R88p DIFFOUT_R87n DIFFOUT_R88n DIFFIO_RX_T1p DIFFIO_TX_T2p DIFFIO_RX_T1n DIFFIO_TX_T2n DIFFIO_RX_T3p DIFFIO_TX_T4p DIFFIO_RX_T3n DIFFIO_TX_T4n DIFFIO_RX_T5p DIFFIO_TX_T6p DIFFIO_RX_T5n DIFFIO_TX_T6n DIFFIO_RX_T7p DIFFIO_TX_T8p DIFFIO_RX_T7n DIFFIO_TX_T8n DIFFIO_RX_T9p DIFFIO_TX_T10p DIFFIO_RX_T9n DIFFIO_TX_T10n DIFFIO_RX_T11p DIFFIO_TX_T12p DIFFIO_RX_T11n DIFFIO_TX_T12n DIFFIO_RX_T13p DIFFIO_TX_T14p DIFFIO_RX_T13n DIFFIO_TX_T14n DIFFIO_RX_T15p DIFFIO_TX_T16p DIFFIO_RX_T15n DIFFIO_TX_T16n DIFFIO_RX_T17p DIFFIO_TX_T18p DIFFIO_RX_T17n DIFFIO_TX_T18n DIFFIO_RX_T19p DIFFIO_TX_T20p DIFFIO_RX_T19n DIFFOUT_T1p DIFFOUT_T2p DIFFOUT_T1n DIFFOUT_T2n DIFFOUT_T3p DIFFOUT_T4p DIFFOUT_T3n DIFFOUT_T4n DIFFOUT_T5p DIFFOUT_T6p DIFFOUT_T5n DIFFOUT_T6n DIFFOUT_T7p DIFFOUT_T8p DIFFOUT_T7n DIFFOUT_T8n DIFFOUT_T9p DIFFOUT_T10p DIFFOUT_T9n DIFFOUT_T10n DIFFOUT_T11p DIFFOUT_T12p DIFFOUT_T11n DIFFOUT_T12n DIFFOUT_T13p DIFFOUT_T14p DIFFOUT_T13n DIFFOUT_T14n DIFFOUT_T15p DIFFOUT_T16p DIFFOUT_T15n DIFFOUT_T16n DIFFOUT_T17p DIFFOUT_T18p DIFFOUT_T17n DIFFOUT_T18n DIFFOUT_T19p DIFFOUT_T20p DIFFOUT_T19n N32 R25 N31 P32 G34 P31 G33 R30 M31 R29 L31 L30 J32 K30 H32 R23 J31 R24 H31 N28 P30 M28 N29 P27 G31 N27 G30 M29 J30 M30 J29 P24 H29 P25 H28 L28 K29 L27 K28 J26 K25 H27 J25 H26 G25 G28 F25 G29 M24 F26 N24 G26 G24 F30 H24 E30 M25 F27 L25 F28 D30 C32 D29 C31 L23 E29 K23 E28 H23 B31 G23 B30 L22 E24 K22 E25 F23 C29 F22 Pin List EF35 DQS for X8 DQS for X16 DQSn9R DQ9R DQ9R DQ9R DQ9R DQ3R DQ3R DQ3R DQ3R DQ3R DQ10R DQ4R DQ10R DQ10R DQ10R DQ10R DQ10R DQS10R DQ4R DQ4R DQ4R DQ4R DQ4R DQS4R DQSn10R DQ10R DQ10R DQ10R DQ10R DQSn4R DQ4R DQ4R DQ4R DQ4R DQ11R DQ4R DQ11R DQ11R DQ11R DQ11R DQ11R DQS11R DQ4R DQ4R DQ4R DQ4R DQ4R DQ4R DQSn11R DQ11R DQ11R DQ11R DQ11R DQ4R DQ4R DQ4R DQ4R DQ4R HMC Pin Assignment HMC Pin Assignment for DDR3/DDR2 (2) for LPDDR2 DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQS1T DQSn1T DQ1T DQ1T DQ1T DQ1T DQ2T DQ1T DQ2T DQ2T DQ2T DQ2T DQ2T DQS2T DQ1T DQ1T DQ1T DQ1T DQ1T DQS1T DQSn2T DQ2T DQ2T DQ2T DQ2T DQSn1T DQ1T DQ1T DQ1T DQ1T DQ3T DQ1T DQ3T DQ3T DQ3T DQ3T DQ1T DQ1T DQ1T DQ1T GND T_DM_4 GND T_DQ_39 T_DQ_37 T_DQ_38 T_DQ_36 GND T_DQS_4 GND T_DQS#_4 T_DQ_35 T_DQ_33 T_DQ_34 T_DQ_32 GND GND T_DM_3 GND T_DQ_31 T_DQ_29 T_DQ_30 T_DQ_28 GND T_DM_4 GND T_DQ_39 T_DQ_37 T_DQ_38 T_DQ_36 GND T_DQS_4 GND T_DQS#_4 T_DQ_35 T_DQ_33 T_DQ_34 T_DQ_32 GND GND T_DM_3 GND T_DQ_31 T_DQ_29 T_DQ_30 T_DQ_28 Page 41 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Optional Function(s) CLK11p CLK11n CLK10p CLK10n RZQ_2 CLK9p CLK9n FPLL_TL_CLKOUT0,FPLL_TL_CLKOUTp,FPLL_TL_FB FPLL_TL_CLKOUT1,FPLL_TL_CLKOUTn CLK8p,FPLL_TL_FBp CLK8n,FPLL_TL_FBn Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F1152 DQS for X8 DQS for X16 HMC Pin Assignment HMC Pin Assignment for DDR3/DDR2 (2) for LPDDR2 DIFFIO_TX_T20n DIFFIO_RX_T21p DIFFIO_TX_T22p DIFFIO_RX_T21n DIFFIO_TX_T22n DIFFIO_RX_T23p DIFFIO_TX_T24p DIFFIO_RX_T23n DIFFIO_TX_T24n DIFFIO_RX_T25p DIFFIO_TX_T26p DIFFIO_RX_T25n DIFFIO_TX_T26n DIFFIO_RX_T27p DIFFIO_TX_T28p DIFFIO_RX_T27n DIFFIO_TX_T28n DIFFIO_RX_T29p DIFFIO_TX_T30p DIFFIO_RX_T29n DIFFIO_TX_T30n DIFFIO_RX_T31p DIFFIO_TX_T32p DIFFIO_RX_T31n DIFFIO_TX_T32n DIFFIO_RX_T33p DIFFIO_TX_T34p DIFFIO_RX_T33n DIFFIO_TX_T34n DIFFIO_RX_T35p DIFFIO_TX_T36p DIFFIO_RX_T35n DIFFIO_TX_T36n DIFFIO_RX_T37p DIFFIO_TX_T38p DIFFIO_RX_T37n DIFFIO_TX_T38n DIFFIO_RX_T39p DIFFIO_TX_T40p DIFFIO_RX_T39n DIFFIO_TX_T40n DIFFIO_RX_T41p DIFFIO_TX_T42p DIFFIO_RX_T41n DIFFIO_TX_T42n DIFFIO_RX_T43p DIFFIO_TX_T44p DIFFIO_RX_T43n DIFFIO_TX_T44n DIFFIO_RX_T45p DIFFIO_TX_T46p DIFFIO_RX_T45n DIFFIO_TX_T46n DIFFIO_RX_T47p DIFFIO_TX_T48p DIFFIO_RX_T47n DIFFIO_TX_T48n DIFFIO_RX_T49p DIFFIO_TX_T50p DIFFIO_RX_T49n DIFFIO_TX_T50n DIFFIO_RX_T51p DIFFIO_TX_T52p DIFFIO_RX_T51n DIFFIO_TX_T52n DIFFIO_RX_T53p DIFFIO_TX_T54p DIFFIO_RX_T53n DIFFIO_TX_T54n DIFFIO_RX_T55p DIFFIO_TX_T56p DIFFIO_RX_T55n DIFFIO_TX_T56n DIFFIO_RX_T57p DIFFIO_TX_T58p DIFFIO_RX_T57n DIFFIO_TX_T58n DIFFIO_RX_T59p DIFFIO_TX_T60p DIFFOUT_T20n DIFFOUT_T21p DIFFOUT_T22p DIFFOUT_T21n DIFFOUT_T22n DIFFOUT_T23p DIFFOUT_T24p DIFFOUT_T23n DIFFOUT_T24n DIFFOUT_T25p DIFFOUT_T26p DIFFOUT_T25n DIFFOUT_T26n DIFFOUT_T27p DIFFOUT_T28p DIFFOUT_T27n DIFFOUT_T28n DIFFOUT_T29p DIFFOUT_T30p DIFFOUT_T29n DIFFOUT_T30n DIFFOUT_T31p DIFFOUT_T32p DIFFOUT_T31n DIFFOUT_T32n DIFFOUT_T33p DIFFOUT_T34p DIFFOUT_T33n DIFFOUT_T34n DIFFOUT_T35p DIFFOUT_T36p DIFFOUT_T35n DIFFOUT_T36n DIFFOUT_T37p DIFFOUT_T38p DIFFOUT_T37n DIFFOUT_T38n DIFFOUT_T39p DIFFOUT_T40p DIFFOUT_T39n DIFFOUT_T40n DIFFOUT_T41p DIFFOUT_T42p DIFFOUT_T41n DIFFOUT_T42n DIFFOUT_T43p DIFFOUT_T44p DIFFOUT_T43n DIFFOUT_T44n DIFFOUT_T45p DIFFOUT_T46p DIFFOUT_T45n DIFFOUT_T46n DIFFOUT_T47p DIFFOUT_T48p DIFFOUT_T47n DIFFOUT_T48n DIFFOUT_T49p DIFFOUT_T50p DIFFOUT_T49n DIFFOUT_T50n DIFFOUT_T51p DIFFOUT_T52p DIFFOUT_T51n DIFFOUT_T52n DIFFOUT_T53p DIFFOUT_T54p DIFFOUT_T53n DIFFOUT_T54n DIFFOUT_T55p DIFFOUT_T56p DIFFOUT_T55n DIFFOUT_T56n DIFFOUT_T57p DIFFOUT_T58p DIFFOUT_T57n DIFFOUT_T58n DIFFOUT_T59p DIFFOUT_T60p C28 M23 E27 N23 D26 H22 B28 H21 B29 L21 E22 L20 E23 F21 D27 G21 C27 N22 D25 M21 C26 F20 D24 G20 C24 J20 A28 K19 A27 D22 B26 C23 B25 M20 C22 M19 D21 E20 A26 D20 A25 H19 B23 H18 B24 C21 A23 B21 A22 M18 E19 L18 D19 B20 A21 B19 A20 G18 C18 F18 C17 E18 B18 E17 A18 M16 A17 L17 A16 C16 B15 B16 A15 H17 A12 H16 A11 F17 B13 DQ3T DQS3T DQ1T DQ1T DQSn3T DQ3T DQ3T DQ3T DQ3T DQ1T DQ1T DQ1T DQ1T DQ1T DQ4T DQ2T DQ4T DQ4T DQ4T DQ4T DQ4T DQS4T DQ2T DQ2T DQ2T DQ2T DQ2T DQS2T DQSn4T DQ4T DQ4T DQ4T DQ4T DQSn2T DQ2T DQ2T DQ2T DQ2T GND T_DQS_3 GND T_DQS#_3 T_DQ_27 T_DQ_25 T_DQ_26 T_DQ_24 GND GND T_DM_2 GND T_DQ_23 T_DQ_21 T_DQ_22 T_DQ_20 GND T_DQS_2 T_RESET# T_DQS#_2 T_DQ_19 T_DQ_17 T_DQ_18 T_DQ_16 GND GND T_DQS_3 GND T_DQS#_3 T_DQ_27 T_DQ_25 T_DQ_26 T_DQ_24 GND GND T_DM_2 GND T_DQ_23 T_DQ_21 T_DQ_22 T_DQ_20 GND T_DQS_2 T_RESET# T_DQS#_2 T_DQ_19 T_DQ_17 T_DQ_18 T_DQ_16 GND DQ5T DQ2T T_DM_1 T_DM_1 DQ5T DQ5T DQ5T DQ5T DQ5T DQS5T DQ2T DQ2T DQ2T DQ2T DQ2T DQ2T DQSn5T DQ5T DQ5T DQ5T DQ5T DQ2T DQ2T DQ2T DQ2T DQ2T T_DQ_15 T_DQ_13 T_DQ_14 T_DQ_12 T_CKE_0 T_DQS_1 T_CKE_1 T_DQS#_1 T_DQ_11 T_DQ_9 T_DQ_10 T_DQ_8 GND T_DQ_15 T_DQ_13 T_DQ_14 T_DQ_12 T_CKE_0 T_DQS_1 T_CKE_1 T_DQS#_1 T_DQ_11 T_DQ_9 T_DQ_10 T_DQ_8 GND DQ6T T_DM_0 T_DM_0 DQ6T DQ6T DQ6T DQ6T DQ6T DQS6T DQSn6T DQ6T DQ6T DQ6T DQ6T T_DQ_7 T_DQ_5 T_DQ_6 T_DQ_4 T_ODT_1 T_DQS_0 T_ODT_0 T_DQS#_0 T_DQ_3 T_DQ_1 T_DQ_2 T_DQ_0 T_DQ_7 T_DQ_5 T_DQ_6 T_DQ_4 T_ODT_1 T_DQS_0 T_ODT_0 T_DQS#_0 T_DQ_3 T_DQ_1 T_DQ_2 T_DQ_0 DQ7T T_A_0 T_CA_0 DQ7T DQ7T DQ7T DQ7T DQ7T DQS7T T_A_1 T_A_4 T_A_2 T_A_5 T_A_3 T_CK T_A_6 T_CK# T_A_7 T_BA_1 T_BA_0 T_BA_2 GND T_CA_1 T_CA_4 T_CA_2 T_CA_5 T_CA_3 T_CK T_CA_6 T_CK# T_CA_7 Pin List EF35 DQSn7T DQ7T DQ7T DQ7T DQ7T DQ8T DQ3T T_CAS# DQ8T DQ8T DQ8T DQ3T DQ3T DQ3T T_RAS# T_A_8 T_A_10 GND T_CA_8 Page 42 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 9A 9A 9A 9A 9A VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO MSEL0 CONF_DONE MSEL1 nSTATUS nCE PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F1152 DQS for X8 DQS for X16 HMC Pin Assignment HMC Pin Assignment for DDR3/DDR2 (2) for LPDDR2 DIFFIO_RX_T59n DIFFIO_TX_T60n DIFFIO_RX_T61p DIFFIO_TX_T62p DIFFIO_RX_T61n DIFFIO_TX_T62n DIFFIO_RX_T63p DIFFIO_TX_T64p DIFFIO_RX_T63n DIFFIO_TX_T64n DIFFIO_RX_T65p DIFFIO_TX_T66p DIFFIO_RX_T65n DIFFIO_TX_T66n DIFFIO_RX_T67p DIFFIO_TX_T68p DIFFIO_RX_T67n DIFFIO_TX_T68n DIFFIO_RX_T69p DIFFIO_TX_T70p DIFFIO_RX_T69n DIFFIO_TX_T70n DIFFIO_RX_T71p DIFFIO_TX_T72p DIFFIO_RX_T71n DIFFIO_TX_T72n DIFFIO_RX_T73p DIFFIO_TX_T74p DIFFIO_RX_T73n DIFFIO_TX_T74n DIFFIO_RX_T75p DIFFIO_TX_T76p DIFFIO_RX_T75n DIFFIO_TX_T76n DIFFIO_RX_T77p DIFFIO_TX_T78p DIFFIO_RX_T77n DIFFIO_TX_T78n DIFFIO_RX_T79p DIFFIO_TX_T80p DIFFIO_RX_T79n DIFFIO_TX_T80n DIFFIO_RX_T81p DIFFIO_TX_T82p DIFFIO_RX_T81n DIFFIO_TX_T82n DIFFIO_RX_T83p DIFFIO_TX_T84p DIFFIO_RX_T83n DIFFIO_TX_T84n DIFFIO_RX_T85p DIFFIO_TX_T86p DIFFIO_RX_T85n DIFFIO_TX_T86n DIFFIO_RX_T87p DIFFIO_TX_T88p DIFFIO_RX_T87n DIFFIO_TX_T88n DIFFIO_RX_T89p DIFFIO_TX_T90p DIFFIO_RX_T89n DIFFIO_TX_T90n DIFFIO_RX_T91p DIFFIO_TX_T92p DIFFIO_RX_T91n DIFFIO_TX_T92n DIFFIO_RX_T93p DIFFIO_TX_T94p DIFFIO_RX_T93n DIFFIO_TX_T94n DIFFIO_RX_T95p DIFFIO_TX_T96p DIFFIO_RX_T95n DIFFIO_TX_T96n DIFFOUT_T59n DIFFOUT_T60n DIFFOUT_T61p DIFFOUT_T62p DIFFOUT_T61n DIFFOUT_T62n DIFFOUT_T63p DIFFOUT_T64p DIFFOUT_T63n DIFFOUT_T64n DIFFOUT_T65p DIFFOUT_T66p DIFFOUT_T65n DIFFOUT_T66n DIFFOUT_T67p DIFFOUT_T68p DIFFOUT_T67n DIFFOUT_T68n DIFFOUT_T69p DIFFOUT_T70p DIFFOUT_T69n DIFFOUT_T70n DIFFOUT_T71p DIFFOUT_T72p DIFFOUT_T71n DIFFOUT_T72n DIFFOUT_T73p DIFFOUT_T74p DIFFOUT_T73n DIFFOUT_T74n DIFFOUT_T75p DIFFOUT_T76p DIFFOUT_T75n DIFFOUT_T76n DIFFOUT_T77p DIFFOUT_T78p DIFFOUT_T77n DIFFOUT_T78n DIFFOUT_T79p DIFFOUT_T80p DIFFOUT_T79n DIFFOUT_T80n DIFFOUT_T81p DIFFOUT_T82p DIFFOUT_T81n DIFFOUT_T82n DIFFOUT_T83p DIFFOUT_T84p DIFFOUT_T83n DIFFOUT_T84n DIFFOUT_T85p DIFFOUT_T86p DIFFOUT_T85n DIFFOUT_T86n DIFFOUT_T87p DIFFOUT_T88p DIFFOUT_T87n DIFFOUT_T88n DIFFOUT_T89p DIFFOUT_T90p DIFFOUT_T89n DIFFOUT_T90n DIFFOUT_T91p DIFFOUT_T92p DIFFOUT_T91n DIFFOUT_T92n DIFFOUT_T93p DIFFOUT_T94p DIFFOUT_T93n DIFFOUT_T94n DIFFOUT_T95p DIFFOUT_T96p DIFFOUT_T95n DIFFOUT_T96n F16 A13 M15 C14 M14 B14 D17 B10 D16 A10 F15 A7 G15 A6 B8 C11 A8 B11 L16 C9 L15 B9 E15 C13 D15 C12 J15 B5 K14 A5 E14 C6 D14 B6 P14 F13 N14 E13 H14 B4 G14 A3 M13 D11 L13 D10 G13 C8 H13 C7 N13 A2 N12 B3 E12 C1 D12 B1 L12 F10 K13 E10 F12 E9 F11 D9 L11 E7 K12 D7 H12 F8 G11 E8 J12 G10 J11 G9 F7 DQ8T DQ8T DQS8T DQ3T DQ3T DQS3T DQSn8T DQ8T DQ8T DQ8T DQ8T DQSn3T DQ3T DQ3T DQ3T DQ3T T_A_9 T_A_11 T_CS#_0 T_A_12 T_CS#_1 T_A_13 T_A_14 T_WE# T_A_15 GND DQ9T DQ3T DQ9T DQ9T DQ9T DQ9T DQ9T DQS9T DQ3T DQ3T DQ3T DQ3T DQ3T DQ3T DQSn9T DQ9T DQ9T DQ9T DQ9T DQ3T DQ3T DQ3T DQ3T DQ3T DQ10T DQ4T DQ10T DQ10T DQ10T DQ10T DQ10T DQS10T DQ4T DQ4T DQ4T DQ4T DQ4T DQS4T DQSn10T DQ10T DQ10T DQ10T DQ10T DQSn4T DQ4T DQ4T DQ4T DQ4T DQ11T DQ4T DQ11T DQ11T DQ11T DQ11T DQ11T DQS11T DQ4T DQ4T DQ4T DQ4T DQ4T DQ4T DQSn11T DQ11T DQ11T DQ11T DQ11T DQ4T DQ4T DQ4T DQ4T DQ4T MSEL0 CONF_DONE MSEL1 nSTATUS nCE Pin List EF35 T_CA_9 T_CS#_0 T_CS#_1 GND DQ12T DQ12T DQ12T DQ12T DQ12T DQ12T DQS12T DQSn12T DQ12T DQ12T DQ12T DQ12T Page 43 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number 9A 9A 9A 9A 9A PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. VREF Pin Name/Function MSEL2 MSEL3 nCONFIG MSEL4 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function Dedicated Tx/Rx Channel MSEL2 MSEL3 nCONFIG MSEL4 Emulated LVDS Output Channel F1152 DQS for X8 DQS for X16 HMC Pin Assignment HMC Pin Assignment for DDR3/DDR2 (2) for LPDDR2 F6 K10 G8 H7 H8 L24 AP2 AP4 AP8 AP13 AP18 AP23 AP28 AP33 AN6 AN15 AN25 AM3 AM12 AM22 AM32 AL5 AL9 AL19 AL29 AL34 AK1 AK2 AK3 AK6 AK16 AK26 AJ3 AJ4 AJ5 AJ13 AJ23 AJ33 AH1 AH2 AH5 AH10 AH20 AH30 AG3 AG4 AG5 AG6 AG7 AG17 AG27 AF1 AF2 AF5 AF6 AF7 AF14 AF24 AF34 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE11 AE21 AE31 AD1 AD2 AD5 AD6 AD7 AD9 AD10 AD18 AD28 AC3 Pin List EF35 Page 44 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Emulated LVDS Output Channel F1152 DQS for X8 DQS for X16 HMC Pin Assignment HMC Pin Assignment for DDR3/DDR2 (2) for LPDDR2 AC4 AC5 AC6 AC8 AC10 AC15 AC25 AB1 AB2 AB5 AB6 AB7 AB9 AB11 AB12 AB22 AB32 AA3 AA4 AA5 AA6 AA8 AA10 AA12 AA14 AA19 AA29 AA34 Y1 Y2 Y5 Y6 Y7 Y9 Y10 Y11 Y13 Y15 Y17 Y19 Y21 W3 W4 W5 W6 W8 W10 W12 W14 W16 W18 W20 W22 W23 W33 V1 V2 V5 V6 V7 V9 V11 V13 V15 V17 V19 V21 V30 U3 U4 U5 U6 U8 U10 U12 U14 U16 U18 U20 Pin List EF35 Page 45 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Emulated LVDS Output Channel F1152 DQS for X8 DQS for X16 HMC Pin Assignment HMC Pin Assignment for DDR3/DDR2 (2) for LPDDR2 U22 U27 T1 T2 T5 T6 T7 T9 T11 T13 T15 T17 T19 T21 T24 T34 R3 R4 R5 R6 R8 R10 R12 R14 R16 R18 R20 R22 R31 P1 P2 P5 P6 P7 P9 P11 P13 P15 P17 P19 P21 P28 N3 N4 N5 N6 N8 N10 N11 N16 N18 N20 N25 M1 M2 M5 M6 M7 M9 M10 M12 M17 M22 M32 L3 L4 L5 L6 L7 L8 L9 L14 L19 L29 L34 K1 K2 K5 K6 Pin List EF35 Page 46 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Emulated LVDS Output Channel F1152 DQS for X8 DQS for X16 HMC Pin Assignment HMC Pin Assignment for DDR3/DDR2 (2) for LPDDR2 K7 K8 K16 K26 J3 J4 J5 J13 J23 J33 H1 H2 H5 H10 H20 H30 G3 G4 G5 G7 G17 G27 F1 F2 F5 F14 F24 F34 E2 E3 E4 E5 E11 E21 E31 D1 D2 D5 D8 D18 D28 D33 C3 C4 C5 C15 C25 B2 B22 B32 B34 A4 A9 A19 A29 N21 AA13 Y12 Y14 Y16 Y18 W13 W15 W17 W19 W21 V12 V14 V16 V18 V20 V22 U13 U15 U17 U19 U21 T12 T14 Pin List EF35 Page 47 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC DNU DNU DNU DNU DNU DNU VCCPGM VCCPGM VCCPGM VCCBAT VCCIO3A VCCIO3A VCCIO3A VCCIO3A VCCIO3A VCCIO3A VCCIO3B VCCIO3B VCCIO3B VCCIO3B VCCIO3B VCCIO3B VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO5A VCCIO5A VCCIO5A VCCIO5A VCCIO5A VCCIO5A VCCIO5B VCCIO5B VCCIO5B VCCIO5B VCCIO5B VCCIO5B VCCIO6A VCCIO6A VCCIO6A VCCIO6A VCCIO6A VCCIO6A VCCIO6A VCCIO6A VCCIO6A VCCIO6A VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7A PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Emulated LVDS Output Channel F1152 DQS for X8 DQS for X16 HMC Pin Assignment HMC Pin Assignment for DDR3/DDR2 (2) for LPDDR2 T16 T18 T20 T22 R13 R15 R17 R19 R21 P12 P16 P18 P20 P22 N15 N17 N19 D4 D3 AG9 AF17 J24 J17 AF12 AD27 H11 H9 AD13 AM7 AK11 AJ8 AG12 AF9 AB17 AN10 AM17 AL14 AH15 AE16 AD23 AN20 AN30 AM27 AL24 AK21 AJ18 AJ28 AH25 AG22 AF19 AC20 AA24 AK31 AF29 AE26 AB27 Y26 V25 AG32 AD33 AC30 Y31 W28 G32 U32 T29 R26 P23 P33 N30 M27 K31 J28 A24 K21 J18 H25 G22 F19 Pin List EF35 Page 48 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number 3A 3B 4A 5A 5B 6A 7A 8A PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. VREF VREFB3AN0 VREFB3BN0 VREFB4AN0 VREFB5AN0 VREFB5BN0 VREFB6AN0 VREFB7AN0 VREFB8AN0 Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCPD3A VCCPD3A VCCPD3B4A VCCPD3B4A VCCPD3B4A VCCPD3B4A VCCPD3B4A VCCPD3B4A VCCPD5A VCCPD5A VCCPD5B VCCPD5B VCCPD6A VCCPD6A VCCPD6A VCCPD6A VCCPD7A8A VCCPD7A8A VCCPD7A8A VCCPD7A8A VCCPD7A8A VCCPD7A8A VCCPD7A8A VCCPD7A8A VREFB3AN0 VREFB3BN0 VREFB4AN0 VREFB5AN0 VREFB5BN0 VREFB6AN0 VREFB7AN0 VREFB8AN0 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Emulated LVDS Output Channel F1152 DQS for X8 DQS for X16 HMC Pin Assignment HMC Pin Assignment for DDR3/DDR2 (2) for LPDDR2 F29 E26 D23 C20 C30 B27 B17 K11 H15 G12 F9 E6 E16 D13 C10 B7 B12 A14 AE15 AE13 AE17 AF15 AF16 AF20 AF21 AE22 AA26 AB26 W25 V26 P26 U26 T26 N26 J22 K15 K17 K20 J14 J16 J19 J21 AH11 AH18 AG20 AE27 V29 P29 G19 G16 AP3 AN1 AN2 AN3 AM1 AM2 AL1 AL2 AL3 AL4 AK4 AH6 AH7 AG8 AF8 L10 L26 K9 K27 J6 J7 J8 J9 J27 H6 G6 F31 F32 F33 Pin List EF35 Page 49 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Note (1) Bank Number VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VCCH_GXBL VCCH_GXBL VCCH_GXBL VCCH_GXBL VCCL_GXBL VCCL_GXBL VCCL_GXBL VCCL_GXBL VCCL_GXBL VCCL_GXBL RREF_TL VCCA_FPLL VCCA_FPLL VCCA_FPLL VCCA_FPLL VCC_AUX VCC_AUX VCC_AUX VCC_AUX VCC_AUX VCC_AUX VCCE_GXBL VCCE_GXBL VCCE_GXBL VCCE_GXBL VCCE_GXBL VCCE_GXBL VCCE_GXBL VCCE_GXBL VCCE_GXBL Emulated LVDS Output Channel F1152 DQS for X8 DQS for X16 HMC Pin Assignment HMC Pin Assignment for DDR3/DDR2 (2) for LPDDR2 E32 E33 E34 D6 D31 D32 D34 C2 C19 C33 C34 B33 A30 A31 A32 A33 N9 AB8 W9 T8 N7 AC7 AA7 W7 U7 R7 E1 AC11 M11 AD26 M26 J10 K18 K24 AE24 AE18 AE12 P8 AD8 AC9 AA9 Y8 V8 U9 R9 M8 Notes: (1) For more information about pin definition and pin connection guidelines, refer to the Cyclone V Device Family Pin Connection Guidelines. (2) RESET pin is only applicable for DDR3 device. PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Pin List EF35 Page 50 of 51 Pin Information for the Cyclone® V 5CGTFD9 Device Version 1.1 Version Number Date 1.0 7/3/2012 1.1 5/22/2013 PT-5CGTFD9-1.1 Copyright © 2013 Altera Corp. Changes Made Initial release. - Added U484 package. - Updated the column from "HMC Pin Assignment for DDR3" to "HMC Pin Assignment for DDR3/DDR2". - Added notes to the "HMC Pin Assignment for DDR3/DDR2" and "HMC Pin Assignment for LPDDR2" columns. Revision History Page 51 of 51