Pin-Outs

Pin Information for the Arria® II GX EP2AGX260 Device
Version 1.1
Bank
number
QL3
QL3
QL3
QL3
QL3
QL3
QL3
QL3
QL3
QL3
QL3
QL3
QL3
QL3
QL3
QL3
QL3
QL3
QL3
QL3
QL2
QL2
QL2
QL2
QL2
QL2
QL2
QL2
QL2
QL2
QL2
QL2
QL2
QL2
QL2
QL2
QL2
QL2
QL2
QL2
QL1
QL1
QL1
QL1
QL1
QL1
QL1
QL1
QL1
QL1
QL1
QL1
QL1
QL1
QL1
QL1
QL1
QL1
QL1
QL1
QL0
QL0
QL0
QL0
QL0
QL0
QL0
QL0
QL0
QL0
QL0
QL0
QL0
QL0
QL0
QL0
QL0
QL0
QL0
QL0
3C
3C
3C
3C
3C
3C
3C
3C
3C
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
PT-EP2AGX260-1.1
Copyright © 2009 Altera Corp.
I/O Module
(Note 1)
BIO1
BIO1
BIO1
BIO1
BIO1
BIO1
BIO1
BIO1
BIO1
BIO1
BIO1
BIO1
BIO1
BIO1
BIO1
BIO1
BIO2
VREF
Pin Function
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
GXB_TX15n
GXB_TX15p
GXB_RX15n
GXB_RX15p
GXB_TX14n
GXB_TX14p
GXB_RX14n
GXB_RX14p
REFCLK7n
REFCLK7p
REFCLK3n
REFCLK3p
GXB_TX13n
GXB_TX13p
GXB_RX13n
GXB_RX13p
GXB_TX12n
GXB_TX12p
GXB_RX12n
GXB_RX12p
GXB_TX11n
GXB_TX11p
GXB_RX11n
GXB_RX11p
GXB_TX10n
GXB_TX10p
GXB_RX10n
GXB_RX10p
REFCLK6n
REFCLK6p
REFCLK2n
REFCLK2p
GXB_TX9n
GXB_TX9p
GXB_RX9n
GXB_RX9p
GXB_TX8n
GXB_TX8p
GXB_RX8n
GXB_RX8p
GXB_TX7n
GXB_TX7p
GXB_RX7n
GXB_RX7p
GXB_TX6n
GXB_TX6p
GXB_RX6n
GXB_RX6p
REFCLK5n
REFCLK5p
REFCLK1n
REFCLK1p
GXB_TX5n
GXB_TX5p
GXB_RX5n
GXB_RX5p
GXB_TX4n
GXB_TX4p
GXB_RX4n
GXB_RX4p
GXB_TX3n
GXB_TX3p
GXB_RX3n
GXB_RX3p
GXB_TX2n
GXB_TX2p
GXB_RX2n
GXB_RX2p
REFCLK4n
REFCLK4p
REFCLK0n
REFCLK0p
GXB_TX1n
GXB_TX1p
GXB_RX1n
GXB_RX1p
GXB_TX0n
GXB_TX0p
GXB_RX0n
GXB_RX0p
nCONFIG
CONF_DONE
MSEL3
MSEL2
MSEL1
MSEL0
nSTATUS
nIO_PULLUP
nCE
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Optional
Function
Configuration
Function
Dedicated Tx/Rx
Channel with
OCT Rd
Emulated LVDS Output Channel/
Dedicated LVDS Input Channel with
no OCT Rd (Note 2)
F1152
DIFFIN_B1n*
DIFFOUT_B1n
DIFFIN_B1p*
DIFFOUT_B1p
DIFFIN_B2n*
DIFFOUT_B2n
DIFFIN_B2p*
DIFFOUT_B2p
DIFFIN_B3n*
DIFFOUT_B3n
DIFFIN_B3p*
DIFFOUT_B3p
DIFFIN_B4n*
DIFFOUT_B4n
DIFFIN_B4p*
DIFFOUT_B4p
DIFFIN_B5n*
B32
B31
C34
C33
D32
D31
E34
E33
L30
L29
N30
N29
F32
F31
G34
G33
H32
H31
J34
J33
K32
K31
L34
L33
M32
M31
N34
N33
R30
R29
U30
U29
P32
P31
R34
R33
T32
T31
U34
U33
V32
V31
W34
W33
Y32
Y31
AA34
AA33
W30
W29
AA30
AA29
AB32
AB31
AC34
AC33
AD32
AD31
AE34
AE33
AF32
AF31
AG34
AG33
AH32
AH31
AJ34
AJ33
AC30
AC29
AE30
AE29
AK32
AK31
AL34
AL33
AM32
AM31
AN34
AN33
AC26
AE25
AB26
AD24
AC25
AC27
AD28
AC28
AB25
AH26
AG24
AG27
AF25
AD22
AF27
AC22
AE28
AH29
AE27
AH28
AE26
AF24
AG28
AE24
AF28
AJ29
nCONFIG
CONF_DONE
MSEL3
MSEL2
MSEL1
MSEL0
nSTATUS
nIO_PULLUP
nCE
DIFFIO_TX_B1n
DIFFIO_RX_B1n
DIFFIO_TX_B1p
DIFFIO_RX_B1p
DIFFIO_TX_B2n
DIFFIO_RX_B2n
DIFFIO_TX_B2p
DIFFIO_RX_B2p
DIFFIO_TX_B3n
DIFFIO_RX_B3n
DIFFIO_TX_B3p
DIFFIO_RX_B3p
DIFFIO_TX_B4n
DIFFIO_RX_B4n
DIFFIO_TX_B4p
DIFFIO_RX_B4p
DIFFIO_TX_B5n
F780
DQS for X4 for F1152
DQS for X8/X9 for
F1152 (Note 3)
DQS for X16/X18 for
F1152 (Note3)
DQ24B
DQ24B
DQ24B
DQ12B
DQ12B
DQ12B
DQ6B
DQ6B
DQ6B
DQSn24B
DQ24B
DQS24B
DQ12B
DQ12B
DQ12B/CQn12B
DQ6B
DQ6B
DQ6B
DQSn23B
DQ23B
DQS23B
DQSn12B/DQ12B
DQ12B
DQS12B/CQ12B
DQ6B
DQ6B
DQ6B
DQS for X32/X36 for
F1152 (Note 3)
DQS for X4 for F780
DQS for X8/X9 for F780 DQS for X16/X18 for
(Note 3)
F780 (Note 3)
DQS for X32/X36 for
F780 (Note 3)
C23
D23
A24
B24
A26
B26
C28
C27
D26
D25
E28
E27
F26
F25
G28
G27
H26
H25
J28
J27
K26
K25
L28
L27
M26
M25
N28
N27
P26
P25
R28
R27
T26
T25
U28
U27
V26
V25
W28
W27
Y26
Y25
AA28
AA27
AB26
AB25
AC28
AC27
AD26
AD25
AE28
AE27
AH27
AG27
AH25
AG25
AF24
AE24
AH23
AG23
AA24
AA23
AB24
Y24
Y23
W24
W23
AB22
AA22
DQ23B
DQ23B
DQ12B
DQ12B
DQ6B
DQ6B
DQ23B
DQ22B
DQ12B
DQ11B
DQ6B
DQ6B
Pin List
Page 1 of 15
®
Pin Information for the Arria II GX EP2AGX260 Device
Version 1.1
Bank
number
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
4A
3A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
PT-EP2AGX260-1.1
Copyright © 2009 Altera Corp.
I/O Module
(Note 1)
BIO2
BIO2
BIO2
BIO2
BIO2
BIO2
BIO2
BIO2
BIO2
BIO2
BIO2
BIO2
BIO2
BIO2
BIO2
BIO3
BIO3
BIO3
BIO3
BIO3
BIO3
BIO3
BIO3
BIO3
BIO3
BIO3
BIO3
BIO3
BIO3
BIO3
BIO3
BIO4
BIO4
BIO4
BIO4
BIO4
BIO4
BIO4
BIO4
BIO4
BIO4
BIO4
BIO4
BIO4
BIO4
BIO4
BIO4
BIO5
BIO5
BIO5
BIO5
BIO5
BIO5
BIO5
BIO5
BIO5
BIO5
BIO5
BIO5
BIO5
BIO5
BIO5
BIO5
BIO6
BIO6
BIO6
BIO6
BIO6
BIO6
BIO6
BIO6
BIO6
BIO6
BIO6
BIO6
BIO6
BIO6
BIO6
BIO6
BIO7
BIO7
BIO7
BIO7
BIO7
BIO7
BIO7
BIO7
BIO7
BIO7
BIO7
BIO7
BIO7
BIO7
BIO7
BIO7
BIO8
BIO8
BIO8
VREF
Pin Function
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB4AN0
VREFB3AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
CLK4
CLK5
CLK6
CLK7
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Optional
Function
Configuration
Function
Dedicated Tx/Rx
Channel with
OCT Rd
Emulated LVDS Output Channel/
Dedicated LVDS Input Channel with
no OCT Rd (Note 2)
DIFFIO_RX_B5n
DIFFIO_TX_B5p
DIFFIO_RX_B5p
DIFFIO_TX_B6n
DIFFIO_RX_B6n
DIFFIO_TX_B6p
DIFFIO_RX_B6p
DIFFIO_TX_B7n
DIFFIO_RX_B7n
DIFFIO_TX_B7p
DIFFIO_RX_B7p
DIFFIO_TX_B8n
DIFFIO_RX_B8n
DIFFIO_TX_B8p
DIFFIO_RX_B8p
DIFFOUT_B5n
DIFFIN_B5p*
DIFFOUT_B5p
DIFFIN_B6n*
DIFFOUT_B6n
DIFFIN_B6p*
DIFFOUT_B6p
DIFFIN_B7n*
DIFFOUT_B7n
DIFFIN_B7p*
DIFFOUT_B7p
DIFFIN_B8n*
DIFFOUT_B8n
DIFFIN_B8p*
DIFFOUT_B8p
PLL4_CLKOUT1n
RDN0
PLL4_CLKOUT1p
RUP0
INIT_DONE
nCEO
DIFFIO_TX_B9n
DIFFIO_RX_B9n
DIFFIO_TX_B9p
DIFFIO_RX_B9p
DIFFIO_TX_B10n
DIFFIO_RX_B10n
DIFFIO_TX_B10p
DIFFIO_RX_B10p
DIFFIO_TX_B11n
DIFFIO_RX_B11n
DIFFIO_TX_B11p
DIFFIO_RX_B11p
DIFFIO_TX_B12n
DIFFIO_RX_B12n
DIFFIO_TX_B12p
DIFFIO_RX_B12p
DIFFIO_TX_B13n
DIFFIO_RX_B13n
DIFFIO_TX_B13p
DIFFIO_RX_B13p
DIFFIO_TX_B14n
DIFFIO_RX_B14n
DIFFIO_TX_B14p
DIFFIO_RX_B14p
DIFFIO_TX_B15n
DIFFIO_RX_B15n
DIFFIO_TX_B15p
DIFFIO_RX_B15p
DIFFIO_TX_B16n
DIFFIO_RX_B16n
DIFFIO_TX_B16p
DIFFIO_RX_B16p
DIFFIO_TX_B17n
DIFFIO_RX_B17n
DIFFIO_TX_B17p
DIFFIO_RX_B17p
DIFFIO_TX_B18n
DIFFIO_RX_B18n
DIFFIO_TX_B18p
DIFFIO_RX_B18p
DIFFIO_TX_B19n
DIFFIO_RX_B19n
DIFFIO_TX_B19p
DIFFIO_RX_B19p
DIFFIO_TX_B20n
DIFFIO_RX_B20n
DIFFIO_TX_B20p
DIFFIO_RX_B20p
DIFFIO_TX_B21n
DIFFIO_RX_B21n
DIFFIO_TX_B21p
DIFFIO_RX_B21p
DIFFIO_TX_B22n
DIFFIO_RX_B22n
DIFFIO_TX_B22p
DIFFIO_RX_B22p
DIFFIO_TX_B23n
DIFFIO_RX_B23n
DIFFIO_TX_B23p
DIFFIO_RX_B23p
DIFFIO_TX_B24n
DIFFIO_RX_B24n
DIFFIO_TX_B24p
DIFFIO_RX_B24p
DIFFIN_B9n*
DIFFOUT_B9n
DIFFIN_B9p*
DIFFOUT_B9p
DIFFIN_B10n*
DIFFOUT_B10n
DIFFIN_B10p*
DIFFOUT_B10p
DIFFIN_B11n*
DIFFOUT_B11n
DIFFIN_B11p*
DIFFOUT_B11p
DIFFIN_B12n*
DIFFOUT_B12n
DIFFIN_B12p*
DIFFOUT_B12p
DIFFIN_B13n*
DIFFOUT_B13n
DIFFIN_B13p*
DIFFOUT_B13p
DIFFIN_B14n*
DIFFOUT_B14n
DIFFIN_B14p*
DIFFOUT_B14p
DIFFIN_B15n*
DIFFOUT_B15n
DIFFIN_B15p*
DIFFOUT_B15p
DIFFIN_B16n*
DIFFOUT_B16n
DIFFIN_B16p*
DIFFOUT_B16p
DIFFIN_B17n*
DIFFOUT_B17n
DIFFIN_B17p*
DIFFOUT_B17p
DIFFIN_B18n*
DIFFOUT_B18n
DIFFIN_B18p*
DIFFOUT_B18p
DIFFIN_B19n*
DIFFOUT_B19n
DIFFIN_B19p*
DIFFOUT_B19p
DIFFIN_B20n*
DIFFOUT_B20n
DIFFIN_B20p*
DIFFOUT_B20p
DIFFIN_B21n*
DIFFOUT_B21n
DIFFIN_B21p*
DIFFOUT_B21p
DIFFIN_B22n*
DIFFOUT_B22n
DIFFIN_B22p*
DIFFOUT_B22p
DIFFIN_B23n*
DIFFOUT_B23n
DIFFIN_B23p*
DIFFOUT_B23p
DIFFIN_B24n*
DIFFOUT_B24n
DIFFIN_B24p*
DIFFOUT_B24p
DIFFIO_TX_B25n
DIFFIO_RX_B25n
DIFFIO_TX_B25p
DIFFIO_RX_B25p
DIFFIO_TX_B26n
DIFFIO_RX_B26n
DIFFIO_TX_B26p
DIFFIO_RX_B26p
DIFFIO_TX_B27n
DIFFIO_RX_B27n
DIFFIO_TX_B27p
DIFFIO_RX_B27p
DIFFIO_TX_B28n
DIFFIO_RX_B28n
DIFFIO_TX_B28p
DIFFIO_RX_B28p
DIFFIO_TX_B29n
DIFFIO_RX_B29n
DIFFIO_TX_B29p
DIFFIN_B25n*
DIFFOUT_B25n
DIFFIN_B25p*
DIFFOUT_B25p
DIFFIN_B26n*
DIFFOUT_B26n
DIFFIN_B26p*
DIFFOUT_B26p
DIFFIN_B27n*
DIFFOUT_B27n
DIFFIN_B27p*
DIFFOUT_B27p
DIFFIN_B28n*
DIFFOUT_B28n
DIFFIN_B28p*
DIFFOUT_B28p
DIFFIN_B29n*
DIFFOUT_B29n
DIFFIN_B29p*
DIFFCLK_0n
DIFFCLK_1n
DIFFCLK_0p
DIFFCLK_1p
F1152
AJ27
AJ28
AH27
AF23
AL28
AE23
AK28
AK30
AK27
AJ30
AJ26
AE21
AH30
AD21
AG30
AH25
AL27
AH24
AL26
AM29
AM28
AL29
AM27
AJ25
AN28
AJ24
AN27
AM26
AK22
AM25
AJ22
AG21
AP29
AF20
AP28
AM24
AM23
AL24
AL23
AH21
AP27
AG22
AP26
AP24
AP25
AN24
AN25
AE19
AJ23
AD19
AH23
AL25
AM22
AK25
AL22
AJ21
AL21
AH20
AK21
AP22
AP23
AP21
AN22
AG19
AL20
AF19
AL19
AN21
AP20
AM21
AP19
AF18
AN19
AE18
AM19
AM18
AP18
AL18
AN18
AH19
AK18
AG18
AJ18
AK19
AP17
AJ19
AP16
AH18
AP15
AH17
AN16
AF17
AP14
AE17
AP13
AM17
AN15
AM16
AM15
AC18
AN13
AC17
AM13
AL16
AP12
AK16
F780
DQS for X4 for F1152
DQS for X8/X9 for
F1152 (Note 3)
DQS for X16/X18 for
F1152 (Note3)
DQ22B
DQ22B
DQ11B
DQ11B
DQ6B
DQ6B
DQS for X32/X36 for
F1152 (Note 3)
DQS for X4 for F780
DQS for X8/X9 for F780 DQS for X16/X18 for
(Note 3)
F780 (Note 3)
DQSn22B
DQ22B
DQS22B
DQ11B
DQ11B
DQ11B/CQn11B
DQ6B
DQ6B
DQ6B/CQn6B
DQSn21B
DQ21B
DQS21B
DQSn11B/DQ11B
DQ11B
DQS11B/CQ11B
DQSn6B/DQ6B
DQ6B
DQS6B/CQ6B
DQ21B
DQ21B
DQ11B
DQ11B
DQ6B
DQ6B
DQ21B
DQ11B
DQ6B
DQ20B
DQ20B
DQ20B
DQ10B
DQ10B
DQ10B
DQ5B
DQ5B
DQ5B
DQ2B
DQ2B
DQ2B
DQSn20B
DQ20B
DQS20B
DQ10B
DQ10B
DQ10B/CQn10B
DQ5B
DQ5B
DQ5B
DQ2B
DQ2B
DQ2B
DQSn19B
DQ19B
DQS19B
DQSn10B/DQ10B
DQ10B
DQS10B/CQ10B
DQ5B
DQ5B
DQ5B
DQ2B
DQ2B
DQ2B
DQ19B
DQ19B
DQ10B
DQ10B
DQ5B
DQ5B
DQ2B
DQ2B
DQ19B
DQ18B
DQ18B
DQ18B
DQ10B
DQ9B
DQ9B
DQ9B
DQ5B
DQ5B
DQ5B
DQ5B
DQ2B
DQ2B
DQ2B
DQ2B
DQ14B
DQ14B
DQ14B
DQ7B
DQ7B
DQ7B
DQSn18B
DQ18B
DQS18B
DQ9B
DQ9B
DQ9B/CQn9B
DQ5B
DQ5B
DQ5B/CQn5B
DQ2B
DQ2B
DQ2B
DQSn14B
DQ14B
DQS14B
DQ7B
DQ7B
DQ7B/CQn7B
DQSn17B
DQ17B
DQS17B
DQSn9B/DQ9B
DQ9B
DQS9B/CQ9B
DQSn5B/DQ5B
DQ5B
DQS5B/CQ5B
DQ2B
DQ2B
DQ2B
DQSn13B
DQ13B
DQS13B
DQSn7B/DQ7B
DQ7B
DQS7B/CQ7B
DQS for X32/X36 for
F780 (Note 3)
U24
AB19
V24
AC19
AD21
AC17
AC21
AB17
Y22
AC16
W21
AB16
AD23
AD18
AD22
AC18
Y20
AC23
Y19
AC22
AD24
AE22
AC24
AE21
V23
AF20
V22
AE20
AF18
AF19
AE18
AE19
AA16
AF17
Y16
AE17
AD15
AF16
AC15
AE16
AA19
AH19
Y18
AG19
AH17
AH18
AH16
AG18
AB15
AH15
AA15
AG15
AF15
AF14
AE15
AE14
AH14
AH12
AH13
AG12
Y14
AH11
Y13
AH10
AH8
AH9
AH7
AG9
AC14
AH6
AB14
AG6
AH5
AF13
AH4
DQ17B
DQ17B
DQ9B
DQ9B
DQ5B
DQ5B
DQ2B
DQ2B
DQ13B
DQ13B
DQ7B
DQ7B
DQ17B
DQ16B
DQ16B
DQ16B
DQ9B
DQ8B
DQ8B
DQ8B
DQ5B
DQ4B
DQ4B
DQ4B
DQ2B
DQ2B
DQ2B
DQ2B
DQ13B
DQ12B
DQ12B
DQ12B
DQ7B
DQ6B
DQ6B
DQ6B
DQ3B
DQ3B
DQ3B
DQSn16B
DQ16B
DQS16B
DQ8B
DQ8B
DQ8B/CQn8B
DQ4B
DQ4B
DQ4B
DQ2B
DQ2B
DQ2B/CQn2B
DQSn12B
DQ12B
DQS12B
DQ6B
DQ6B
DQ6B/CQn6B
DQ3B
DQ3B
DQ3B
DQSn15B
DQ15B
DQS15B
DQSn8B/DQ8B
DQ8B
DQS8B/CQ8B
DQ4B
DQ4B
DQ4B
DQSn2B/DQ2B
DQ2B
DQS2B/CQ2B
DQSn11B
DQ11B
DQS11B
DQSn6B/DQ6B
DQ6B
DQS6B/CQ6B
DQ3B
DQ3B
DQ3B
DQ15B
DQ15B
DQ8B
DQ8B
DQ4B
DQ4B
DQ2B
DQ2B
DQ11B
DQ11B
DQ6B
DQ6B
DQ3B
DQ3B
DQ15B
DQ14B
DQ14B
DQ14B
DQ8B
DQ7B
DQ7B
DQ7B
DQ4B
DQ4B
DQ4B
DQ4B
DQ2B
DQ2B
DQ2B
DQ2B
DQ11B
DQ10B
DQ10B
DQ10B
DQ6B
DQ5B
DQ5B
DQ5B
DQ3B
DQ3B
DQ3B
DQ3B
DQSn14B
DQ14B
DQS14B
DQ7B
DQ7B
DQ7B/CQn7B
DQ4B
DQ4B
DQ4B/CQn4B
DQ2B
DQ2B
DQ2B
DQSn10B
DQ10B
DQS10B
DQ5B
DQ5B
DQ5B/CQn5B
DQ3B
DQ3B
DQ3B/CQn3B
DQSn13B
DQ13B
DQS13B
DQSn7B/DQ7B
DQ7B
DQS7B/CQ7B
DQSn4B/DQ4B
DQ4B
DQS4B/CQ4B
DQ2B
DQ2B
DQ2B
DQSn9B
DQ9B
DQS9B
DQSn5B/DQ5B
DQ5B
DQS5B/CQ5B
DQSn3B/DQ3B
DQ3B
DQS3B/CQ3B
DQ13B
DQ13B
DQ7B
DQ7B
DQ4B
DQ4B
DQ2B
DQ2B
DQ9B
DQ9B
DQ5B
DQ5B
DQ3B
DQ3B
DQ13B
DQ7B
DQ4B
DQ2B
DQ9B
DQ5B
DQ3B
DQ12B
DQ12B
DQ12B
DQ6B
DQ6B
DQ6B
DQ3B
DQ3B
DQ3B
DQ1B
DQ1B
DQ1B
DQ8B
DQ8B
DQ8B
DQ4B
DQ4B
DQ4B
DQ2B
DQ2B
DQ2B
DQ1B
DQ1B
DQ1B
DQSn12B
DQ12B
DQS12B
DQ6B
DQ6B
DQ6B/CQn6B
DQ3B
DQ3B
DQ3B/CQn3B
DQ1B
DQ1B
DQ1B
DQSn8B
DQ8B
DQS8B
DQ4B
DQ4B
DQ4B/CQn4B
DQ2B
DQ2B
DQ2B/CQn2B
DQ1B
DQ1B
DQ1B
DQSn11B
DQ11B
DQS11B
DQSn6B/DQ6B
DQ6B
DQS6B/CQ6B
DQSn3B/DQ3B
DQ3B
DQS3B/CQ3B
DQ1B
DQ1B
DQ1B
DQSn7B
DQ7B
DQS7B
DQSn4B/DQ4B
DQ4B
DQS4B/CQ4B
DQSn2B/DQ2B
DQ2B
DQS2B/CQ2B
DQ1B
DQ1B
DQ1B
DQ11B
DQ11B
DQ6B
DQ6B
DQ3B
DQ3B
DQ1B
DQ1B
DQ7B
DQ7B
DQ4B
DQ4B
DQ2B
DQ2B
DQ1B
DQ1B
DQ11B
DQ10B
DQ10B
DQ10B
DQ6B
DQ5B
DQ5B
DQ5B
DQ3B
DQ3B
DQ3B
DQ3B
DQ1B
DQ1B
DQ1B
DQ1B
DQ7B
DQ6B
DQ6B
DQ6B
DQ4B
DQ3B
DQ3B
DQ3B
DQ2B
DQ2B
DQ2B
DQ2B
DQ1B
DQ1B
DQ1B
DQ1B
Pin List
Page 2 of 15
®
Pin Information for the Arria II GX EP2AGX260 Device
Version 1.1
Bank
number
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
5B
5B
5B
5B
5B
5B
5B
5B
5B
5B
5B
5B
5B
5B
5B
5B
5B
5B
5B
5B
5B
PT-EP2AGX260-1.1
Copyright © 2009 Altera Corp.
I/O Module
(Note 1)
BIO8
BIO8
BIO8
BIO8
BIO8
BIO8
BIO8
BIO8
BIO8
BIO8
BIO8
BIO8
BIO8
BIO9
BIO9
BIO9
BIO9
BIO9
BIO9
BIO9
BIO9
BIO9
BIO9
BIO9
BIO9
BIO9
BIO9
BIO9
BIO9
BIO10
BIO10
BIO10
BIO10
BIO10
BIO10
BIO10
BIO10
BIO10
BIO10
BIO10
BIO10
BIO10
BIO10
BIO10
BIO10
BIO11
BIO11
BIO11
BIO11
BIO11
BIO11
BIO11
BIO11
BIO11
BIO11
BIO11
BIO11
BIO11
BIO11
BIO11
BIO11
BIO12
BIO12
BIO12
BIO12
BIO12
BIO12
BIO12
BIO12
BIO12
BIO12
BIO12
BIO12
BIO12
BIO12
BIO12
BIO12
RIO1
RIO1
RIO1
RIO1
RIO1
RIO1
RIO1
RIO1
RIO1
RIO1
RIO1
RIO1
RIO1
RIO1
RIO1
RIO1
RIO2
RIO2
RIO2
RIO2
RIO2
VREF
Pin Function
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
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VREFB5BN0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Optional
Function
Configuration
Function
Dedicated Tx/Rx
Channel with
OCT Rd
Emulated LVDS Output Channel/
Dedicated LVDS Input Channel with
no OCT Rd (Note 2)
DIFFIO_RX_B29p
DIFFIO_TX_B30n
DIFFIO_RX_B30n
DIFFIO_TX_B30p
DIFFIO_RX_B30p
DIFFIO_TX_B31n
DIFFIO_RX_B31n
DIFFIO_TX_B31p
DIFFIO_RX_B31p
DIFFIO_TX_B32n
DIFFIO_RX_B32n
DIFFIO_TX_B32p
DIFFIO_RX_B32p
DIFFIO_TX_B33n
DIFFIO_RX_B33n
DIFFIO_TX_B33p
DIFFIO_RX_B33p
DIFFIO_TX_B34n
DIFFIO_RX_B34n
DIFFIO_TX_B34p
DIFFIO_RX_B34p
DIFFIO_TX_B35n
DIFFIO_RX_B35n
DIFFIO_TX_B35p
DIFFIO_RX_B35p
DIFFIO_TX_B36n
DIFFIO_RX_B36n
DIFFIO_TX_B36p
DIFFIO_RX_B36p
DIFFIO_TX_B37n
DIFFIO_RX_B37n
DIFFIO_TX_B37p
DIFFIO_RX_B37p
DIFFIO_TX_B38n
DIFFIO_RX_B38n
DIFFIO_TX_B38p
DIFFIO_RX_B38p
DIFFIO_TX_B39n
DIFFIO_RX_B39n
DIFFIO_TX_B39p
DIFFIO_RX_B39p
DIFFIO_TX_B40n
DIFFIO_RX_B40n
DIFFIO_TX_B40p
DIFFIO_RX_B40p
DIFFOUT_B29p
DIFFIN_B30n*
DIFFOUT_B30n
DIFFIN_B30p*
DIFFOUT_B30p
DIFFIN_B31n*
DIFFOUT_B31n
DIFFIN_B31p*
DIFFOUT_B31p
DIFFIN_B32n*
DIFFOUT_B32n
DIFFIN_B32p*
DIFFOUT_B32p
DIFFIN_B33n*
DIFFOUT_B33n
DIFFIN_B33p*
DIFFOUT_B33p
DIFFIN_B34n*
DIFFOUT_B34n
DIFFIN_B34p*
DIFFOUT_B34p
DIFFIN_B35n*
DIFFOUT_B35n
DIFFIN_B35p*
DIFFOUT_B35p
DIFFIN_B36n*
DIFFOUT_B36n
DIFFIN_B36p*
DIFFOUT_B36p
DIFFIN_B37n*
DIFFOUT_B37n
DIFFIN_B37p*
DIFFOUT_B37p
DIFFIN_B38n*
DIFFOUT_B38n
DIFFIN_B38p*
DIFFOUT_B38p
DIFFIN_B39n*
DIFFOUT_B39n
DIFFIN_B39p*
DIFFOUT_B39p
DIFFIN_B40n*
DIFFOUT_B40n
DIFFIN_B40p*
DIFFOUT_B40p
DIFFIO_RX_B41n
DIFFOUT_B41n
DIFFIO_RX_B41p
DIFFOUT_B41p
DIFFIO_TX_B41n
DIFFIO_RX_B42n
DIFFIO_TX_B41p
DIFFIO_RX_B42p
DIFFIO_TX_B42n
DIFFIO_RX_B43n
DIFFIO_TX_B42p
DIFFIO_RX_B43p
DIFFIO_TX_B43n
DIFFIO_RX_B44n
DIFFIO_TX_B43p
DIFFIO_RX_B44p
DIFFIO_TX_B44n
DIFFIO_RX_B45n
DIFFIO_TX_B44p
DIFFIO_RX_B45p
DIFFIO_TX_B45n
DIFFIO_RX_B46n
DIFFIO_TX_B45p
DIFFIO_RX_B46p
DIFFIO_TX_B46n
DIFFIO_RX_B47n
DIFFIO_TX_B46p
DIFFIO_RX_B47p
DIFFIO_TX_B47n
DIFFIO_RX_B48n
DIFFIO_TX_B47p
DIFFIO_RX_B48p
DIFFIO_TX_B48n
DIFFIO_RX_B49n
DIFFIO_TX_B48p
DIFFIO_RX_B49p
DIFFIO_TX_R1n
DIFFIO_RX_R1n
DIFFIO_TX_R1p
DIFFIO_RX_R1p
DIFFIO_TX_R2n
DIFFIO_RX_R2n
DIFFIO_TX_R2p
DIFFIO_RX_R2p
DIFFIO_TX_R3n
DIFFIO_RX_R3n
DIFFIO_TX_R3p
DIFFIO_RX_R3p
DIFFIO_TX_R4n
DIFFIO_RX_R4n
DIFFIO_TX_R4p
DIFFIO_RX_R4p
DIFFIO_TX_R5n
DIFFIO_RX_R5n
DIFFIO_TX_R5p
DIFFIO_RX_R5p
DIFFIO_TX_R6n
DIFFIN_B41n*
DIFFOUT_B42n
DIFFIN_B41p*
DIFFOUT_B42p
DIFFIN_B42n*
DIFFOUT_B43n
DIFFIN_B42p*
DIFFOUT_B43p
DIFFIN_B43n*
DIFFOUT_B44n
DIFFIN_B43p*
DIFFOUT_B44p
DIFFIN_B44n*
DIFFOUT_B45n
DIFFIN_B44p*
DIFFOUT_B45p
DIFFIN_B45n*
DIFFOUT_B46n
DIFFIN_B45p*
DIFFOUT_B46p
DIFFIN_B46n*
DIFFOUT_B47n
DIFFIN_B46p*
DIFFOUT_B47p
DIFFIN_B47n*
DIFFOUT_B48n
DIFFIN_B47p*
DIFFOUT_B48p
DIFFIN_B48n*
DIFFOUT_B49n
DIFFIN_B48p*
DIFFOUT_B49p
DIFFIN_R1n*
DIFFOUT_R1n
DIFFIN_R1p*
DIFFOUT_R1p
DIFFIN_R2n*
DIFFOUT_R2n
DIFFIN_R2p*
DIFFOUT_R2p
DIFFIN_R3n*
DIFFOUT_R3n
DIFFIN_R3p*
DIFFOUT_R3p
DIFFIN_R4n*
DIFFOUT_R4n
DIFFIN_R4p*
DIFFOUT_R4p
DIFFIN_R5n*
DIFFOUT_R5n
DIFFIN_R5p*
DIFFOUT_R5p
DIFFIN_R6n*
PLL3_CLKOUT1n
PLL3_CLKOUT1p
PLL3_CLKOUT2n
PLL3_CLKOUT3n
PLL3_CLKOUT2p
PLL3_CLKOUT3p
F1152
F780
AP11
AH16
AN12
AG16
AM12
AL15
AP10
AK15
AN10
AH15
AP9
AG15
AP8
AP7
AL14
AN7
AL13
AF16
AP6
AE16
AN6
AL12
AP5
AK13
AP4
AC15
AL11
AC14
AK12
AP3
AN9
AP2
AM9
AF15
AM10
AE15
AL10
AM8
AN4
AM7
AN3
AJ16
AJ12
AJ15
AJ11
AJ13
AH13
AH14
AG13
AF14
AH12
AE14
AG12
AK10
AL9
AJ10
AK9
AF13
AL8
AE13
AL7
AL6
AM6
AK6
AM5
AF12
AK7
AE12
AJ7
AM4
AJ9
AL5
AH9
AE11
AH10
AD12
AG9
AM2
AM3
AL3
AL4
AG10
AN1
AF11
AM1
AJ6
AF7
AH7
AF8
AD9
AK3
AD10
AK4
AH5
AG6
AH6
AG7
AE7
AL1
AE8
AL2
AK1
AJ3
AJ1
AJ4
AC10
AE13
AC13
AF12
AB13
AE12
AF10
AF11
AE10
AE11
W13
AF9
W12
AE9
AF8
AF7
AE8
AE7
Y12
AF6
W11
AE6
AD12
AF5
AC12
AE5
AC11
AG4
AB11
AG3
AH3
AF4
AH2
AE4
Y11
AF3
W10
AF2
AD6
AG1
AC6
AF1
AA10
AD9
Y10
AC9
AC10
AD7
AB10
AC7
AB9
AC8
AA9
AB8
DQS for X4 for F1152
DQS for X8/X9 for
F1152 (Note 3)
DQS for X16/X18 for
F1152 (Note3)
DQS for X32/X36 for
F1152 (Note 3)
DQS for X4 for F780
DQS for X8/X9 for F780 DQS for X16/X18 for
(Note 3)
F780 (Note 3)
DQS for X32/X36 for
F780 (Note 3)
DQSn10B
DQ10B
DQS10B
DQ5B
DQ5B
DQ5B/CQn5B
DQ3B
DQ3B
DQ3B
DQ1B
DQ1B
DQ1B/CQn1B
DQSn6B
DQ6B
DQS6B
DQ3B
DQ3B
DQ3B/CQn3B
DQ2B
DQ2B
DQ2B
DQ1B
DQ1B
DQ1B/CQn1B
DQSn9B
DQ9B
DQS9B
DQSn5B/DQ5B
DQ5B
DQS5B/CQ5B
DQ3B
DQ3B
DQ3B
DQSn1B/DQ1B
DQ1B
DQS1B/CQ1B
DQSn5B
DQ5B
DQS5B
DQSn3B/DQ3B
DQ3B
DQS3B/CQ3B
DQ2B
DQ2B
DQ2B
DQSn1B/DQ1B
DQ1B
DQS1B/CQ1B
DQ9B
DQ9B
DQ5B
DQ5B
DQ3B
DQ3B
DQ1B
DQ1B
DQ5B
DQ5B
DQ3B
DQ3B
DQ2B
DQ2B
DQ1B
DQ1B
DQ9B
DQ8B
DQ8B
DQ8B
DQ5B
DQ4B
DQ4B
DQ4B
DQ3B
DQ2B
DQ2B
DQ2B
DQ1B
DQ1B
DQ1B
DQ1B
DQ5B
DQ4B
DQ4B
DQ4B
DQ3B
DQ2B
DQ2B
DQ2B
DQ2B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQSn8B
DQ8B
DQS8B
DQ4B
DQ4B
DQ4B/CQn4B
DQ2B
DQ2B
DQ2B/CQn2B
DQ1B
DQ1B
DQ1B
DQSn4B
DQ4B
DQS4B
DQ2B
DQ2B
DQ2B/CQn2B
DQ1B
DQ1B
DQ1B/CQn1B
DQ1B
DQ1B
DQ1B
DQSn7B
DQ7B
DQS7B
DQSn4B/DQ4B
DQ4B
DQS4B/CQ4B
DQSn2B/DQ2B
DQ2B
DQS2B/CQ2B
DQ1B
DQ1B
DQ1B
DQSn3B
DQ3B
DQS3B
DQSn2B/DQ2B
DQ2B
DQS2B/CQ2B
DQSn1B/DQ1B
DQ1B
DQS1B/CQ1B
DQ1B
DQ1B
DQ1B
DQ7B
DQ7B
DQ4B
DQ4B
DQ2B
DQ2B
DQ1B
DQ1B
DQ3B
DQ3B
DQ2B
DQ2B
DQ1B
DQ1B
DQ1B
DQ1B
DQ7B
DQ6B
DQ6B
DQ6B
DQ4B
DQ3B
DQ3B
DQ3B
DQ2B
DQ2B
DQ2B
DQ2B
DQ1B
DQ1B
DQ1B
DQ1B
DQ3B
DQ2B
DQ2B
DQ2B
DQ2B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQSn6B
DQ6B
DQS6B
DQ3B
DQ3B
DQ3B/CQn3B
DQ2B
DQ2B
DQ2B
DQ1B
DQ1B
DQ1B
DQSn2B
DQ2B
DQS2B
DQ1B
DQ1B
DQ1B/CQn1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQSn5B
DQ5B
DQS5B
DQSn3B/DQ3B
DQ3B
DQS3B/CQ3B
DQ2B
DQ2B
DQ2B
DQ1B
DQ1B
DQ1B
DQSn1B
DQ1B
DQS1B
DQSn1B/DQ1B
DQ1B
DQS1B/CQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ5B
DQ5B
DQ3B
DQ3B
DQ2B
DQ2B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ5B
DQ3B
DQ2B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ4B
DQ4B
DQ4B
DQ2B
DQ2B
DQ2B
DQ1B
DQ1B
DQ1B
DQSn4B
DQ4B
DQS4B
DQ2B
DQ2B
DQ2B/CQn2B
DQ1B
DQ1B
DQ1B/CQn1B
DQSn3B
DQ3B
DQS3B
DQSn2B/DQ2B
DQ2B
DQS2B/CQ2B
DQSn1B/DQ1B
DQ1B
DQS1B/CQ1B
DQ3B
DQ3B
DQ2B
DQ2B
DQ1B
DQ1B
DQ3B
DQ2B
DQ2B
DQ2B
DQ2B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQSn2B
DQ2B
DQS2B
DQ1B
DQ1B
DQ1B/CQn1B
DQ1B
DQ1B
DQ1B
DQSn1B
DQ1B
DQS1B
DQSn1B/DQ1B
DQ1B
DQS1B/CQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ24R
DQ24R
DQ24R
DQ1B
DQ12R
DQ12R
DQ12R
DQ1B
DQ6R
DQ6R
DQ6R
DQSn24R
DQ24R
DQS24R
DQ12R
DQ12R
DQ12R/CQn12R
DQ6R
DQ6R
DQ6R
DQSn23R
DQ23R
DQS23R
DQSn12R/DQ12R
DQ12R
DQS12R/CQ12R
DQ6R
DQ6R
DQ6R
DQ23R
DQ23R
DQ12R
DQ12R
DQ6R
DQ6R
DQ23R
DQ22R
DQ22R
DQ22R
DQ12R
DQ11R
DQ11R
DQ11R
DQ6R
DQ6R
DQ6R
DQ6R
DQSn22R
DQ11R
DQ6R
Pin List
Page 3 of 15
®
Pin Information for the Arria II GX EP2AGX260 Device
Version 1.1
Bank
number
5B
5B
5B
5B
5B
5B
5B
5B
5B
5B
5B
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
PT-EP2AGX260-1.1
Copyright © 2009 Altera Corp.
I/O Module
(Note 1)
RIO2
RIO2
RIO2
RIO2
RIO2
RIO2
RIO2
RIO2
RIO2
RIO2
RIO2
RIO3
RIO3
RIO3
RIO3
RIO3
RIO3
RIO3
RIO3
RIO3
RIO3
RIO3
RIO3
RIO3
RIO3
RIO3
RIO3
RIO4
RIO4
RIO4
RIO4
RIO4
RIO4
RIO4
RIO4
RIO4
RIO4
RIO4
RIO4
RIO4
RIO4
RIO4
RIO4
RIO5
RIO5
RIO5
RIO5
RIO5
RIO5
RIO5
RIO5
RIO5
RIO5
RIO5
RIO5
RIO5
RIO5
RIO5
RIO5
RIO6
RIO6
RIO6
RIO6
RIO6
RIO6
RIO6
RIO6
RIO6
RIO6
RIO6
RIO6
RIO6
RIO6
RIO6
RIO6
RIO7
RIO7
RIO7
RIO7
RIO7
RIO7
RIO7
RIO7
RIO7
RIO7
RIO7
RIO7
RIO7
RIO7
RIO7
RIO7
RIO8
RIO8
RIO8
RIO8
RIO8
RIO8
RIO8
RIO8
RIO8
RIO8
RIO8
VREF
Pin Function
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
CLK8
CLK10
CLK9
CLK11
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Optional
Function
Configuration
Function
Dedicated Tx/Rx
Channel with
OCT Rd
Emulated LVDS Output Channel/
Dedicated LVDS Input Channel with
no OCT Rd (Note 2)
DIFFIO_RX_R6n
DIFFIO_TX_R6p
DIFFIO_RX_R6p
DIFFIO_TX_R7n
DIFFIO_RX_R7n
DIFFIO_TX_R7p
DIFFIO_RX_R7p
DIFFIO_TX_R8n
DIFFIO_RX_R8n
DIFFIO_TX_R8p
DIFFIO_RX_R8p
DIFFIO_TX_R9n
DIFFIO_RX_R9n
DIFFIO_TX_R9p
DIFFIO_RX_R9p
DIFFIO_TX_R10n
DIFFIO_RX_R10n
DIFFIO_TX_R10p
DIFFIO_RX_R10p
DIFFIO_TX_R11n
DIFFIO_RX_R11n
DIFFIO_TX_R11p
DIFFIO_RX_R11p
DIFFIO_TX_R12n
DIFFIO_RX_R12n
DIFFIO_TX_R12p
DIFFIO_RX_R12p
DIFFIO_TX_R13n
DIFFIO_RX_R13n
DIFFIO_TX_R13p
DIFFIO_RX_R13p
DIFFIO_TX_R14n
DIFFIO_RX_R14n
DIFFIO_TX_R14p
DIFFIO_RX_R14p
DIFFIO_TX_R15n
DIFFIO_RX_R15n
DIFFIO_TX_R15p
DIFFIO_RX_R15p
DIFFIO_TX_R16n
DIFFIO_RX_R16n
DIFFIO_TX_R16p
DIFFIO_RX_R16p
DIFFIO_TX_R17n
DIFFIO_RX_R17n
DIFFIO_TX_R17p
DIFFIO_RX_R17p
DIFFIO_TX_R18n
DIFFIO_RX_R18n
DIFFIO_TX_R18p
DIFFIO_RX_R18p
DIFFIO_TX_R19n
DIFFIO_RX_R19n
DIFFIO_TX_R19p
DIFFIO_RX_R19p
DIFFIO_TX_R20n
DIFFIO_RX_R20n
DIFFIO_TX_R20p
DIFFIO_RX_R20p
DIFFIO_TX_R21n
DIFFIO_RX_R21n
DIFFIO_TX_R21p
DIFFIO_RX_R21p
DIFFIO_TX_R22n
DIFFIO_RX_R22n
DIFFIO_TX_R22p
DIFFIO_RX_R22p
DIFFIO_TX_R23n
DIFFIO_RX_R23n
DIFFIO_TX_R23p
DIFFIO_RX_R23p
DIFFIO_TX_R24n
DIFFIO_RX_R24n
DIFFIO_TX_R24p
DIFFIO_RX_R24p
DIFFOUT_R6n
DIFFIN_R6p*
DIFFOUT_R6p
DIFFIN_R7n*
DIFFOUT_R7n
DIFFIN_R7p*
DIFFOUT_R7p
DIFFIN_R8n*
DIFFOUT_R8n
DIFFIN_R8p*
DIFFOUT_R8p
DIFFIN_R9n*
DIFFOUT_R9n
DIFFIN_R9p*
DIFFOUT_R9p
DIFFIN_R10n*
DIFFOUT_R10n
DIFFIN_R10p*
DIFFOUT_R10p
DIFFIN_R11n*
DIFFOUT_R11n
DIFFIN_R11p*
DIFFOUT_R11p
DIFFIN_R12n*
DIFFOUT_R12n
DIFFIN_R12p*
DIFFOUT_R12p
DIFFIN_R13n*
DIFFOUT_R13n
DIFFIN_R13p*
DIFFOUT_R13p
DIFFIN_R14n*
DIFFOUT_R14n
DIFFIN_R14p*
DIFFOUT_R14p
DIFFIN_R15n*
DIFFOUT_R15n
DIFFIN_R15p*
DIFFOUT_R15p
DIFFIN_R16n*
DIFFOUT_R16n
DIFFIN_R16p*
DIFFOUT_R16p
DIFFIN_R17n*
DIFFOUT_R17n
DIFFIN_R17p*
DIFFOUT_R17p
DIFFIN_R18n*
DIFFOUT_R18n
DIFFIN_R18p*
DIFFOUT_R18p
DIFFIN_R19n*
DIFFOUT_R19n
DIFFIN_R19p*
DIFFOUT_R19p
DIFFIN_R20n*
DIFFOUT_R20n
DIFFIN_R20p*
DIFFOUT_R20p
DIFFIN_R21n*
DIFFOUT_R21n
DIFFIN_R21p*
DIFFOUT_R21p
DIFFIN_R22n*
DIFFOUT_R22n
DIFFIN_R22p*
DIFFOUT_R22p
DIFFIN_R23n*
DIFFOUT_R23n
DIFFIN_R23p*
DIFFOUT_R23p
DIFFIN_R24n*
DIFFOUT_R24n
DIFFIN_R24p*
DIFFOUT_R24p
DIFFIO_TX_R25n
DIFFIO_RX_R25n
DIFFIO_TX_R25p
DIFFIO_RX_R25p
DIFFIO_TX_R26n
DIFFIO_RX_R26n
DIFFIO_TX_R26p
DIFFIO_RX_R26p
DIFFIO_TX_R27n
DIFFIO_RX_R27n
DIFFIO_TX_R27p
DIFFIO_RX_R27p
DIFFIO_TX_R28n
DIFFIO_RX_R28n
DIFFIO_TX_R28p
DIFFIO_RX_R28p
DIFFIO_TX_R29n
DIFFIO_RX_R29n
DIFFIO_TX_R29p
DIFFIO_RX_R29p
DIFFIO_TX_R30n
DIFFIO_RX_R30n
DIFFIO_TX_R30p
DIFFIO_RX_R30p
DIFFIO_TX_R31n
DIFFIO_RX_R31n
DIFFIO_TX_R31p
DIFFIN_R25n*
DIFFOUT_R25n
DIFFIN_R25p*
DIFFOUT_R25p
DIFFIN_R26n*
DIFFOUT_R26n
DIFFIN_R26p*
DIFFOUT_R26p
DIFFIN_R27n*
DIFFOUT_R27n
DIFFIN_R27p*
DIFFOUT_R27p
DIFFIN_R28n*
DIFFOUT_R28n
DIFFIN_R28p*
DIFFOUT_R28p
DIFFIN_R29n*
DIFFOUT_R29n
DIFFIN_R29p*
DIFFOUT_R29p
DIFFIN_R30n*
DIFFOUT_R30n
DIFFIN_R30p*
DIFFOUT_R30p
DIFFIN_R31n*
DIFFOUT_R31n
DIFFIN_R31p*
DIFFCLK_2n
DIFFCLK_2p
DIFFCLK_3n
DIFFCLK_3p
F1152
AJ2
AC11
AH3
AF5
AH4
AF6
AG4
AC8
AE5
AC9
AE6
AD6
AC6
AD7
AC7
AB9
AB7
AB10
AB8
AH1
AF4
AH2
AE4
Y6
AG1
AA7
AF1
AF2
AE1
AF3
AE2
AA9
AB5
AA10
AB6
AE3
AC4
AD4
AC5
Y7
AD1
Y8
AC1
AC2
AB3
AC3
AB4
Y10
AB1
Y11
AB2
AA4
AA1
Y5
Y1
Y9
Y3
W10
Y4
W6
W1
W7
Y2
V10
W3
V11
W4
V3
V1
V4
V2
W12
V7
V12
U7
V5
V6
U5
U6
T7
U1
R7
U2
U10
T1
U11
R1
P1
U3
R2
U4
V9
N1
U9
N2
T4
R5
R4
R6
R10
M1
R11
M2
L1
R3
K1
F780
AA6
AD4
AB7
AC5
W8
AB5
Y9
AB6
AC4
Y5
AB4
Y6
W6
AE3
V7
AD3
AC2
AA3
AC3
AA4
V6
W4
U6
W5
AB2
Y3
AB3
Y4
T6
AE1
T7
AD1
AC1
AA1
AB1
Y1
N4
V3
P5
V4
W1
W2
V1
W3
R6
U4
P6
U5
U3
T3
T4
R3
N6
U1
M6
T1
R1
R4
P1
R5
M5
P3
L6
P4
P2
N3
N1
M1
L1
M2
K1
L3
K6
M3
L7
M4
J2
J1
J3
H1
J6
K3
J7
L4
G1
E1
F1
F2
K7
D1
J8
C1
J4
H3
J5
DQS for X4 for F1152
DQS for X8/X9 for
F1152 (Note 3)
DQS for X16/X18 for
F1152 (Note3)
DQ22R
DQS22R
DQ11R
DQ11R/CQn11R
DQ6R
DQ6R/CQn6R
DQS for X32/X36 for
F1152 (Note 3)
DQS for X4 for F780
DQS for X8/X9 for F780 DQS for X16/X18 for
(Note 3)
F780 (Note 3)
DQS for X32/X36 for
F780 (Note 3)
DQSn21R
DQ21R
DQS21R
DQSn11R/DQ11R
DQ11R
DQS11R/CQ11R
DQSn6R/DQ6R
DQ6R
DQS6R/CQ6R
DQ21R
DQ21R
DQ11R
DQ11R
DQ6R
DQ6R
DQ21R
DQ20R
DQ20R
DQ20R
DQ11R
DQ10R
DQ10R
DQ10R
DQ6R
DQ5R
DQ5R
DQ5R
DQ2R
DQ2R
DQ2R
DQ14R
DQ14R
DQ14R
DQ7R
DQ7R
DQ7R
DQ3R
DQ3R
DQ3R
DQ1R
DQ1R
DQ1R
DQSn20R
DQ20R
DQS20R
DQ10R
DQ10R
DQ10R/CQn10R
DQ5R
DQ5R
DQ5R
DQ2R
DQ2R
DQ2R
DQSn14R
DQ14R
DQS14R
DQ7R
DQ7R
DQ7R/CQn7R
DQ3R
DQ3R
DQ3R
DQ1R
DQ1R
DQ1R
DQSn19R
DQ19R
DQS19R
DQSn10R/DQ10R
DQ10R
DQS10R/CQ10R
DQ5R
DQ5R
DQ5R
DQ2R
DQ2R
DQ2R
DQSn13R
DQ13R
DQS13R
DQSn7R/DQ7R
DQ7R
DQS7R/CQ7R
DQ3R
DQ3R
DQ3R
DQ1R
DQ1R
DQ1R
DQ19R
DQ19R
DQ10R
DQ10R
DQ5R
DQ5R
DQ2R
DQ2R
DQ13R
DQ13R
DQ7R
DQ7R
DQ3R
DQ3R
DQ1R
DQ1R
DQ19R
DQ18R
DQ18R
DQ18R
DQ10R
DQ9R
DQ9R
DQ9R
DQ5R
DQ5R
DQ5R
DQ5R
DQ2R
DQ2R
DQ2R
DQ2R
DQ13R
DQ12R
DQ12R
DQ12R
DQ7R
DQ6R
DQ6R
DQ6R
DQ3R
DQ3R
DQ3R
DQ3R
DQ1R
DQ1R
DQ1R
DQ1R
DQSn18R
DQ18R
DQS18R
DQ9R
DQ9R
DQ9R/CQn9R
DQ5R
DQ5R
DQ5R/CQn5R
DQ2R
DQ2R
DQ2R
DQSn12R
DQ12R
DQS12R
DQ6R
DQ6R
DQ6R/CQn6R
DQ3R
DQ3R
DQ3R/CQn3R
DQ1R
DQ1R
DQ1R
DQSn17R
DQ17R
DQS17R
DQSn9R/DQ9R
DQ9R
DQS9R/CQ9R
DQSn5R/DQ5R
DQ5R
DQS5R/CQ5R
DQ2R
DQ2R
DQ2R
DQSn11R
DQ11R
DQS11R
DQSn6R/DQ6R
DQ6R
DQS6R/CQ6R
DQSn3R/DQ3R
DQ3R
DQS3R/CQ3R
DQ1R
DQ1R
DQ1R
DQ17R
DQ17R
DQ9R
DQ9R
DQ5R
DQ5R
DQ2R
DQ2R
DQ11R
DQ11R
DQ6R
DQ6R
DQ3R
DQ3R
DQ1R
DQ1R
DQ17R
DQ16R
DQ16R
DQ16R
DQ9R
DQ8R
DQ8R
DQ8R
DQ5R
DQ4R
DQ4R
DQ4R
DQ2R
DQ2R
DQ2R
DQ2R
DQ11R
DQ10R
DQ10R
DQ10R
DQ6R
DQ5R
DQ5R
DQ5R
DQ3R
DQ2R
DQ2R
DQ2R
DQ1R
DQ1R
DQ1R
DQ1R
DQSn16R
DQ16R
DQS16R
DQ8R
DQ8R
DQ8R/CQn8R
DQ4R
DQ4R
DQ4R
DQ2R
DQ2R
DQ2R/CQn2R
DQSn10R
DQ10R
DQS10R
DQ5R
DQ5R
DQ5R/CQn5R
DQ2R
DQ2R
DQ2R
DQ1R
DQ1R
DQ1R/CQn1R
DQSn15R
DQ15R
DQS15R
DQSn8R/DQ8R
DQ8R
DQS8R/CQ8R
DQ4R
DQ4R
DQ4R
DQSn2R/DQ2R
DQ2R
DQS2R/CQ2R
DQSn9R
DQ9R
DQS9R
DQSn5R/DQ5R
DQ5R
DQS5R/CQ5R
DQ2R
DQ2R
DQ2R
DQSn1R/DQ1R
DQ1R
DQS1R/CQ1R
DQ15R
DQ15R
DQ8R
DQ8R
DQ4R
DQ4R
DQ2R
DQ2R
DQ9R
DQ9R
DQ5R
DQ5R
DQ2R
DQ2R
DQ1R
DQ1R
DQ15R
DQ14R
DQ14R
DQ14R
DQ8R
DQ7R
DQ7R
DQ7R
DQ4R
DQ4R
DQ4R
DQ4R
DQ2R
DQ2R
DQ2R
DQ2R
DQ9R
DQ8R
DQ8R
DQ8R
DQ5R
DQ4R
DQ4R
DQ4R
DQ2R
DQ2R
DQ2R
DQ2R
DQ1R
DQ1R
DQ1R
DQ1R
DQSn14R
DQ14R
DQS14R
DQ7R
DQ7R
DQ7R/CQn7R
DQ4R
DQ4R
DQ4R/CQn4R
DQ2R
DQ2R
DQ2R
DQSn8R
DQ8R
DQS8R
DQ4R
DQ4R
DQ4R/CQn4R
DQ2R
DQ2R
DQ2R/CQn2R
DQ1R
DQ1R
DQ1R
DQSn13R
DQ13R
DQS13R
DQSn7R/DQ7R
DQ7R
DQS7R/CQ7R
DQSn4R/DQ4R
DQ4R
DQS4R/CQ4R
DQ2R
DQ2R
DQ2R
DQSn7R
DQ7R
DQS7R
DQSn4R/DQ4R
DQ4R
DQS4R/CQ4R
DQSn2R/DQ2R
DQ2R
DQS2R/CQ2R
DQ1R
DQ1R
DQ1R
DQ13R
DQ13R
DQ7R
DQ7R
DQ4R
DQ4R
DQ2R
DQ2R
DQ7R
DQ7R
DQ4R
DQ4R
DQ2R
DQ2R
DQ1R
DQ1R
DQ13R
DQ7R
DQ4R
DQ2R
DQ7R
DQ4R
DQ2R
DQ1R
DQ12R
DQ12R
DQ12R
DQ6R
DQ6R
DQ6R
DQ3R
DQ3R
DQ3R
DQ1R
DQ1R
DQ1R
DQ6R
DQ6R
DQ6R
DQ3R
DQ3R
DQ3R
DQ1R
DQ1R
DQ1R
DQSn12R
DQ12R
DQS12R
DQ6R
DQ6R
DQ6R/CQn6R
DQ3R
DQ3R
DQ3R/CQn3R
DQ1R
DQ1R
DQ1R
DQSn6R
DQ6R
DQS6R
DQ3R
DQ3R
DQ3R/CQn3R
DQ1R
DQ1R
DQ1R/CQn1R
DQSn11R
DQ11R
DQS11R
DQSn6R/DQ6R
DQ6R
DQS6R/CQ6R
DQSn3R/DQ3R
DQ3R
DQS3R/CQ3R
DQ1R
DQ1R
DQ1R
DQSn5R
DQ5R
DQS5R
DQSn3R/DQ3R
DQ3R
DQS3R/CQ3R
DQSn1R/DQ1R
DQ1R
DQS1R/CQ1R
DQ11R
DQ11R
DQ6R
DQ6R
DQ3R
DQ3R
DQ1R
DQ1R
DQ5R
DQ5R
DQ3R
DQ3R
DQ1R
DQ1R
DQ11R
DQ10R
DQ10R
DQ10R
DQ6R
DQ5R
DQ5R
DQ5R
DQ3R
DQ3R
DQ3R
DQ3R
DQ1R
DQ1R
DQ1R
DQ1R
DQ5R
DQ4R
DQ4R
DQ4R
DQ3R
DQ2R
DQ2R
DQ2R
DQ1R
DQ1R
DQ1R
DQ1R
DQSn10R
DQ10R
DQS10R
DQ5R
DQ5R
DQ5R/CQn5R
DQ3R
DQ3R
DQ3R
DQ1R
DQ1R
DQ1R/CQn1R
DQSn4R
DQ4R
DQS4R
DQ2R
DQ2R
DQ2R/CQn2R
DQ1R
DQ1R
DQ1R
DQSn9R
DQ9R
DQS9R
DQSn5R/DQ5R
DQ5R
DQS5R/CQ5R
DQ3R
DQ3R
DQ3R
DQSn1R/DQ1R
DQ1R
DQS1R/CQ1R
DQSn3R
DQ3R
DQS3R
DQSn2R/DQ2R
DQ2R
DQS2R/CQ2R
DQ1R
DQ1R
DQ1R
Pin List
Page 4 of 15
®
Pin Information for the Arria II GX EP2AGX260 Device
Version 1.1
Bank
number
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7A
7A
7A
7A
7A
PT-EP2AGX260-1.1
Copyright © 2009 Altera Corp.
I/O Module
(Note 1)
RIO8
RIO8
RIO8
RIO8
RIO8
RIO9
RIO9
RIO9
RIO9
RIO9
RIO9
RIO9
RIO9
RIO9
RIO9
RIO9
RIO9
RIO9
RIO9
RIO9
RIO9
RIO10
RIO10
RIO10
RIO10
RIO10
RIO10
RIO10
RIO10
RIO10
RIO10
RIO10
RIO10
RIO10
RIO10
RIO10
RIO10
RIO11
RIO11
RIO11
RIO11
RIO11
RIO11
RIO11
RIO11
RIO11
RIO11
RIO11
RIO11
RIO11
RIO11
RIO11
RIO11
RIO12
RIO12
RIO12
RIO12
RIO12
RIO12
RIO12
RIO12
RIO12
RIO12
RIO12
RIO12
RIO12
RIO12
RIO12
RIO12
TIO12
TIO12
TIO12
TIO12
TIO12
TIO12
TIO12
TIO12
TIO12
TIO12
TIO12
TIO12
TIO12
TIO12
TIO12
TIO12
TIO11
TIO11
TIO11
TIO11
TIO11
TIO11
TIO11
TIO11
TIO11
TIO11
TIO11
TIO11
TIO11
TIO11
TIO11
TIO11
TIO10
VREF
Pin Function
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6BN0
VREFB6BN0
VREFB6BN0
VREFB6BN0
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VREFB6BN0
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VREFB6BN0
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VREFB6BN0
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VREFB6BN0
VREFB6BN0
VREFB6BN0
VREFB6BN0
VREFB6BN0
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VREFB6BN0
VREFB6BN0
VREFB6BN0
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VREFB6BN0
VREFB6BN0
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VREFB6BN0
VREFB6BN0
VREFB6BN0
VREFB6BN0
VREFB6BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
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VREFB7BN0
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VREFB7AN0
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VREFB7AN0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Optional
Function
Configuration
Function
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
CLKUSR
DEV_OE
DEV_CLRn
Dedicated Tx/Rx
Channel with
OCT Rd
Emulated LVDS Output Channel/
Dedicated LVDS Input Channel with
no OCT Rd (Note 2)
DIFFIO_RX_R31p
DIFFIO_TX_R32n
DIFFIO_RX_R32n
DIFFIO_TX_R32p
DIFFIO_RX_R32p
DIFFIO_TX_R33n
DIFFIO_RX_R33n
DIFFIO_TX_R33p
DIFFIO_RX_R33p
DIFFIO_TX_R34n
DIFFIO_RX_R34n
DIFFIO_TX_R34p
DIFFIO_RX_R34p
DIFFIO_TX_R35n
DIFFIO_RX_R35n
DIFFIO_TX_R35p
DIFFIO_RX_R35p
DIFFIO_TX_R36n
DIFFIO_RX_R36n
DIFFIO_TX_R36p
DIFFIO_RX_R36p
DIFFIO_TX_R37n
DIFFIO_RX_R37n
DIFFIO_TX_R37p
DIFFIO_RX_R37p
DIFFIO_TX_R38n
DIFFIO_RX_R38n
DIFFIO_TX_R38p
DIFFIO_RX_R38p
DIFFIO_TX_R39n
DIFFIO_RX_R39n
DIFFIO_TX_R39p
DIFFIO_RX_R39p
DIFFIO_TX_R40n
DIFFIO_RX_R40n
DIFFIO_TX_R40p
DIFFIO_RX_R40p
DIFFIO_TX_R41n
DIFFIO_RX_R41n
DIFFIO_TX_R41p
DIFFIO_RX_R41p
DIFFIO_TX_R42n
DIFFIO_RX_R42n
DIFFIO_TX_R42p
DIFFIO_RX_R42p
DIFFIO_TX_R43n
DIFFIO_RX_R43n
DIFFIO_TX_R43p
DIFFIO_RX_R43p
DIFFIO_TX_R44n
DIFFIO_RX_R44n
DIFFIO_TX_R44p
DIFFIO_RX_R44p
DIFFIO_TX_R45n
DIFFIO_RX_R45n
DIFFIO_TX_R45p
DIFFIO_RX_R45p
DIFFIO_TX_R46n
DIFFIO_RX_R46n
DIFFIO_TX_R46p
DIFFIO_RX_R46p
DIFFIO_TX_R47n
DIFFIO_RX_R47n
DIFFIO_TX_R47p
DIFFIO_RX_R47p
DIFFIO_TX_R48n
DIFFIO_RX_R48n
DIFFIO_TX_R48p
DIFFIO_RX_R48p
DIFFIO_RX_T1p
DIFFIO_TX_T1p
DIFFIO_RX_T1n
DIFFIO_TX_T1n
DIFFIO_RX_T2p
DIFFIO_TX_T2p
DIFFIO_RX_T2n
DIFFIO_TX_T2n
DIFFIO_RX_T3p
DIFFIO_TX_T3p
DIFFIO_RX_T3n
DIFFIO_TX_T3n
DIFFIO_RX_T4p
DIFFIO_TX_T4p
DIFFIO_RX_T4n
DIFFIO_TX_T4n
DIFFIO_RX_T5p
DIFFIO_TX_T5p
DIFFIO_RX_T5n
DIFFIO_TX_T5n
DIFFIO_RX_T6p
DIFFIO_TX_T6p
DIFFIO_RX_T6n
DIFFIO_TX_T6n
DIFFIO_RX_T7p
DIFFIO_TX_T7p
DIFFIO_RX_T7n
DIFFIO_TX_T7n
DIFFIO_RX_T8p
DIFFIO_TX_T8p
DIFFIO_RX_T8n
DIFFIO_TX_T8n
DIFFOUT_R31p
DIFFIN_R32n*
DIFFOUT_R32n
DIFFIN_R32p*
DIFFOUT_R32p
DIFFIN_R33n*
DIFFOUT_R33n
DIFFIN_R33p*
DIFFOUT_R33p
DIFFIN_R34n*
DIFFOUT_R34n
DIFFIN_R34p*
DIFFOUT_R34p
DIFFIN_R35n*
DIFFOUT_R35n
DIFFIN_R35p*
DIFFOUT_R35p
DIFFIN_R36n*
DIFFOUT_R36n
DIFFIN_R36p*
DIFFOUT_R36p
DIFFIN_R37n*
DIFFOUT_R37n
DIFFIN_R37p*
DIFFOUT_R37p
DIFFIN_R38n*
DIFFOUT_R38n
DIFFIN_R38p*
DIFFOUT_R38p
DIFFIN_R39n*
DIFFOUT_R39n
DIFFIN_R39p*
DIFFOUT_R39p
DIFFIN_R40n*
DIFFOUT_R40n
DIFFIN_R40p*
DIFFOUT_R40p
DIFFIN_R41n*
DIFFOUT_R41n
DIFFIN_R41p*
DIFFOUT_R41p
DIFFIN_R42n*
DIFFOUT_R42n
DIFFIN_R42p*
DIFFOUT_R42p
DIFFIN_R43n*
DIFFOUT_R43n
DIFFIN_R43p*
DIFFOUT_R43p
DIFFIN_R44n*
DIFFOUT_R44n
DIFFIN_R44p*
DIFFOUT_R44p
DIFFIN_R45n*
DIFFOUT_R45n
DIFFIN_R45p*
DIFFOUT_R45p
DIFFIN_R46n*
DIFFOUT_R46n
DIFFIN_R46p*
DIFFOUT_R46p
DIFFIN_R47n*
DIFFOUT_R47n
DIFFIN_R47p*
DIFFOUT_R47p
DIFFIN_R48n*
DIFFOUT_R48n
DIFFIN_R48p*
DIFFOUT_R48p
DIFFOUT_T1p
DIFFIN_T1p*
DIFFOUT_T1n
DIFFIN_T1n*
DIFFOUT_T2p
DIFFIN_T2p*
DIFFOUT_T2n
DIFFIN_T2n*
DIFFOUT_T3p
DIFFIN_T3p*
DIFFOUT_T3n
DIFFIN_T3n*
DIFFOUT_T4p
DIFFIN_T4p*
DIFFOUT_T4n
DIFFIN_T4n*
DIFFOUT_T5p
DIFFIN_T5p*
DIFFOUT_T5n
DIFFIN_T5n*
DIFFOUT_T6p
DIFFIN_T6p*
DIFFOUT_T6n
DIFFIN_T6n*
DIFFOUT_T7p
DIFFIN_T7p*
DIFFOUT_T7n
DIFFIN_T7n*
DIFFOUT_T8p
DIFFIN_T8p*
DIFFOUT_T8n
DIFFIN_T8n*
RUP1
PLL2_CLKOUT1p
RDN1
PLL2_CLKOUT1n
DIFFIO_RX_T9p
DIFFOUT_T9p
F1152
F780
P4
R9
J1
T10
J2
H1
F1
G1
E1
P7
D1
R8
D2
N3
N4
M3
N5
P9
C1
P10
C2
K2
M4
K3
L4
P6
G2
N6
F2
J4
J3
J5
H3
N9
K4
N10
K5
M5
G3
M6
H4
N7
F3
N8
F4
D3
E3
D4
E4
M9
K6
M10
K7
J6
G4
J7
G5
M7
C5
M8
D5
F5
C6
G6
D6
L7
H7
K8
J8
F6
L11
E6
K11
G7
H9
F7
G9
E7
L10
D7
L9
H10
F9
G10
F8
C8
K12
C7
J11
F10
J12
E9
H12
E10
M13
D9
L13
D10
J13
C10
H13
G12
K14
G11
J14
G13
H4
K8
K4
K9
K5
B1
C2
A2
C3
H6
G3
H7
G4
E3
F3
D3
F4
G5
E4
G6
F5
F7
K10
G7
J9
F9
DQS for X4 for F1152
DQS for X8/X9 for
F1152 (Note 3)
DQS for X16/X18 for
F1152 (Note3)
DQS for X32/X36 for
F1152 (Note 3)
DQS for X4 for F780
DQS for X8/X9 for F780 DQS for X16/X18 for
(Note 3)
F780 (Note 3)
DQ9R
DQ9R
DQ5R
DQ5R
DQ3R
DQ3R
DQ1R
DQ1R
DQ3R
DQ3R
DQ2R
DQ2R
DQ1R
DQ1R
DQ9R
DQ8R
DQ8R
DQ8R
DQ5R
DQ4R
DQ4R
DQ4R
DQ3R
DQ2R
DQ2R
DQ2R
DQ1R
DQ1R
DQ1R
DQ1R
DQ3R
DQ2R
DQ1R
DQSn8R
DQ8R
DQS8R
DQ4R
DQ4R
DQ4R/CQn4R
DQ2R
DQ2R
DQ2R/CQn2R
DQ1R
DQ1R
DQ1R
DQSn7R
DQ7R
DQS7R
DQSn4R/DQ4R
DQ4R
DQS4R/CQ4R
DQSn2R/DQ2R
DQ2R
DQS2R/CQ2R
DQ1R
DQ1R
DQ1R
DQ7R
DQ7R
DQ4R
DQ4R
DQ2R
DQ2R
DQ1R
DQ1R
DQ7R
DQ6R
DQ6R
DQ6R
DQ4R
DQ3R
DQ3R
DQ3R
DQ2R
DQ2R
DQ2R
DQ2R
DQ1R
DQ1R
DQ1R
DQ1R
DQ2R
DQ2R
DQ2R
DQ1R
DQ1R
DQ1R
DQSn6R
DQ6R
DQS6R
DQ3R
DQ3R
DQ3R/CQn3R
DQ2R
DQ2R
DQ2R
DQ1R
DQ1R
DQ1R
DQSn2R
DQ2R
DQS2R
DQ1R
DQ1R
DQ1R/CQn1R
DQSn5R
DQ5R
DQS5R
DQSn3R/DQ3R
DQ3R
DQS3R/CQ3R
DQ2R
DQ2R
DQ2R
DQ1R
DQ1R
DQ1R
DQSn1R
DQ1R
DQS1R
DQSn1R/DQ1R
DQ1R
DQS1R/CQ1R
DQ5R
DQ5R
DQ3R
DQ3R
DQ2R
DQ2R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ5R
DQ4R
DQ4R
DQ4R
DQ3R
DQ2R
DQ2R
DQ2R
DQ2R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQSn4R
DQ4R
DQS4R
DQ2R
DQ2R
DQ2R/CQn2R
DQ1R
DQ1R
DQ1R/CQn1R
DQSn3R
DQ3R
DQS3R
DQSn2R/DQ2R
DQ2R
DQS2R/CQ2R
DQSn1R/DQ1R
DQ1R
DQS1R/CQ1R
DQ3R
DQ3R
DQ2R
DQ2R
DQ1R
DQ1R
DQ3R
DQ2R
DQ2R
DQ2R
DQ2R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQSn2R
DQ2R
DQS2R
DQ1R
DQ1R
DQ1R/CQn1R
DQ1R
DQ1R
DQ1R
DQSn1R
DQ1R
DQS1R
DQSn1R/DQ1R
DQ1R
DQS1R/CQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ24T
DQ1R
DQ12T
DQ1R
DQ6T
DQ24T
DQ24T
DQ12T
DQ12T
DQ6T
DQ6T
DQS24T
DQ24T
DQSn24T
DQS12T/CQ12T
DQ12T
DQSn12T/DQ12T
DQ6T
DQ6T
DQ6T
DQS23T
DQ23T
DQSn23T
DQ12T/CQn12T
DQ12T
DQ12T
DQ6T
DQ6T
DQ6T
DQ23T
DQ23T
DQ23T
DQ22T
DQ12T
DQ12T
DQ12T
DQ11T
DQ6T
DQ6T
DQ6T
DQ6T
DQ22T
DQ22T
DQ11T
DQ11T
DQ6T
DQ6T
DQS22T
DQ22T
DQSn22T
DQS11T/CQ11T
DQ11T
DQSn11T/DQ11T
DQS6T/CQ6T
DQ6T
DQSn6T/DQ6T
DQS21T
DQ21T
DQSn21T
DQ11T/CQn11T
DQ11T
DQ11T
DQ6T/CQn6T
DQ6T
DQ6T
DQ21T
DQ21T
DQ21T
DQ11T
DQ11T
DQ11T
DQ6T
DQ6T
DQ6T
DQ20T
DQ10T
DQ5T
DQ2T
DQ14T
DQ7T
Pin List
DQ3T
DQS for X32/X36 for
F780 (Note 3)
DQ1T
Page 5 of 15
®
Pin Information for the Arria II GX EP2AGX260 Device
Version 1.1
Bank
number
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
8A
7A
8A
7A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
PT-EP2AGX260-1.1
Copyright © 2009 Altera Corp.
I/O Module
(Note 1)
TIO10
TIO10
TIO10
TIO10
TIO10
TIO10
TIO10
TIO10
TIO10
TIO10
TIO10
TIO10
TIO10
TIO10
TIO10
TIO9
TIO9
TIO9
TIO9
TIO9
TIO9
TIO9
TIO9
TIO9
TIO9
TIO9
TIO9
TIO9
TIO9
TIO9
TIO9
TIO8
TIO8
TIO8
TIO8
TIO8
TIO8
TIO8
TIO8
TIO8
TIO8
TIO8
TIO8
TIO8
TIO8
TIO8
TIO8
TIO7
TIO7
TIO7
TIO7
TIO7
TIO7
TIO7
TIO7
TIO7
TIO7
TIO7
TIO7
TIO7
TIO7
TIO7
TIO7
TIO6
TIO6
TIO6
TIO6
TIO6
TIO6
TIO6
TIO6
TIO6
TIO6
TIO6
TIO6
TIO6
TIO6
TIO6
TIO6
TIO5
TIO5
TIO5
TIO5
TIO5
TIO5
TIO5
TIO5
TIO5
TIO5
TIO5
TIO5
TIO5
TIO5
TIO5
TIO5
TIO4
TIO4
TIO4
TIO4
TIO4
TIO4
TIO4
VREF
Pin Function
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB8AN0
VREFB7AN0
VREFB8AN0
VREFB7AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
CLK12
CLK13
CLK14
CLK15
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Optional
Function
Configuration
Function
Dedicated Tx/Rx
Channel with
OCT Rd
Emulated LVDS Output Channel/
Dedicated LVDS Input Channel with
no OCT Rd (Note 2)
DIFFIO_TX_T9p
DIFFIO_RX_T9n
DIFFIO_TX_T9n
DIFFIO_RX_T10p
DIFFIO_TX_T10p
DIFFIO_RX_T10n
DIFFIO_TX_T10n
DIFFIO_RX_T11p
DIFFIO_TX_T11p
DIFFIO_RX_T11n
DIFFIO_TX_T11n
DIFFIO_RX_T12p
DIFFIO_TX_T12p
DIFFIO_RX_T12n
DIFFIO_TX_T12n
DIFFIO_RX_T13p
DIFFIO_TX_T13p
DIFFIO_RX_T13n
DIFFIO_TX_T13n
DIFFIO_RX_T14p
DIFFIO_TX_T14p
DIFFIO_RX_T14n
DIFFIO_TX_T14n
DIFFIO_RX_T15p
DIFFIO_TX_T15p
DIFFIO_RX_T15n
DIFFIO_TX_T15n
DIFFIO_RX_T16p
DIFFIO_TX_T16p
DIFFIO_RX_T16n
DIFFIO_TX_T16n
DIFFIO_RX_T17p
DIFFIO_TX_T17p
DIFFIO_RX_T17n
DIFFIO_TX_T17n
DIFFIO_RX_T18p
DIFFIO_TX_T18p
DIFFIO_RX_T18n
DIFFIO_TX_T18n
DIFFIO_RX_T19p
DIFFIO_TX_T19p
DIFFIO_RX_T19n
DIFFIO_TX_T19n
DIFFIO_RX_T20p
DIFFIO_TX_T20p
DIFFIO_RX_T20n
DIFFIO_TX_T20n
DIFFIO_RX_T21p
DIFFIO_TX_T21p
DIFFIO_RX_T21n
DIFFIO_TX_T21n
DIFFIO_RX_T22p
DIFFIO_TX_T22p
DIFFIO_RX_T22n
DIFFIO_TX_T22n
DIFFIO_RX_T23p
DIFFIO_TX_T23p
DIFFIO_RX_T23n
DIFFIO_TX_T23n
DIFFIO_RX_T24p
DIFFIO_TX_T24p
DIFFIO_RX_T24n
DIFFIO_TX_T24n
DIFFIN_T9p*
DIFFOUT_T9n
DIFFIN_T9n*
DIFFOUT_T10p
DIFFIN_T10p*
DIFFOUT_T10n
DIFFIN_T10n*
DIFFOUT_T11p
DIFFIN_T11p*
DIFFOUT_T11n
DIFFIN_T11n*
DIFFOUT_T12p
DIFFIN_T12p*
DIFFOUT_T12n
DIFFIN_T12n*
DIFFOUT_T13p
DIFFIN_T13p*
DIFFOUT_T13n
DIFFIN_T13n*
DIFFOUT_T14p
DIFFIN_T14p*
DIFFOUT_T14n
DIFFIN_T14n*
DIFFOUT_T15p
DIFFIN_T15p*
DIFFOUT_T15n
DIFFIN_T15n*
DIFFOUT_T16p
DIFFIN_T16p*
DIFFOUT_T16n
DIFFIN_T16n*
DIFFOUT_T17p
DIFFIN_T17p*
DIFFOUT_T17n
DIFFIN_T17n*
DIFFOUT_T18p
DIFFIN_T18p*
DIFFOUT_T18n
DIFFIN_T18n*
DIFFOUT_T19p
DIFFIN_T19p*
DIFFOUT_T19n
DIFFIN_T19n*
DIFFOUT_T20p
DIFFIN_T20p*
DIFFOUT_T20n
DIFFIN_T20n*
DIFFOUT_T21p
DIFFIN_T21p*
DIFFOUT_T21n
DIFFIN_T21n*
DIFFOUT_T22p
DIFFIN_T22p*
DIFFOUT_T22n
DIFFIN_T22n*
DIFFOUT_T23p
DIFFIN_T23p*
DIFFOUT_T23n
DIFFIN_T23n*
DIFFOUT_T24p
DIFFIN_T24p*
DIFFOUT_T24n
DIFFIN_T24n*
DIFFIO_RX_T25p
DIFFIO_TX_T25p
DIFFIO_RX_T25n
DIFFIO_TX_T25n
DIFFIO_RX_T26p
DIFFIO_TX_T26p
DIFFIO_RX_T26n
DIFFIO_TX_T26n
DIFFIO_RX_T27p
DIFFIO_TX_T27p
DIFFIO_RX_T27n
DIFFIO_TX_T27n
DIFFIO_RX_T28p
DIFFIO_TX_T28p
DIFFIO_RX_T28n
DIFFIO_TX_T28n
DIFFIO_RX_T29p
DIFFIO_TX_T29p
DIFFIO_RX_T29n
DIFFIO_TX_T29n
DIFFIO_RX_T30p
DIFFIO_TX_T30p
DIFFIO_RX_T30n
DIFFIO_TX_T30n
DIFFIO_RX_T31p
DIFFIO_TX_T31p
DIFFIO_RX_T31n
DIFFIO_TX_T31n
DIFFIO_RX_T32p
DIFFIO_TX_T32p
DIFFIO_RX_T32n
DIFFIO_TX_T32n
DIFFIO_RX_T33p
DIFFIO_TX_T33p
DIFFIO_RX_T33n
DIFFIO_TX_T33n
DIFFIO_RX_T34p
DIFFIO_TX_T34p
DIFFIO_RX_T34n
DIFFOUT_T25p
DIFFIN_T25p*
DIFFOUT_T25n
DIFFIN_T25n*
DIFFOUT_T26p
DIFFIN_T26p*
DIFFOUT_T26n
DIFFIN_T26n*
DIFFOUT_T27p
DIFFIN_T27p*
DIFFOUT_T27n
DIFFIN_T27n*
DIFFOUT_T28p
DIFFIN_T28p*
DIFFOUT_T28n
DIFFIN_T28n*
DIFFOUT_T29p
DIFFIN_T29p*
DIFFOUT_T29n
DIFFIN_T29n*
DIFFOUT_T30p
DIFFIN_T30p*
DIFFOUT_T30n
DIFFIN_T30n*
DIFFOUT_T31p
DIFFIN_T31p*
DIFFOUT_T31n
DIFFIN_T31n*
DIFFOUT_T32p
DIFFIN_T32p*
DIFFOUT_T32n
DIFFIN_T32n*
DIFFOUT_T33p
DIFFIN_T33p*
DIFFOUT_T33n
DIFFIN_T33n*
DIFFOUT_T34p
DIFFIN_T34p*
DIFFOUT_T34n
DIFFCLK_4p
DIFFCLK_5p
DIFFCLK_4n
DIFFCLK_5n
F1152
F780
H15
F13
G15
B1
F12
A2
E12
C3
K15
B4
J15
E13
D12
D13
D11
B3
K16
A3
J16
A5
G14
A4
F15
C9
L16
B9
K17
B6
B7
A6
A7
D14
J17
C15
H16
A9
E15
A8
D15
C13
H18
C12
G18
F16
D16
E16
C16
B13
G17
B12
G16
A12
B10
A11
A10
A14
M17
A13
M16
B15
B16
A15
A16
F18
K18
F17
J18
D18
N19
D17
M18
C18
A18
B18
A17
B19
G19
A19
F19
D19
A21
C19
A20
C21
K20
B21
J20
E19
A23
E18
A22
C22
J19
B22
H19
B24
B25
A24
A25
A27
G21
A26
G20
D21
C28
D20
H10
F8
G10
F10
E6
E10
D5
D4
K11
C4
J10
B3
A5
A3
A4
E7
G11
D7
F11
D6
E9
C5
D9
C7
J12
C6
J11
D8
D10
C8
C10
E12
G12
D12
F12
C9
D11
B9
C11
G13
K13
F13
K12
E13
C13
D13
C12
B6
K14
A6
J14
A10
A8
A9
A7
B12
G14
A11
F14
A13
A15
A12
A14
D15
D14
C15
C14
C16
F16
B15
F15
A18
B16
A17
A16
E15
H15
D16
G15
A20
C19
A19
B19
D17
L15
C17
K15
D18
D21
C18
C21
D20
G17
D19
F17
L19
J21
K20
J20
F22
K16
E22
J16
G24
F24
F23
DQS for X4 for F1152
DQS for X8/X9 for
F1152 (Note 3)
DQS for X16/X18 for
F1152 (Note3)
DQS for X32/X36 for
F1152 (Note 3)
DQS for X4 for F780
DQS for X8/X9 for F780 DQS for X16/X18 for
(Note 3)
F780 (Note 3)
DQS for X32/X36 for
F780 (Note 3)
DQ20T
DQ20T
DQ10T
DQ10T
DQ5T
DQ5T
DQ2T
DQ2T
DQ14T
DQ14T
DQ7T
DQ7T
DQ3T
DQ3T
DQ1T
DQ1T
DQS20T
DQ20T
DQSn20T
DQS10T/CQ10T
DQ10T
DQSn10T/DQ10T
DQ5T
DQ5T
DQ5T
DQ2T
DQ2T
DQ2T
DQS14T
DQ14T
DQSn14T
DQS7T/CQ7T
DQ7T
DQSn7T/DQ7T
DQ3T
DQ3T
DQ3T
DQ1T
DQ1T
DQ1T
DQS19T
DQ19T
DQSn19T
DQ10T/CQn10T
DQ10T
DQ10T
DQ5T
DQ5T
DQ5T
DQ2T
DQ2T
DQ2T
DQS13T
DQ13T
DQSn13T
DQ7T/CQn7T
DQ7T
DQ7T
DQ3T
DQ3T
DQ3T
DQ1T
DQ1T
DQ1T
DQ19T
DQ19T
DQ19T
DQ18T
DQ10T
DQ10T
DQ10T
DQ9T
DQ5T
DQ5T
DQ5T
DQ5T
DQ2T
DQ2T
DQ2T
DQ2T
DQ13T
DQ13T
DQ13T
DQ12T
DQ7T
DQ7T
DQ7T
DQ6T
DQ3T
DQ3T
DQ3T
DQ3T
DQ1T
DQ1T
DQ1T
DQ1T
DQ18T
DQ18T
DQ9T
DQ9T
DQ5T
DQ5T
DQ2T
DQ2T
DQ12T
DQ12T
DQ6T
DQ6T
DQ3T
DQ3T
DQ1T
DQ1T
DQS18T
DQ18T
DQSn18T
DQS9T/CQ9T
DQ9T
DQSn9T/DQ9T
DQS5T/CQ5T
DQ5T
DQSn5T/DQ5T
DQ2T
DQ2T
DQ2T
DQS12T
DQ12T
DQSn12T
DQS6T/CQ6T
DQ6T
DQSn6T/DQ6T
DQS3T/CQ3T
DQ3T
DQSn3T/DQ3T
DQ1T
DQ1T
DQ1T
DQS17T
DQ17T
DQSn17T
DQ9T/CQn9T
DQ9T
DQ9T
DQ5T/CQn5T
DQ5T
DQ5T
DQ2T
DQ2T
DQ2T
DQS11T
DQ11T
DQSn11T
DQ6T/CQn6T
DQ6T
DQ6T
DQ3T/CQn3T
DQ3T
DQ3T
DQ1T
DQ1T
DQ1T
DQ17T
DQ17T
DQ17T
DQ16T
DQ9T
DQ9T
DQ9T
DQ8T
DQ5T
DQ5T
DQ5T
DQ4T
DQ2T
DQ2T
DQ2T
DQ2T
DQ11T
DQ11T
DQ11T
DQ10T
DQ6T
DQ6T
DQ6T
DQ5T
DQ3T
DQ3T
DQ3T
DQ2T
DQ1T
DQ1T
DQ1T
DQ1T
DQ16T
DQ16T
DQ8T
DQ8T
DQ4T
DQ4T
DQ2T
DQ2T
DQ10T
DQ10T
DQ5T
DQ5T
DQ2T
DQ2T
DQ1T
DQ1T
DQS16T
DQ16T
DQSn16T
DQS8T/CQ8T
DQ8T
DQSn8T/DQ8T
DQ4T
DQ4T
DQ4T
DQS2T/CQ2T
DQ2T
DQSn2T/DQ2T
DQS10T
DQ10T
DQSn10T
DQS5T/CQ5T
DQ5T
DQSn5T/DQ5T
DQ2T
DQ2T
DQ2T
DQS1T/CQ1T
DQ1T
DQSn1T/DQ1T
DQS15T
DQ15T
DQSn15T
DQ8T/CQn8T
DQ8T
DQ8T
DQ4T
DQ4T
DQ4T
DQ2T/CQn2T
DQ2T
DQ2T
DQS9T
DQ9T
DQSn9T
DQ5T/CQn5T
DQ5T
DQ5T
DQ2T
DQ2T
DQ2T
DQ1T/CQn1T
DQ1T
DQ1T
DQ15T
DQ15T
DQ15T
DQ14T
DQ8T
DQ8T
DQ8T
DQ7T
DQ4T
DQ4T
DQ4T
DQ4T
DQ2T
DQ2T
DQ2T
DQ2T
DQ9T
DQ9T
DQ9T
DQ8T
DQ5T
DQ5T
DQ5T
DQ4T
DQ2T
DQ2T
DQ2T
DQ2T
DQ1T
DQ1T
DQ1T
DQ1T
DQ14T
DQ14T
DQ7T
DQ7T
DQ4T
DQ4T
DQ2T
DQ2T
DQ8T
DQ8T
DQ4T
DQ4T
DQ2T
DQ2T
DQ1T
DQ1T
DQS14T
DQ14T
DQSn14T
DQS7T/CQ7T
DQ7T
DQSn7T/DQ7T
DQS4T/CQ4T
DQ4T
DQSn4T/DQ4T
DQ2T
DQ2T
DQ2T
DQS8T
DQ8T
DQSn8T
DQS4T/CQ4T
DQ4T
DQSn4T/DQ4T
DQS2T/CQ2T
DQ2T
DQSn2T/DQ2T
DQ1T
DQ1T
DQ1T
DQS13T
DQ13T
DQSn13T
DQ7T/CQn7T
DQ7T
DQ7T
DQ4T/CQn4T
DQ4T
DQ4T
DQ2T
DQ2T
DQ2T
DQS7T
DQ7T
DQSn7T
DQ4T/CQn4T
DQ4T
DQ4T
DQ2T/CQn2T
DQ2T
DQ2T
DQ1T
DQ1T
DQ1T
DQ13T
DQ13T
DQ13T
DQ7T
DQ7T
DQ7T
DQ4T
DQ4T
DQ4T
DQ2T
DQ2T
DQ2T
DQ7T
DQ7T
DQ7T
DQ4T
DQ4T
DQ4T
DQ2T
DQ2T
DQ2T
DQ1T
DQ1T
DQ1T
DQ12T
DQ6T
DQ3T
DQ1T
DQ6T
DQ3T
DQ1T
DQ12T
DQ12T
DQ6T
DQ6T
DQ3T
DQ3T
DQ1T
DQ1T
DQ6T
DQ6T
DQ3T
DQ3T
DQ1T
DQ1T
DQS12T
DQ12T
DQSn12T
DQS6T/CQ6T
DQ6T
DQSn6T/DQ6T
DQS3T/CQ3T
DQ3T
DQSn3T/DQ3T
DQ1T
DQ1T
DQ1T
DQS6T
DQ6T
DQSn6T
DQS3T/CQ3T
DQ3T
DQSn3T/DQ3T
DQS1T/CQ1T
DQ1T
DQSn1T/DQ1T
DQS11T
DQ11T
DQSn11T
DQ6T/CQn6T
DQ6T
DQ6T
DQ3T/CQn3T
DQ3T
DQ3T
DQ1T
DQ1T
DQ1T
DQS5T
DQ5T
DQSn5T
DQ3T/CQn3T
DQ3T
DQ3T
DQ1T/CQn1T
DQ1T
DQ1T
DQ11T
DQ11T
DQ11T
DQ10T
DQ6T
DQ6T
DQ6T
DQ5T
DQ3T
DQ3T
DQ3T
DQ3T
DQ1T
DQ1T
DQ1T
DQ1T
DQ5T
DQ5T
DQ5T
DQ4T
DQ3T
DQ3T
DQ3T
DQ2T
DQ1T
DQ1T
DQ1T
DQ1T
DQ10T
DQ10T
DQ5T
DQ5T
DQ3T
DQ3T
DQ1T
DQ1T
DQ4T
DQ4T
DQ2T
DQ2T
DQ1T
DQ1T
DQS10T
DQ10T
DQSn10T
DQS5T/CQ5T
DQ5T
DQSn5T/DQ5T
DQ3T
DQ3T
DQ3T
DQS1T/CQ1T
DQ1T
DQSn1T/DQ1T
DQS4T
DQ4T
DQSn4T
DQS2T/CQ2T
DQ2T
DQSn2T/DQ2T
DQ1T
DQ1T
DQ1T
DQS9T
DQ9T
DQSn9T
DQ5T/CQn5T
DQ5T
DQ5T
DQ3T
DQ3T
DQ3T
DQ1T/CQn1T
DQ1T
DQ1T
DQS3T
DQ3T
DQSn3T
DQ2T/CQn2T
DQ2T
DQ2T
DQ1T
DQ1T
DQ1T
DQ9T
DQ9T
DQ9T
DQ8T
DQ5T
DQ5T
DQ5T
DQ4T
DQ3T
DQ3T
DQ3T
DQ2T
DQ1T
DQ1T
DQ1T
DQ1T
DQ3T
DQ3T
DQ3T
DQ2T
DQ2T
DQ2T
DQ2T
DQ1T
DQ1T
DQ1T
DQ1T
DQ8T
DQ8T
DQ4T
DQ4T
DQ2T
DQ2T
DQ1T
DQ1T
DQ2T
DQ2T
DQ1T
DQ1T
DQS8T
DQ8T
DQS4T/CQ4T
DQ4T
DQS2T/CQ2T
DQ2T
DQ1T
DQ1T
DQS2T
DQ2T
DQS1T/CQ1T
DQ1T
Pin List
Page 6 of 15
®
Pin Information for the Arria II GX EP2AGX260 Device
Version 1.1
Bank
number
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8C
8C
8C
8C
8C
8C
8C
8C
PT-EP2AGX260-1.1
Copyright © 2009 Altera Corp.
I/O Module
(Note 1)
TIO4
TIO4
TIO4
TIO4
TIO4
TIO4
TIO4
TIO4
TIO4
TIO3
TIO3
TIO3
TIO3
TIO3
TIO3
TIO3
TIO3
TIO3
TIO3
TIO3
TIO3
TIO3
TIO3
TIO3
TIO3
TIO2
TIO2
TIO2
TIO2
TIO2
TIO2
TIO2
TIO2
TIO2
TIO2
TIO2
TIO2
TIO2
TIO2
TIO2
TIO2
TIO1
TIO1
TIO1
TIO1
TIO1
TIO1
TIO1
TIO1
TIO1
TIO1
TIO1
TIO1
TIO1
TIO1
TIO1
TIO1
VREF
Pin Function
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
TDO
ASDO
nCSO
DATA0
TDI
TMS
TCK
DCLK
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Optional
Function
Configuration
Function
CRC_ERROR
Dedicated Tx/Rx
Channel with
OCT Rd
Emulated LVDS Output Channel/
Dedicated LVDS Input Channel with
no OCT Rd (Note 2)
DIFFIO_TX_T34n
DIFFIO_RX_T35p
DIFFIO_TX_T35p
DIFFIO_RX_T35n
DIFFIO_TX_T35n
DIFFIO_RX_T36p
DIFFIO_TX_T36p
DIFFIO_RX_T36n
DIFFIO_TX_T36n
DIFFIO_RX_T37p
DIFFIO_TX_T37p
DIFFIO_RX_T37n
DIFFIO_TX_T37n
DIFFIO_RX_T38p
DIFFIO_TX_T38p
DIFFIO_RX_T38n
DIFFIO_TX_T38n
DIFFIO_RX_T39p
DIFFIO_TX_T39p
DIFFIO_RX_T39n
DIFFIO_TX_T39n
DIFFIO_RX_T40p
DIFFIO_TX_T40p
DIFFIO_RX_T40n
DIFFIO_TX_T40n
DIFFIN_T34n*
DIFFOUT_T35p
DIFFIN_T35p*
DIFFOUT_T35n
DIFFIN_T35n*
DIFFOUT_T36p
DIFFIN_T36p*
DIFFOUT_T36n
DIFFIN_T36n*
DIFFOUT_T37p
DIFFIN_T37p*
DIFFOUT_T37n
DIFFIN_T37n*
DIFFOUT_T38p
DIFFIN_T38p*
DIFFOUT_T38n
DIFFIN_T38n*
DIFFOUT_T39p
DIFFIN_T39p*
DIFFOUT_T39n
DIFFIN_T39n*
DIFFOUT_T40p
DIFFIN_T40p*
DIFFOUT_T40n
DIFFIN_T40n*
RUP2
PLL1_CLKOUT1p
RDN2
PLL1_CLKOUT1n
PLL1_CLKOUT2p
PLL1_CLKOUT3p
PLL1_CLKOUT2n
PLL1_CLKOUT3n
DIFFIO_RX_T41p
DIFFIO_TX_T41p
DIFFIO_RX_T41n
DIFFIO_TX_T41n
DIFFIO_RX_T42p
DIFFIO_TX_T42p
DIFFIO_RX_T42n
DIFFIO_TX_T42n
DIFFIO_RX_T43p
DIFFIO_TX_T43p
DIFFIO_RX_T43n
DIFFIO_TX_T43n
DIFFIO_RX_T44p
DIFFIO_TX_T44p
DIFFIO_RX_T44n
DIFFIO_TX_T44n
DIFFIO_RX_T45p
DIFFIO_TX_T45p
DIFFIO_RX_T45n
DIFFIO_TX_T45n
DIFFIO_RX_T46p
DIFFIO_TX_T46p
DIFFIO_RX_T46n
DIFFIO_TX_T46n
DIFFIO_RX_T47p
DIFFIO_TX_T47p
DIFFIO_RX_T47n
DIFFIO_TX_T47n
DIFFIO_RX_T48p
DIFFIO_TX_T48p
DIFFIO_RX_T48n
DIFFIO_TX_T48n
TDO
ASDO
nCSO
DATA0
TDI
TMS
TCK
DCLK
DIFFOUT_T41p
DIFFIN_T41p*
DIFFOUT_T41n
DIFFIN_T41n*
DIFFOUT_T42p
DIFFIN_T42p*
DIFFOUT_T42n
DIFFIN_T42n*
DIFFOUT_T43p
DIFFIN_T43p*
DIFFOUT_T43n
DIFFIN_T43n*
DIFFOUT_T44p
DIFFIN_T44p*
DIFFOUT_T44n
DIFFIN_T44n*
DIFFOUT_T45p
DIFFIN_T45p*
DIFFOUT_T45n
DIFFIN_T45n*
DIFFOUT_T46p
DIFFIN_T46p*
DIFFOUT_T46n
DIFFIN_T46n*
DIFFOUT_T47p
DIFFIN_T47p*
DIFFOUT_T47n
DIFFIN_T47n*
DIFFOUT_T48p
DIFFIN_T48p*
DIFFOUT_T48n
DIFFIN_T48n*
F1152
F780
DQS for X4 for F1152
DQS for X8/X9 for
F1152 (Note 3)
DQS for X16/X18 for
F1152 (Note3)
DQS for X32/X36 for
F1152 (Note 3)
DQS for X4 for F780
DQS for X8/X9 for F780 DQS for X16/X18 for
(Note 3)
F780 (Note 3)
B27
D23
G23
C24
F23
F24
D24
E24
C25
F21
N20
E21
M20
D27
D25
C27
C26
E22
H21
D22
G22
D29
C30
D28
C29
E25
M21
D26
L21
F26
K21
F25
J21
G25
K23
G24
J22
J27
H27
J28
G26
G28
L22
G27
K22
L28
F27
K28
E27
J29
K24
H28
J24
G30
J30
F30
H30
F28
J25
E28
H24
G29
E30
F29
D30
M27
K27
M26
N26
M25
N25
L24
L25
U17
AD27
M28
N27
Y34
Y33
Y30
Y29
Y27
Y25
W32
W31
W28
W26
V34
V33
V30
V29
V27
V25
U32
U31
U28
U26
T34
T33
T30
T29
T27
T25
R32
R31
R28
E24
F21
K18
E21
J17
E19
G19
E18
G18
DQSn8T
DQSn4T/DQ4T
DQSn2T/DQ2T
DQ1T
DQSn2T
DQSn1T/DQ1T
DQS7T
DQ7T
DQSn7T
DQ4T/CQn4T
DQ4T
DQ4T
DQ2T/CQn2T
DQ2T
DQ2T
DQ1T
DQ1T
DQ1T
DQS1T
DQ1T
DQSn1T
DQ1T/CQn1T
DQ1T
DQ1T
DQ7T
DQ7T
DQ7T
DQ6T
DQ4T
DQ4T
DQ4T
DQ3T
DQ2T
DQ2T
DQ2T
DQ2T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ6T
DQ6T
DQ3T
DQ3T
DQ2T
DQ2T
DQ1T
DQ1T
DQS6T
DQ6T
DQSn6T
DQS3T/CQ3T
DQ3T
DQSn3T/DQ3T
DQ2T
DQ2T
DQ2T
DQ1T
DQ1T
DQ1T
DQS5T
DQ5T
DQSn5T
DQ3T/CQn3T
DQ3T
DQ3T
DQ2T
DQ2T
DQ2T
DQ1T
DQ1T
DQ1T
DQ5T
DQ5T
DQ5T
DQ3T
DQ3T
DQ3T
DQ2T
DQ2T
DQ2T
DQ1T
DQ1T
DQ1T
DQ4T
DQ2T
DQ1T
DQ4T
DQ4T
DQ2T
DQ2T
DQ1T
DQ1T
DQS4T
DQ4T
DQSn4T
DQS2T/CQ2T
DQ2T
DQSn2T/DQ2T
DQS1T/CQ1T
DQ1T
DQSn1T/DQ1T
DQS3T
DQ3T
DQSn3T
DQ2T/CQn2T
DQ2T
DQ2T
DQ1T/CQn1T
DQ1T
DQ1T
DQ3T
DQ3T
DQ3T
DQ2T
DQ2T
DQ2T
DQ2T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQS for X32/X36 for
F780 (Note 3)
L21
K19
K21
J18
F20
J19
F19
H19
DQ2T
DQ2T
DQ1T
DQ1T
DQ1T
DQ1T
DQS2T
DQ2T
DQSn2T
DQS1T/CQ1T
DQ1T
DQSn1T/DQ1T
DQ1T
DQ1T
DQ1T
DQS1T
DQ1T
DQSn1T
DQ1T/CQn1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
L23
J22
H22
K22
H24
J23
L24
K24
P14
AB21
G22
K23
Y28
Y27
W26
W25
V28
V27
U26
U25
T28
T27
T24
T22
R26
R25
R23
R21
P28
P27
P24
P22
N26
N25
N23
N21
M28
M27
M24
L26
L25
Pin List
Page 7 of 15
®
Pin Information for the Arria II GX EP2AGX260 Device
Version 1.1
Bank
number
I/O Module
(Note 1)
VREF
Pin Function
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PT-EP2AGX260-1.1
Copyright © 2009 Altera Corp.
Optional
Function
Configuration
Function
Dedicated Tx/Rx
Channel with
OCT Rd
Emulated LVDS Output Channel/
Dedicated LVDS Input Channel with
no OCT Rd (Note 2)
F1152
F780
R26
P34
P33
P30
P29
P28
P26
N32
N31
M34
M33
M30
M29
L32
L31
K34
K33
K30
K29
J32
J31
H34
H33
G32
G31
F34
F33
E32
E31
D34
D33
C32
C31
B34
B33
B30
B29
B28
AP33
AP32
AP30
AN32
AN31
AN30
AM34
AM33
AL32
AL31
AK34
AK33
AJ32
AJ31
AH34
AH33
AG32
AG31
AF34
AF33
AF30
AF29
AE32
AE31
AD34
AD33
AD30
AD29
AC32
AC31
AB34
AB33
AB30
AB29
AB27
AA32
AA31
AA28
AA26
A33
A32
A31
A30
A28
Y23
Y21
Y19
Y17
Y15
Y13
W8
W5
W22
W20
W2
W18
W16
W14
W11
V23
V21
V19
V15
V13
U22
U20
U18
U16
K28
K27
J26
J25
H28
H27
G26
G25
F28
F27
E26
E25
D28
D27
D24
D22
C26
C25
C24
C22
B28
B27
B25
B23
B22
B21
AH26
AH24
AH22
AH20
AG28
AG26
AG24
AG22
AG21
AG20
AF28
AF27
AF26
AF25
AF23
AE26
AE25
AE23
AD28
AD27
AC26
AC25
AB28
AB27
AA26
AA25
A27
A25
A23
A21
Y7
W9
W22
W19
W17
W15
V8
V5
V20
V2
V18
V16
V14
V12
V10
U9
U17
U13
T8
T20
T18
T14
T10
R19
R13
P18
P12
N9
N5
N19
N15
N11
M16
M12
L8
L20
L17
L11
H5
H17
G9
E20
E11
B2
AG8
AG14
AD20
AD11
AA20
AA11
DQS for X4 for F1152
Pin List
DQS for X8/X9 for
F1152 (Note 3)
DQS for X16/X18 for
F1152 (Note3)
DQS for X32/X36 for
F1152 (Note 3)
DQS for X4 for F780
DQS for X8/X9 for F780 DQS for X16/X18 for
(Note 3)
F780 (Note 3)
DQS for X32/X36 for
F780 (Note 3)
Page 8 of 15
®
Pin Information for the Arria II GX EP2AGX260 Device
Version 1.1
Bank
number
I/O Module
(Note 1)
VREF
Pin Function
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PT-EP2AGX260-1.1
Copyright © 2009 Altera Corp.
Optional
Function
Configuration
Function
Dedicated Tx/Rx
Channel with
OCT Rd
Emulated LVDS Output Channel/
Dedicated LVDS Input Channel with
no OCT Rd (Note 2)
F1152
F780
U14
T8
T5
T23
T21
T2
T19
T17
T15
T13
T11
R22
R20
R18
R16
R14
P8
P5
P25
P23
P21
P2
P19
P17
P15
P13
P11
N24
N22
N18
N16
N14
N12
L8
L5
L26
L23
L20
L2
L17
L14
K10
J9
H8
H5
H29
H26
H23
H20
H2
H17
H14
H11
E8
E5
E29
E26
E23
E20
E2
E17
E14
E11
B8
B5
B26
B23
B20
B2
B17
B11
AN5
AN26
AN20
AN17
AN11
AK5
AK26
AK20
AK17
AK11
AG5
AG26
AG20
AG17
AG11
AE10
AD5
AD23
AD2
AD14
AB21
AB17
AB13
AA25
AA2
AA11
B14
AN8
AN29
AN23
AN2
AN14
AK8
AK29
AK23
U19
U15
U11
T5
T2
T16
T12
R9
R17
R11
P16
P10
N8
N2
N17
N13
M18
M14
M10
L5
L2
L14
H8
H2
H11
E23
E14
B20
B11
AG17
AD5
AD14
AA5
AA14
H20
H14
E5
E17
B5
B14
AG2
AD8
AD17
AA8
AA17
E8
E2
B8
B17
AG5
AG11
AD2
AB23
AA2
DQS for X4 for F1152
Pin List
DQS for X8/X9 for
F1152 (Note 3)
DQS for X16/X18 for
F1152 (Note3)
DQS for X32/X36 for
F1152 (Note 3)
DQS for X4 for F780
DQS for X8/X9 for F780 DQS for X16/X18 for
(Note 3)
F780 (Note 3)
DQS for X32/X36 for
F780 (Note 3)
Page 9 of 15
®
Pin Information for the Arria II GX EP2AGX260 Device
Version 1.1
Bank
number
I/O Module
(Note 1)
VREF
Pin Function
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
DNU
DNU
DNU
VCCBAT
VCCA_PLL_1
VCCA_PLL_2
VCCA_PLL_3
VCCA_PLL_4
VCCA_PLL_5
VCCA_PLL_6
VCCD_PLL_1
VCCD_PLL_2
VCCD_PLL_3
VCCD_PLL_4
VCCD_PLL_5
VCCD_PLL_6
VCCIO3A
VCCIO3A
VCCIO3A
VCCIO3A
VCCIO3B
VCCIO3B
VCCIO3C
VCCIO4A
PT-EP2AGX260-1.1
Copyright © 2009 Altera Corp.
Optional
Function
Configuration
Function
Dedicated Tx/Rx
Channel with
OCT Rd
Emulated LVDS Output Channel/
Dedicated LVDS Input Channel with
no OCT Rd (Note 2)
F1152
AK2
AK14
AG8
AG29
AG23
AG2
AG14
AF9
AD8
AD26
AD20
AD17
AB23
AB19
AB15
AA5
AA20
AA14
AA8
AA22
AA16
AA18
V16
Y24
Y22
Y20
Y18
Y16
Y14
W23
W21
W19
W17
W15
W13
V24
V22
V20
V18
V14
U21
U19
U15
U13
T24
T22
T20
T18
T16
T14
R23
R21
R19
R17
R15
R13
P24
P22
P20
P18
P16
P14
P12
N23
N21
N17
N15
N13
AC23
AB24
AB22
AB20
AB18
AB16
AB14
AB12
AA23
AA21
AA19
AA17
AA15
AA13
K25
V17
C4
L27
H25
J10
AF10
AG25
T9
W9
J26
K9
AE9
AF26
U8
V8
AM20
AK24
AJ20
AH22
AF22
AF21
AD25
AM14
F780
DQS for X4 for F1152
DQS for X8/X9 for
F1152 (Note 3)
DQS for X16/X18 for
F1152 (Note3)
DQS for X32/X36 for
F1152 (Note 3)
DQS for X4 for F780
DQS for X8/X9 for F780 DQS for X16/X18 for
(Note 3)
F780 (Note 3)
DQS for X32/X36 for
F780 (Note 3)
P15
W20
W18
W16
W14
V9
V21
V19
V17
V15
V13
V11
U20
U18
U16
U14
U12
U10
T9
T19
T17
T15
T13
T11
R18
R16
R14
R12
R10
P9
P19
P17
P13
P11
N20
N18
N16
N14
N12
N10
M9
M20
M19
M17
M15
M13
M11
L18
L16
L13
L12
L10
K17
H23
R15
F6
J24
G20
H9
Y8
AB20
P8
R7
H21
G8
AA7
AA21
P7
R8
AG16
AD19
AD16
AC20
AG7
Pin List
Page 10 of 15
®
Pin Information for the Arria II GX EP2AGX260 Device
Version 1.1
Bank
number
3A
3B
4A
4B
5A
5B
6A
6B
7A
7B
8A
8B
I/O Module
(Note 1)
VREF
VREFB3AN0
VREFB3BN0
VREFB4AN0
VREFB4BN0
VREFB5AN0
VREFB5BN0
VREFB6AN0
VREFB6BN0
VREFB7AN0
VREFB7BN0
VREFB8AN0
VREFB8BN0
Pin Function
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4B
VCCIO4B
VCCIO5A
VCCIO5A
VCCIO5A
VCCIO5A
VCCIO5B
VCCIO5B
VCCIO6A
VCCIO6A
VCCIO6A
VCCIO6A
VCCIO6B
VCCIO6B
VCCIO7A
VCCIO7A
VCCIO7A
VCCIO7A
VCCIO7B
VCCIO7B
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8B
VCCIO8B
VCCIO8C
VCCPD3A
VCCPD3A
VCCPD3B
VCCPD3C
VCCPD4A
VCCPD4A
VCCPD4B
VCCPD5A
VCCPD5A
VCCPD5B
VCCPD6A
VCCPD6A
VCCPD6B
VCCPD7A
VCCPD7A
VCCPD7B
VCCPD8A
VCCPD8A
VCCPD8B
VCCPD8C
VREFB3AN0
VREFB3BN0
VREFB4AN0
VREFB4BN0
VREFB5AN0
VREFB5BN0
VREFB6AN0
VREFB6BN0
VREFB7AN0
VREFB7BN0
VREFB8AN0
VREFB8BN0
NC
NC
VCCL_GXB
VCCL_GXB
VCCL_GXB
VCCL_GXB
VCCL_GXB
VCCL_GXB
VCCL_GXB
VCCL_GXB
VCCL_GXB
VCCL_GXB
VCCL_GXB
VCCL_GXB
VCCCB
VCCCB
VCCCB
VCCCB
RREF0
RREF1
VCCA
VCCA
VCCA
VCCA
VCCH_GXB
VCCH_GXB
VCCH_GXB
VCCH_GXB
Optional
Function
Configuration
Function
Dedicated Tx/Rx
Channel with
OCT Rd
Emulated LVDS Output Channel/
Dedicated LVDS Input Channel with
no OCT Rd (Note 2)
VREFB3AN0
VREFB3BN0
VREFB4AN0
VREFB4BN0
VREFB5AN0
VREFB5BN0
VREFB6AN0
VREFB6BN0
VREFB7AN0
VREFB7BN0
VREFB8AN0
VREFB8BN0
F1152
F780
AM11
AL17
AJ17
AJ14
AH11
AJ8
AG3
AD3
AA6
AA3
AJ5
AH8
T6
T3
P3
L3
L6
H6
F14
F11
C14
C11
D8
G8
F22
F20
C23
C20
C17
J23
H22
K26
AC20
AC19
AC21
AC24
AD16
AC16
AC13
Y12
AA12
AC12
T12
R12
M11
M15
M14
L12
M19
L19
M22
M24
AE20
AE22
AD15
AD13
AB11
AD11
N11
M12
L15
K13
K19
M23
AL30
AM30
W25
V28
V26
U27
U25
T28
T26
R27
R25
Y28
Y26
W27
U23
U12
L18
AD18
AP31
A29
U24
R24
AA24
W24
P27
N28
AB28
AA27
AG13
AG10
AD13
AD10
DQS for X4 for F1152
DQS for X8/X9 for
F1152 (Note 3)
DQS for X16/X18 for
F1152 (Note3)
DQS for X32/X36 for
F1152 (Note 3)
DQS for X4 for F780
DQS for X8/X9 for F780 DQS for X16/X18 for
(Note 3)
F780 (Note 3)
DQS for X32/X36 for
F780 (Note 3)
Y2
U2
R2
AE2
K2
G2
D2
B7
B4
B13
B10
F18
E16
C20
B18
G23
AB18
AA18
Y21
AA13
AA12
U8
U7
M8
M7
J13
H13
H16
G16
G21
Y17
AB12
W7
L9
H12
H18
AF21
AF22
R22
P23
P21
N24
N22
M23
T23
T21
R24
Y15
N7
J15
P20
AH21
A22
R20
M21
U21
U23
U22
M22
L22
Notes:
(1) An I/O module is a group of 16 I/O pins.
(2) When not used as DIFFIN or DIFFIO_TX, all pins marked with * (DIFFIN_[##]p/n) can be configured as emulated LVDS output channels (DIFFOUT).
Only DIFFIN pins of the same index group (e.g DIFFIN_B1p and DIFFIN_B1n) can be used to form an emulated LVDS output channel.
(3) When not used as clocks, the CQn and DQSn pins can be used as DQ pins.
PT-EP2AGX260-1.1
Copyright © 2009 Altera Corp.
Pin List
Page 11 of 15
Pin Information for the Arria® II GX EP2AGX260 Device
Version 1.1
Notes (1), (2), (3)
Pin Type (1st and 2nd
Function)
Pin Name
Clock and PLL Pins
CLK[4:15]
DIFFCLK[0:5]p
DIFFCLK[0:5]n
PLL_[1:4]_CLKOUT1p
Clock, Input
Clock, Input
Clock, Input
I/O, Clock
PLL_[1:4]_CLKOUT1n
I/O, Clock
PLL_[1,3]_CLKOUT[2:3]p
(Note 4)
PLL_[1,3]_CLKOUT[2:3]n
(Note 4)
Dedicated Configuration/JTAG Pins
nIO_PULLUP
I/O, Clock
Input
MSEL[0:3]
nCE
nCONFIG
Input
Input
Input
CONF_DONE
Bidirectional
(open-drain)
nCEO
I/O, Output
(open-drain)
Bidirectional
(open-drain)
Output that drives low when device configuration is complete. This pin can be used as a regular I/O if not used for device configuration.
Input
Input
Input
Output
Dedicated JTAG test clock input pin.
Dedicated JTAG test mode select input pin.
Dedicated JTAG test data input pin.
Dedicated JTAG test data output pin.
Output
Output
I/O (PS, FPP)
Output (AS)
I/O, Output
(open-drain)
I/O, Input
Dedicated output control signal from the FPGA to the serial configuration device in AS mode that enables the configuration device.
Control signal from the FPGA to the serial configuration device in AS mode used to read out configuration data.
Dedicated configuration clock pin. In PS and FPP configuration, DCLK is used to clock configuration data from an external source into the FPGA. In AS mode, DCLK is an output from the FPGA that provides timing for the
configuration interface.
Active high signal that indicates that the error detection circuit has detected errors in the configuration SRAM bits. This pin is optional and is used when the CRC error detection circuit is enabled. This pin can be used as
regular I/O if not used for CRC error detection.
Optional pin that allows designers to override all clears on all device registers. When this pin is driven low, all registers are cleared; when this pin is driven high, all registers behave as programmed.
nSTATUS
TCK
TMS
TDI
TDO
Optional/Dual-Purpose Configuration Pins
nCSO
ASDO
DCLK
CRC_ERROR
DEV_CLRn
Pin Description
Single ended clock input pin.
Clock input pin for differential clock input. OCT Rd is not supported.
Negative clock input for differential clock input. OCT Rd is not supported
PLL[1:4]_CLKOUT1 (except PLL1 and PLL3 in EP2AGX125 and EP2AGX260) supports 2 clock I/O pins, configured either as one single ended I/O or one differential I/O pair. PLL1 and PLL3 in EP2AGX125 and
EP2AGX260 support 6 clock I/O pins, configured either as 3 single ended I/Os or 3 differential I/O pairs.
PLL1 and PLL3 in EP2AGX125 and EP2AGX260 support 6 clock I/O pins, configured either as 3 single ended I/Os or 3 differential I/O pairs.
I/O, Clock
Dedicated input that chooses whether the internal pull-ups on the user I/O pins and dual-purpose I/O pins (nCSO, ASDO, DATA[7:0], CLKUSR, INIT_DONE, DEV_OE, DEV_CLRn) are on or off before and during
configuration. A logic high (1.5V, 1.8V, 2.5V, 3.0V or 3.3V) turns off the weak pull-up, while a logic low turns them on.
Configuration input pins that set the FPGA device configuration scheme.
Dedicated active-low chip enable. When nCE is low, the device is enabled. When nCE is high, the device is disabled.
Dedicated configuration control input. Pulling this pin low during user-mode will cause the FPGA to lose its configuration data, enter a reset state, and tri-state all I/O pins. Returning this pin to a logic high level will initiate
reconfiguration.
This is a dedicated configuration done pin. As a status output, the CONF_DONE pin drives low before and during configuration. Once all configuration data is received without error and the initialization cycle starts,
CONF_DONE is released. As a status input, CONF_DONE goes high after all data is received. Then the device initializes and enters user mode. It is not available as a user I/O pin.
This is a dedicated configuration status pin. The FPGA drives nSTATUS low immediately after power-up and releases it after POR time. As a status output, the nSTATUS is pulled low if an error occurs during
configuration. As a status input, the device enters an error state when nSTATUS is driven low by an external source during configuration or initialization. It is not available as an user I/O pin.
DEV_OE
I/O, Input
Optional pin that allows designers to override all tri-states on the device. When this pin is driven low, all I/O pins are tri-stated; when this pin is driven high, all I/O pins behave as defined in the design.
DATA0
DATA[1:7]
INIT_DONE
Input
I/O, Input
I/O, Output
(open-drain)
I/O, Input
DATA[0] is a dedicated pin that is used for both the passive and active configuration modes
Dual-purpose configuration input data pins. The DATA[0:7] pins can be used for byte-wide configuration. DATA[1:7] pins can also be used as user I/O pins after configuration, but not DATA0.
This is a dual-purpose pin and can be used as an I/O pin when not enabled as INIT_DONE. When enabled, a transition from low to high at the pin indicates when the device has entered user mode. If the INIT_DONE
output is enabled, the INIT_DONE pin cannot be used as a user I/O pin after configuration.
Optional user-supplied clock input. Synchronizes the initialization of one or more devices. If this pin is not enabled for use as a user-supplied configuration clock, it can be used as a user I/O pin.
I/O, RX channel
These are true LVDS receiver channels with OCT Rd support. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not
used for differential signaling, these pins are available as user I/O pins.
These are true LVDS transmitter channels. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used as true LVDS
transmitter channels, these pins can be configured as true LVDS receiver channels without OCT Rd support (DIFFIN_[T,B,R][##][p,n]). If not used for differential signaling, these pins are available as user I/O pins.
CLKUSR
Differential I/O Pins
DIFFIO_RX_[T,B,R][##]p,
DIFFIO_RX_[T,B,R][##]n
DIFFIO_TX_[T,B,R][##]p,
DIFFIO_TX_[T,B,R][##]n
I/O, TX channel
DIFFIN_[T,B,R][##]p,
DIFFIN_[T,B,R][##]n
I/O, RX channel
DIFFOUT_[##]p,
DIFFOUT_[##]n
I/O, TX channel
These are true LVDS receiver channels without OCT Rd support. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not
used as true LVDS receiver channels without OCT Rd support, these pins can be configured as true LVDS transmitter channels (DIFFIO_TX_[T,B,R][##][p,n]). If not used for differential signaling, these pins are available
as user I/O pin.
These are emulated LVDS output channels. On I/O banks, there are true LVDS input buffers but no true LVDS output buffers. However, all column user I/Os, including I/Os with true LVDS input buffers,
(DIFFIO_RX_[T,B,R][##][p,n] , DIFFIN_[T,B,R][##][p,n]) can be configured as emulated LVDS output buffers. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the
negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins.
External Memory Interface Pins
DQS[##][T,B,R]
I/O, DQS
Optional data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry. The shifted DQS signal can also drive to internal logic.
DQSn[##][T,B,R] (Note 5)
DQ[##][T,B,R]
I/O, DQSn
I/O, DQ
CQ[##][T,B,R]
CQn[##][T,B,R] (Note 5)
Reference Pins
RUP[0:2]
DQS
DQS
Optional complementary data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry.
Optional data signal for use in external memory interfacing. The order of the DQ bits within a designated DQ bus is not important; however, use caution when making pin assignments if you plan on migrating to a different
memory interface that has a different DQ bus width. Analyze the available DQ pins across all pertinent DQS columns in the pin list.
Optional data strobe signal for use in QDRII SRAM. These are the pins for echo clocks.
Optional complementary data strobe signal for use in QDRII SRAM. These are the pins for echo clocks.
RDN[0:2]
I/O, Input
DNU
NC
Do Not Use
No Connect
PT-EP2AGX260-1.1
Copyright © 2009 Altera Corp.
I/O, Input
Reference pins for I/O banks. The RUP pins share the same VCCIO with the I/O bank where they are located. The external precision resistor RUP must be connected to the designated RUP pin within the bank. If not
required, this pin is a regular I/O pin.
Reference pins for I/O banks. The RDN pins share the same GND with the I/O bank where they are located. The external precision resistor RDN must be connected to the designated RDN pin within the bank. If not
required, this pin is a regular I/O pin.
Do Not Use (DNU).
Do not drive signals into these pins.
Pin Definitions
Page 12 of 15
Pin Information for the Arria® II GX EP2AGX260 Device
Version 1.1
Notes (1), (2), (3)
Pin Type (1st and 2nd
Function)
Pin Name
Supply Pins
VCC
VCCD_PLL_[1:6]
VCCCB
VCCA_PLL_[1:6]
VCCIO[3:8][A,B]
Power
Power
Power
Power
Power
VCCIO[3,8]C
Power
VCCPD[3:8][A,B],
VCCPD[3,8]C
VCCBAT
GND
VREF[3:8][A,B]N0
Power
Transceiver Pins
VCCL_GXB
VCCH_GXB
VCCA
GXB_RX[0:15]p (Note 6)
GXB_RX[0:15]n (Note 6)
GXB_TX[0:15]p (Note 6)
GXB_TX[0:15]n (Note 6)
REFCLK[0:7]p
REFCLK[0:7]n
RREF[0:1]
Pin Description
Power
Ground
Power
VCC supplies power to the core and periphery.
Digital power for PLL[1:6]. All of these pins must be connected even if the PLL is not used
Configuration RAM bits power supply.
Analog power for PLL [1:6]. All of these pins must be connected even if the PLL is not used
These are I/O supply voltage pins for banks 3 through 8. Each bank can support a different voltage level. VCCIO supplies power to the output buffers for all LVDS, LVCMOS(1.2V, 1.5V, 1.8V, 2.5V, 3.0V,3.3V),
HSTL(12,15,18),SSTL(15,18,2),3.0V PCI/PCI-X I/O as well as LVTTL (1.8V, 2.5V, 3.0V, 3.3V) I/O standards. VCCIO also supplies power to the input buffers used for LVCMOS(1.2V, 1.5V, 1.8V, 2.5V, 3.0V, 3.3V), 3.0V
PCI/PCI-X and LVTTL (1.8V, 2.5V, 3.0V, 3.3V) I/O standards.
These are configuration and JTAG supply voltage pins for banks 3C and 8C. Each bank can support a different voltage level. For AS/PP/FPP configuration schemes, VCCIO8C supports 1.8V, 2.5V, 3.0V or 3.3V. JTAG
can support 1.5V, 1.8V, 2.5V, 3.0V or 3.3V.
Dedicated power pins. This supply is used to power the I/O pre-drivers and the input buffers for HSTL/SSTL input buffers. This can be connected to 3.3V, 3.0V or 2.5V. For 3.3V I/O standard connect VCCPD to 3.3V, for
3.0V I/O standard connect VCCPD to 3.0V and for 2.5V/1.8V/1.2V I/O standards connect VCCPD to 2.5V
Battery back-up power supply for design security volatile key register.
Device ground pins.
Input reference voltage for each I/O bank. If a bank uses a voltage-referenced I/O standard, then these pins are used as the voltage-reference pins for the bank. These pins cannot be used as regular I/Os.
Power
Power
Power
Input
Input
Output
Output
Input
Input
Input
Supplies power to the transceiver PMA TX, PMA RX and clocking.
Supplies power to the transceiver PMA output (TX) buffer.
Supplies power to the transceiver PMA regulator.
High speed positive differential receiver channels.
High speed negative differential receiver channels.
High speed positive differential transmitter channels.
High speed negative differential transmitter channels.
High speed differential reference clock positive.
High speed differential reference clock complement.
Reference resistor for transceiver.
Notes:
1. Refer to the Arria II GX Device Datasheet and Pin Connection Guidelines for the recommended operating conditions.
2. This pin definition is prepared based on the EP2AGX260.
3. Some of the pull-up /pull down resisitors mentioned in the table above may not be required, depending on the exact device configuration scheme.
The ability to NC or short them may be valuable during the debug phase, should you be required to use a different configuration scheme.
Refer to the Configuring Arria II GX Devices chapter in the Arria II GX Device Handbook for more information.
4. PLL[1,3]_CLKOUT[2..3][p,n] are only available in PLL1 and PLL3 in EP2AGX125 and EP2AGX260.
5. When not used as clocks, the CQn and DQSn pins can be used as DQ pin.
6. Transceiver signals GXB_RX[15..0] and GXB_TX[15..0] are device specific.
PT-EP2AGX260-1.1
Copyright © 2009 Altera Corp.
Pin Definitions
Page 13 of 15
Pin Information for the Arria® II GX EP2AGX260 Device
Version 1.1
8B
8A
7A
7B
VREFB8BN0
VREFB8AN0
VREFB7AN0
VREFB7BN0
6B
6A
Transceiver Block
(QL2)
Transceiver Block
(QL1)
PLL_5
5B
3C
3B
VREFB3BN0
3A
VREFB3AN0
4A
VREFB4CN0
4B
VREFB4BN0
VREFB5BN0 VREFB5AN0
5A
PLL_6
Transceiver Block
(QL0)
PLL_4
PLL_2
VREFB6AN0 VREFB6BN0
8C
Transceiver Block
(QL3)
PLL_1
PLL_3
This is a top view of the silicon die that corresponds to a reverse view for flip chip packages. It is a graphical representation only.
PT-EP2AGX260-1.1
Copyright © 2009 Altera Corp.
Bank & PLL Diagram
Page 14 of 15
Pin Information for the Arria® II GX EP2AGX260 Device
Version 1.1
Version Number
1.0
1.1
PT-EP2AGX260-1.1
Copyright © 2009 Altera Corp.
Date
2/27/2009
5/29/2009
Changes Made
Initial release.
Added DNU in Pin List and Pin Definitions.
Revision History
Page 15 of 15