Pin Information for HardCopy® III HC335FF1517 Version 1.0 Bank Number VREF Group 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 Pin Name /Function TDI TMS TRST TCK TDO PLL_L1_CLKn PLL_L1_CLKp IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Optional Function(s) PLL_L1_CLKn PLL_L1_CLKp PLL_L1_CLKOUT0n PLL_L1_FB_CLKOUT0p RDN1A RUP1A Configuration Function for Stratix III Dedicated Tx_Rx Only (1) Channel (2) TDI TMS TRST TCK TDO DIFFIO_TX_L1n DIFFIO_TX_L1p DIFFIO_RX_L1n DIFFIO_RX_L1p DIFFIO_TX_L2n DIFFIO_TX_L2p DIFFIO_RX_L2n DIFFIO_RX_L2p DIFFIO_TX_L3n DIFFIO_TX_L3p DIFFIO_RX_L3n DIFFIO_RX_L3p DIFFIO_TX_L4n DIFFIO_TX_L4p DIFFIO_RX_L4n DIFFIO_RX_L4p DIFFIO_TX_L5n DIFFIO_TX_L5p DIFFIO_RX_L5n DIFFIO_RX_L5p DIFFIO_TX_L6n DIFFIO_TX_L6p DIFFIO_RX_L6n DIFFIO_RX_L6p DIFFIO_TX_L7n DIFFIO_TX_L7p DIFFIO_RX_L7n DIFFIO_RX_L7p DIFFIO_TX_L8n DIFFIO_TX_L8p DIFFIO_RX_L8n DIFFIO_RX_L8p DIFFIO_TX_L9n DIFFIO_TX_L9p DIFFIO_RX_L9n DIFFIO_RX_L9p DIFFIO_TX_L10n DIFFIO_TX_L10p DIFFIO_RX_L10n DIFFIO_RX_L10p DIFFIO_TX_L11n DIFFIO_TX_L11p DIFFIO_RX_L11n Emulated LVDS Output Channel (2) DIFFOUT_L1n DIFFOUT_L1p DIFFOUT_L2n DIFFOUT_L2p DIFFOUT_L3n DIFFOUT_L3p DIFFOUT_L4n DIFFOUT_L4p DIFFOUT_L5n DIFFOUT_L5p DIFFOUT_L6n DIFFOUT_L6p DIFFOUT_L7n DIFFOUT_L7p DIFFOUT_L8n DIFFOUT_L8p DIFFOUT_L9n DIFFOUT_L9p DIFFOUT_L10n DIFFOUT_L10p DIFFOUT_L11n DIFFOUT_L11p DIFFOUT_L12n DIFFOUT_L12p DIFFOUT_L13n DIFFOUT_L13p DIFFOUT_L14n DIFFOUT_L14p DIFFOUT_L15n DIFFOUT_L15p DIFFOUT_L16n DIFFOUT_L16p DIFFOUT_L17n DIFFOUT_L17p DIFFOUT_L18n DIFFOUT_L18p DIFFOUT_L19n DIFFOUT_L19p DIFFOUT_L20n DIFFOUT_L20p DIFFOUT_L21n DIFFOUT_L21p DIFFOUT_L22n Pin List DQ Group for F1517 DQS X4 Mode (2) G34 F34 C37 D36 F35 C39 C38 J33 K32 G35 H34 J35 DQ1L J34 DQ1L E37 DQSn1L E36 DQS1L K35 DQ1L K34 DQ1L D38 DQSn2L D37 DQS2L L34 DQ2L L33 DQ2L F36 DQ2L G36 DQ2L M34 DQ3L M33 DQ3L D39 DQSn3L E39 DQS3L M32 DQ3L N31 DQ3L F39 DQSn4L F38 DQS4L J37 DQ4L J36 DQ4L H37 DQ4L H36 DQ4L M29 DQ5L M28 DQ5L G38 DQSn5L G37 DQS5L N30 DQ5L N29 DQ5L G39 DQSn6L H39 DQS6L L37 DQ6L L36 DQ6L J39 DQ6L J38 DQ6L P28 DQ7L N27 DQ7L K38 DQSn7L DQ Group for DQS X8/X9 Mode (2) DQ1L DQ1L DQ1L DQ1L/CQn1L DQ1L DQ1L DQSn1L/DQ1L DQS1L/CQ1L DQ1L DQ1L DQ1L DQ1L DQ2L DQ2L DQ2L DQ2L/CQn2L DQ2L DQ2L DQSn2L/DQ2L DQS2L/CQ2L DQ2L DQ2L DQ2L DQ2L DQ3L DQ3L DQ3L DQ3L/CQn3L DQ3L DQ3L DQSn3L/DQ3L DQS3L/CQ3L DQ3L DQ3L DQ3L DQ3L DQ Group for DQS X16/X18 Mode (2) DQ Group for DQS X32/X36 Mode (2) DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L/CQn1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQSn1L/DQ1L DQS1L/CQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L Page 1 of 35 Pin Information for HardCopy® III HC335FF1517 Version 1.0 Bank Number 1A 1A 1A 1A 1A 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 2C 2C 2C VREF Group VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 Pin Name /Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO CLK1n CLK1p CLK3p CLK3n IO PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Optional Function(s) PLL_L2_CLKOUT0n PLL_L2_FB_CLKOUT0p CLK0n CLK0p CLK1n CLK1p CLK3p CLK3n CLK2p Configuration Function for Stratix III Dedicated Tx_Rx Only (1) Channel (2) DIFFIO_RX_L11p DIFFIO_TX_L12n DIFFIO_TX_L12p DIFFIO_RX_L12n DIFFIO_RX_L12p DIFFIO_TX_L13n DIFFIO_TX_L13p DIFFIO_RX_L13n DIFFIO_RX_L13p DIFFIO_TX_L14n DIFFIO_TX_L14p DIFFIO_RX_L14n DIFFIO_RX_L14p DIFFIO_TX_L15n DIFFIO_TX_L15p DIFFIO_RX_L15n DIFFIO_RX_L15p DIFFIO_TX_L16n DIFFIO_TX_L16p DIFFIO_RX_L16n DIFFIO_RX_L16p DIFFIO_TX_L17n DIFFIO_TX_L17p DIFFIO_RX_L17n DIFFIO_RX_L17p DIFFIO_TX_L18n DIFFIO_TX_L18p DIFFIO_RX_L18n DIFFIO_RX_L18p DATA0 DIFFIO_TX_L19n DIFFIO_TX_L19p DIFFIO_RX_L19n DIFFIO_RX_L19p DIFFIO_TX_L20n DIFFIO_TX_L20p DIFFIO_RX_L20n DIFFIO_RX_L20p INIT_DONE DIFFIO_TX_L21n DIFFIO_TX_L21p DEV_OE DIFFIO_RX_L21n DEV_CLRn DIFFIO_RX_L21p DIFFIO_TX_L22n DIFFIO_TX_L22p DIFFIO_RX_L22n DIFFIO_RX_L22p DIFFIO_RX_L23p Emulated LVDS Output Channel (2) DIFFOUT_L22p DIFFOUT_L23n DIFFOUT_L23p DIFFOUT_L24n DIFFOUT_L24p DIFFOUT_L25n DIFFOUT_L25p DIFFOUT_L26n DIFFOUT_L26p DIFFOUT_L27n DIFFOUT_L27p DIFFOUT_L28n DIFFOUT_L28p DIFFOUT_L29n DIFFOUT_L29p DIFFOUT_L30n DIFFOUT_L30p DIFFOUT_L31n DIFFOUT_L31p DIFFOUT_L32n DIFFOUT_L32p DIFFOUT_L33n DIFFOUT_L33p DIFFOUT_L34n DIFFOUT_L34p DIFFOUT_L35n DIFFOUT_L35p DIFFOUT_L36n DIFFOUT_L36p DIFFOUT_L37n DIFFOUT_L37p DIFFOUT_L38n DIFFOUT_L38p DIFFOUT_L39n DIFFOUT_L39p DIFFOUT_L40n DIFFOUT_L40p DIFFOUT_L41n DIFFOUT_L41p DIFFOUT_L42n DIFFOUT_L42p DIFFOUT_L43n DIFFOUT_L43p DIFFOUT_L44n DIFFOUT_L44p DIFFOUT_L45p Pin List DQ Group for F1517 DQS X4 Mode (2) K37 DQS7L R27 DQ7L R26 DQ7L K39 L39 R36 DQ8L R35 DQ8L T36 DQSn8L T35 DQS8L T33 DQ8L T32 DQ8L P37 DQSn9L P36 DQS9L R34 DQ9L T34 DQ9L R38 DQ9L R37 DQ9L U31 DQ10L U30 DQ10L P39 DQSn10L R39 DQS10L V29 DQ10L V28 DQ10L T39 DQSn11L T38 DQS11L U34 DQ11L U33 DQ11L U37 DQ11L U36 DQ11L W29 DQ12L W28 DQ12L U39 DQSn12L V39 DQS12L V31 DQ12L W30 DQ12L V38 DQSn13L V37 DQS13L V33 DQ13L W33 DQ13L V36 DQ13L V35 DQ13L W35 W34 W37 W36 W39 W38 AA38 AA39 Y36 DQ Group for DQS X8/X9 Mode (2) DQ8L DQ8L DQ8L DQ8L/CQn8L DQ8L DQ8L DQSn8L/DQ8L DQS8L/CQ8L DQ8L DQ8L DQ8L DQ8L DQ9L DQ9L DQ9L DQ9L/CQn9L DQ9L DQ9L DQSn9L/DQ9L DQS9L/CQ9L DQ9L DQ9L DQ9L DQ9L DQ10L DQ10L DQ10L DQ10L/CQn10L DQ10L DQ10L DQSn10L/DQ10L DQS10L/CQ10L DQ10L DQ10L DQ10L DQ10L DQ Group for DQS X16/X18 Mode (2) DQ Group for DQS X32/X36 Mode (2) DQ8L DQ8L DQ8L DQ8L DQ8L DQ8L DQ8L DQ8L/CQn8L DQ8L DQ8L DQ8L DQ8L DQ8L DQ8L DQSn8L/DQ8L DQS8L/CQ8L DQ8L DQ8L DQ8L DQ8L DQ8L DQ8L DQ8L DQ8L Page 2 of 35 Pin Information for HardCopy® III HC335FF1517 Version 1.0 Bank Number 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A VREF Group VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 Pin Name /Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Optional Function(s) CLK2n PLL_L3_FB_CLKOUT0p PLL_L3_CLKOUT0n Configuration Function for Stratix III Dedicated Tx_Rx Only (1) Channel (2) DIFFIO_RX_L23n DIFFIO_TX_L23p DIFFIO_TX_L23n DIFFIO_RX_L24p DIFFIO_RX_L24n DIFFIO_TX_L24p DIFFIO_TX_L24n DIFFIO_RX_L25p DIFFIO_RX_L25n DIFFIO_TX_L25p DIFFIO_TX_L25n DIFFIO_RX_L26p DIFFIO_RX_L26n DIFFIO_TX_L26p DIFFIO_TX_L26n DIFFIO_RX_L27p DIFFIO_RX_L27n DIFFIO_TX_L27p DIFFIO_TX_L27n DIFFIO_RX_L28p DIFFIO_RX_L28n DIFFIO_TX_L28p DIFFIO_TX_L28n DIFFIO_RX_L29p DIFFIO_RX_L29n DIFFIO_TX_L29p DIFFIO_TX_L29n DIFFIO_RX_L30p DIFFIO_RX_L30n DIFFIO_TX_L30p DIFFIO_TX_L30n DIFFIO_RX_L31p DIFFIO_RX_L31n DIFFIO_TX_L31p DIFFIO_TX_L31n DIFFIO_RX_L32p DIFFIO_RX_L32n DIFFIO_TX_L32p DIFFIO_TX_L32n DIFFIO_RX_L33p DIFFIO_RX_L33n DIFFIO_TX_L33p DIFFIO_TX_L33n DIFFIO_RX_L34p DIFFIO_RX_L34n DIFFIO_TX_L34p DIFFIO_TX_L34n DIFFIO_RX_L35p DIFFIO_RX_L35n DIFFIO_TX_L35p Emulated LVDS Output Channel (2) DIFFOUT_L45n DIFFOUT_L46p DIFFOUT_L46n DIFFOUT_L47p DIFFOUT_L47n DIFFOUT_L48p DIFFOUT_L48n DIFFOUT_L49p DIFFOUT_L49n DIFFOUT_L50p DIFFOUT_L50n DIFFOUT_L51p DIFFOUT_L51n DIFFOUT_L52p DIFFOUT_L52n DIFFOUT_L53p DIFFOUT_L53n DIFFOUT_L54p DIFFOUT_L54n DIFFOUT_L55p DIFFOUT_L55n DIFFOUT_L56p DIFFOUT_L56n DIFFOUT_L57p DIFFOUT_L57n DIFFOUT_L58p DIFFOUT_L58n DIFFOUT_L59p DIFFOUT_L59n DIFFOUT_L60p DIFFOUT_L60n DIFFOUT_L61p DIFFOUT_L61n DIFFOUT_L62p DIFFOUT_L62n DIFFOUT_L63p DIFFOUT_L63n DIFFOUT_L64p DIFFOUT_L64n DIFFOUT_L65p DIFFOUT_L65n DIFFOUT_L66p DIFFOUT_L66n DIFFOUT_L67p DIFFOUT_L67n DIFFOUT_L68p DIFFOUT_L68n DIFFOUT_L69p DIFFOUT_L69n DIFFOUT_L70p Pin List DQ Group for F1517 DQS X4 Mode (2) Y37 AA34 AA35 AA36 DQ14L AA37 DQ14L AB34 DQ14L AB35 DQ14L AB38 DQS14L AB39 DQSn14L AB32 DQ15L AA33 DQ15L AB36 DQS15L AB37 DQSn15L AC33 DQ15L AC34 DQ15L AC39 DQ16L AD39 DQ16L Y30 DQ16L Y31 DQ16L AC36 DQS16L AC37 DQSn16L AA30 DQ17L AB31 DQ17L AF39 DQS17L AE39 DQSn17L AA28 DQ17L Y28 DQ17L AD38 DQ18L AE38 DQ18L AB29 DQ18L AA29 DQ18L AE36 DQS18L AE37 DQSn18L AC30 DQ19L AC31 DQ19L AD35 DQS19L AD36 DQSn19L AD33 DQ19L AD34 DQ19L AK39 AJ39 AE27 DQ20L AE28 DQ20L AJ36 DQS20L AJ37 DQSn20L AH35 DQ20L AH36 DQ20L AL38 DQ21L AL39 DQ21L AH33 DQ21L DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) DQ17L DQ17L DQ17L DQ17L DQS17L/CQ17L DQSn17L/DQ17L DQ17L DQ17L DQ17L/CQn17L DQ17L DQ17L DQ17L DQ18L DQ18L DQ18L DQ18L DQS18L/CQ18L DQSn18L/DQ18L DQ18L DQ18L DQ18L/CQn18L DQ18L DQ18L DQ18L DQ19L DQ19L DQ19L DQ19L DQS19L/CQ19L DQSn19L/DQ19L DQ19L DQ19L DQ19L/CQn19L DQ19L DQ19L DQ19L DQ19L DQ19L DQ19L DQ19L DQ19L DQ19L DQ19L DQ19L DQS19L/CQ19L DQSn19L/DQ19L DQ19L DQ19L DQ19L DQ19L DQ19L DQ19L DQ19L/CQn19L DQ19L DQ19L DQ19L DQ19L DQ19L DQ19L DQ19L DQ Group for DQS X32/X36 Mode (2) DQ24L DQ24L DQ24L Page 3 of 35 Pin Information for HardCopy® III HC335FF1517 Version 1.0 Bank Number 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 3A 3A 3A 3A 3A 3A VREF Group VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 Pin Name /Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PLL_L4_CLKp PLL_L4_CLKn nCONFIG nSTATUS CONF_DONE PORSEL nCE IO IO IO IO IO IO PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Optional Function(s) RUP2A RDN2A PLL_L4_FB_CLKOUT0p PLL_L4_CLKOUT0n PLL_L4_CLKp PLL_L4_CLKn Configuration Function for Stratix III Dedicated Tx_Rx Only (1) Channel (2) DIFFIO_TX_L35n DIFFIO_RX_L36p DIFFIO_RX_L36n DIFFIO_TX_L36p DIFFIO_TX_L36n DIFFIO_RX_L37p DIFFIO_RX_L37n DIFFIO_TX_L37p DIFFIO_TX_L37n DIFFIO_RX_L38p DIFFIO_RX_L38n DIFFIO_TX_L38p DIFFIO_TX_L38n DIFFIO_RX_L39p DIFFIO_RX_L39n DIFFIO_TX_L39p DIFFIO_TX_L39n DIFFIO_RX_L40p DIFFIO_RX_L40n DIFFIO_TX_L40p DIFFIO_TX_L40n DIFFIO_RX_L41p DIFFIO_RX_L41n DIFFIO_TX_L41p DIFFIO_TX_L41n DIFFIO_RX_L42p DIFFIO_RX_L42n DIFFIO_TX_L42p DIFFIO_TX_L42n DIFFIO_RX_L43p DIFFIO_RX_L43n DIFFIO_TX_L43p DIFFIO_TX_L43n DIFFIO_RX_L44p DIFFIO_RX_L44n DIFFIO_TX_L44p DIFFIO_TX_L44n Emulated LVDS Output Channel (2) DIFFOUT_L70n DIFFOUT_L71p DIFFOUT_L71n DIFFOUT_L72p DIFFOUT_L72n DIFFOUT_L73p DIFFOUT_L73n DIFFOUT_L74p DIFFOUT_L74n DIFFOUT_L75p DIFFOUT_L75n DIFFOUT_L76p DIFFOUT_L76n DIFFOUT_L77p DIFFOUT_L77n DIFFOUT_L78p DIFFOUT_L78n DIFFOUT_L79p DIFFOUT_L79n DIFFOUT_L80p DIFFOUT_L80n DIFFOUT_L81p DIFFOUT_L81n DIFFOUT_L82p DIFFOUT_L82n DIFFOUT_L83p DIFFOUT_L83n DIFFOUT_L84p DIFFOUT_L84n DIFFOUT_L85p DIFFOUT_L85n DIFFOUT_L86p DIFFOUT_L86n DIFFOUT_L87p DIFFOUT_L87n DIFFOUT_L88p DIFFOUT_L88n nCONFIG nSTATUS CONF_DONE PORSEL nCE RDN3A RUP3A DIFFIO_RX_B1n DIFFIO_RX_B1p DIFFOUT_B1n DIFFOUT_B1p DIFFOUT_B2n DIFFOUT_B2p DIFFOUT_B3n DIFFOUT_B3p Pin List F1517 AG34 AN39 AM39 AG32 AG33 AL37 AK38 AF30 AF31 AP38 AN38 AF28 AG29 AM36 AM37 AG30 AG31 AL35 AL36 AH31 AH32 AN36 AN37 AK35 AK36 AR39 AP39 AK33 AK34 AT38 AT39 AJ33 AJ34 AP36 AR37 AL33 AL34 AU38 AU39 AG28 AN35 AT37 AM34 AH29 AM30 AM31 AN30 AN29 AN31 AL31 DQ Group for DQS X16/X18 Mode (2) DQ Group for DQS X4 Mode (2) DQ21L DQS21L DQSn21L DQ22L DQ22L DQS22L DQSn22L DQ22L DQ22L DQ23L DQ23L DQ23L DQ23L DQS23L DQSn23L DQ24L DQ24L DQS24L DQSn24L DQ24L DQ24L DQ25L DQ25L DQ25L DQ25L DQS25L DQSn25L DQ26L DQ26L DQS26L DQSn26L DQ26L DQ26L DQ Group for DQS X8/X9 Mode (2) DQ24L DQS24L/CQ24L DQSn24L/DQ24L DQ24L DQ24L DQ24L/CQn24L DQ24L DQ24L DQ24L DQ25L DQ25L DQ25L DQ25L DQS25L/CQ25L DQSn25L/DQ25L DQ25L DQ25L DQ25L/CQn25L DQ25L DQ25L DQ25L DQ26L DQ26L DQ26L DQ26L DQS26L/CQ26L DQSn26L/DQ26L DQ26L DQ26L DQ26L/CQn26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQS26L/CQ26L DQSn26L/DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L/CQn26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ1B DQ1B DQSn1B DQS1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B/CQn1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ Group for DQS X32/X36 Mode (2) DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B Page 4 of 35 Pin Information for HardCopy® III HC335FF1517 Version 1.0 Bank Number 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3B 3B 3B 3B 3B 3B 3B 3B VREF Group VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 Pin Name /Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Optional Function(s) Configuration Function for Stratix III Dedicated Tx_Rx Only (1) Channel (2) DIFFIO_RX_B2n DIFFIO_RX_B2p DIFFIO_RX_B3n DIFFIO_RX_B3p DIFFIO_RX_B4n DIFFIO_RX_B4p DIFFIO_RX_B5n DIFFIO_RX_B5p DIFFIO_RX_B6n DIFFIO_RX_B6p DIFFIO_RX_B7n DIFFIO_RX_B7p DIFFIO_RX_B8n DIFFIO_RX_B8p DIFFIO_RX_B9n DIFFIO_RX_B9p DIFFIO_RX_B10n DIFFIO_RX_B10p DIFFIO_RX_B11n DIFFIO_RX_B11p DIFFIO_RX_B12n DIFFIO_RX_B12p DIFFIO_RX_B13n DIFFIO_RX_B13p DIFFIO_RX_B14n DIFFIO_RX_B14p Emulated LVDS Output Channel (2) DIFFOUT_B4n DIFFOUT_B4p DIFFOUT_B5n DIFFOUT_B5p DIFFOUT_B6n DIFFOUT_B6p DIFFOUT_B7n DIFFOUT_B7p DIFFOUT_B8n DIFFOUT_B8p DIFFOUT_B9n DIFFOUT_B9p DIFFOUT_B10n DIFFOUT_B10p DIFFOUT_B11n DIFFOUT_B11p DIFFOUT_B12n DIFFOUT_B12p DIFFOUT_B13n DIFFOUT_B13p DIFFOUT_B14n DIFFOUT_B14p DIFFOUT_B15n DIFFOUT_B15p DIFFOUT_B16n DIFFOUT_B16p DIFFOUT_B17n DIFFOUT_B17p DIFFOUT_B18n DIFFOUT_B18p DIFFOUT_B19n DIFFOUT_B19p DIFFOUT_B20n DIFFOUT_B20p DIFFOUT_B21n DIFFOUT_B21p DIFFOUT_B22n DIFFOUT_B22p DIFFOUT_B23n DIFFOUT_B23p DIFFOUT_B24n DIFFOUT_B24p DIFFOUT_B25n DIFFOUT_B25p DIFFOUT_B26n DIFFOUT_B26p DIFFOUT_B27n DIFFOUT_B27p DIFFOUT_B28n DIFFOUT_B28p Pin List F1517 AP33 AN33 AP32 AN32 AR33 AP34 AL29 AL28 AK30 AK29 AK28 AJ28 AT36 AR36 AR34 AT34 AU35 AT35 AW37 AV36 AV37 AU37 AW36 AW38 AU32 AT32 AR31 AT31 AU33 AT33 AK27 AJ27 AH27 AG27 AH26 AH25 AV34 AU34 AV33 AW33 AW35 AW34 AN28 AM28 AR27 AP27 AP29 AP28 AT28 AR28 DQ Group for DQS X4 Mode (2) DQSn2B DQS2B DQ2B DQ2B DQ2B DQ2B DQ3B DQ3B DQSn3B DQS3B DQ3B DQ3B DQSn4B DQS4B DQ4B DQ4B DQ4B DQ4B DQ5B DQ5B DQSn5B DQS5B DQ5B DQ5B DQSn6B DQS6B DQ6B DQ6B DQ6B DQ6B DQ7B DQ7B DQSn7B DQS7B DQ7B DQ7B DQSn8B DQS8B DQ8B DQ8B DQ8B DQ8B DQ9B DQ9B DQSn9B DQS9B DQ9B DQ9B DQSn10B DQS10B DQ Group for DQS X8/X9 Mode (2) DQSn1B/DQ1B DQS1B/CQ1B DQ1B DQ1B DQ1B DQ1B DQ2B DQ2B DQ2B DQ2B/CQn2B DQ2B DQ2B DQSn2B/DQ2B DQS2B/CQ2B DQ2B DQ2B DQ2B DQ2B DQ3B DQ3B DQ3B DQ3B/CQn3B DQ3B DQ3B DQSn3B/DQ3B DQS3B/CQ3B DQ3B DQ3B DQ3B DQ3B DQ4B DQ4B DQ4B DQ4B/CQn4B DQ4B DQ4B DQSn4B/DQ4B DQS4B/CQ4B DQ4B DQ4B DQ4B DQ4B DQ9B DQ9B DQ9B DQ9B/CQn9B DQ9B DQ9B DQSn9B/DQ9B DQS9B/CQ9B DQ Group for DQS X16/X18 Mode (2) DQ1B DQ1B/CQn1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQSn1B/DQ1B DQS1B/CQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ2B DQ2B DQ2B DQ2B DQ2B DQ2B DQ2B DQ2B/CQn2B DQ2B DQ2B DQ2B DQ2B DQ2B DQ2B DQSn2B/DQ2B DQS2B/CQ2B DQ2B DQ2B DQ2B DQ2B DQ2B DQ2B DQ2B DQ2B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B/CQn9B DQ Group for DQS X32/X36 Mode (2) DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B/CQn1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQSn1B/DQ1B DQS1B/CQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B Page 5 of 35 Pin Information for HardCopy® III HC335FF1517 Version 1.0 Bank Number 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C VREF Group VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 Pin Name /Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Optional Function(s) Configuration Function for Stratix III Dedicated Tx_Rx Only (1) Channel (2) DIFFIO_RX_B15n DIFFIO_RX_B15p DIFFIO_RX_B16n DIFFIO_RX_B16p DIFFIO_RX_B17n DIFFIO_RX_B17p DIFFIO_RX_B18n DIFFIO_RX_B18p DIFFIO_RX_B19n DIFFIO_RX_B19p DIFFIO_RX_B20n DIFFIO_RX_B20p DIFFIO_RX_B21n DIFFIO_RX_B21p DIFFIO_RX_B22n DIFFIO_RX_B22p DIFFIO_RX_B23n DIFFIO_RX_B23p DIFFIO_RX_B24n DIFFIO_RX_B24p DIFFIO_RX_B25n DIFFIO_RX_B25p DIFFIO_RX_B26n DIFFIO_RX_B26p Emulated LVDS Output Channel (2) DIFFOUT_B29n DIFFOUT_B29p DIFFOUT_B30n DIFFOUT_B30p DIFFOUT_B31n DIFFOUT_B31p DIFFOUT_B32n DIFFOUT_B32p DIFFOUT_B33n DIFFOUT_B33p DIFFOUT_B34n DIFFOUT_B34p DIFFOUT_B35n DIFFOUT_B35p DIFFOUT_B36n DIFFOUT_B36p DIFFOUT_B37n DIFFOUT_B37p DIFFOUT_B38n DIFFOUT_B38p DIFFOUT_B39n DIFFOUT_B39p DIFFOUT_B40n DIFFOUT_B40p DIFFOUT_B41n DIFFOUT_B41p DIFFOUT_B42n DIFFOUT_B42p DIFFOUT_B43n DIFFOUT_B43p DIFFOUT_B44n DIFFOUT_B44p DIFFOUT_B45n DIFFOUT_B45p DIFFOUT_B46n DIFFOUT_B46p DIFFOUT_B47n DIFFOUT_B47p DIFFOUT_B48n DIFFOUT_B48p DIFFOUT_B49n DIFFOUT_B49p DIFFOUT_B50n DIFFOUT_B50p DIFFOUT_B51n DIFFOUT_B51p DIFFOUT_B52n DIFFOUT_B52p DIFFOUT_B53n DIFFOUT_B53p Pin List F1517 AR30 AT30 AU29 AT29 AL26 AK26 AM27 AL27 AM25 AL25 AV31 AU30 AW32 AW31 AW30 AV30 AH24 AH23 AJ25 AJ24 AK24 AL24 AR25 AP25 AN26 AP26 AP24 AN25 AT26 AU26 AU27 AT27 AT25 AU25 AW29 AW28 AV27 AV28 AW27 AW26 AP22 AN23 AR24 AP23 AM22 AN22 AU24 AT23 AV25 AW25 DQ Group for DQS X4 Mode (2) DQ10B DQ10B DQ10B DQ10B DQ11B DQ11B DQSn11B DQS11B DQ11B DQ11B DQSn12B DQS12B DQ12B DQ12B DQ12B DQ12B DQ13B DQ13B DQSn13B DQS13B DQ13B DQ13B DQSn14B DQS14B DQ14B DQ14B DQ14B DQ14B DQ15B DQ15B DQSn15B DQS15B DQ15B DQ15B DQSn16B DQS16B DQ16B DQ16B DQ16B DQ16B DQ17B DQ17B DQSn17B DQS17B DQ17B DQ17B DQSn18B DQS18B DQ18B DQ18B DQ Group for DQS X8/X9 Mode (2) DQ9B DQ9B DQ9B DQ9B DQ10B DQ10B DQ10B DQ10B/CQn10B DQ10B DQ10B DQSn10B/DQ10B DQS10B/CQ10B DQ10B DQ10B DQ10B DQ10B DQ11B DQ11B DQ11B DQ11B/CQn11B DQ11B DQ11B DQSn11B/DQ11B DQS11B/CQ11B DQ11B DQ11B DQ11B DQ11B DQ12B DQ12B DQ12B DQ12B/CQn12B DQ12B DQ12B DQSn12B/DQ12B DQS12B/CQ12B DQ12B DQ12B DQ12B DQ12B DQ17B DQ17B DQ17B DQ17B/CQn17B DQ17B DQ17B DQSn17B/DQ17B DQS17B/CQ17B DQ17B DQ17B DQ Group for DQS X16/X18 Mode (2) DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQSn9B/DQ9B DQS9B/CQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ10B DQ10B DQ10B DQ10B DQ10B DQ10B DQ10B DQ10B/CQn10B DQ10B DQ10B DQ10B DQ10B DQ10B DQ10B DQSn10B/DQ10B DQS10B/CQ10B DQ10B DQ10B DQ10B DQ10B DQ10B DQ10B DQ10B DQ10B DQ Group for DQS X32/X36 Mode (2) DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B/CQn9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQSn9B/DQ9B DQS9B/CQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B DQ9B Page 6 of 35 Pin Information for HardCopy® III HC335FF1517 Version 1.0 Bank Number 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C VREF Group VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 Pin Name /Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Optional Function(s) Configuration Function for Stratix III Dedicated Tx_Rx Only (1) Channel (2) DIFFIO_RX_B27n DIFFIO_RX_B27p DIFFIO_RX_B28n DIFFIO_RX_B28p DIFFIO_RX_B29n DIFFIO_RX_B29p PLL_B1_CLKOUT4 PLL_B1_CLKOUT3 DIFFIO_RX_B30n DIFFIO_RX_B30p PLL_B1_CLKOUT0n PLL_B1_CLKOUT0p PLL_B1_FBn/CLKOUT2 PLL_B1_FBp/CLKOUT1 CLK5n CLK5p CLK4n CLK4p CLK6p CLK6n CLK7p CLK7n PLL_B2_FBp/CLKOUT1 PLL_B2_FBn/CLKOUT2 PLL_B2_CLKOUT0p PLL_B2_CLKOUT0n DIFFIO_RX_B31n DIFFIO_RX_B31p DIFFIO_RX_B32n DIFFIO_RX_B32p DIFFIO_RX_B33p DIFFIO_RX_B33n DIFFIO_RX_B34p DIFFIO_RX_B34n DIFFIO_RX_B35p DIFFIO_RX_B35n PLL_B2_CLKOUT3 PLL_B2_CLKOUT4 DIFFIO_RX_B36p DIFFIO_RX_B36n DIFFIO_RX_B37p DIFFIO_RX_B37n DIFFIO_RX_B38p DIFFIO_RX_B38n DIFFIO_RX_B39p DIFFIO_RX_B39n Emulated LVDS Output Channel (2) DIFFOUT_B54n DIFFOUT_B54p DIFFOUT_B55n DIFFOUT_B55p DIFFOUT_B56n DIFFOUT_B56p DIFFOUT_B57n DIFFOUT_B57p DIFFOUT_B58n DIFFOUT_B58p DIFFOUT_B59n DIFFOUT_B59p DIFFOUT_B60n DIFFOUT_B60p DIFFOUT_B61n DIFFOUT_B61p DIFFOUT_B62n DIFFOUT_B62p DIFFOUT_B63n DIFFOUT_B63p DIFFOUT_B64n DIFFOUT_B64p DIFFOUT_B65p DIFFOUT_B65n DIFFOUT_B66p DIFFOUT_B66n DIFFOUT_B67p DIFFOUT_B67n DIFFOUT_B68p DIFFOUT_B68n DIFFOUT_B69p DIFFOUT_B69n DIFFOUT_B70p DIFFOUT_B70n DIFFOUT_B71p DIFFOUT_B71n DIFFOUT_B72p DIFFOUT_B72n DIFFOUT_B73p DIFFOUT_B73n DIFFOUT_B74p DIFFOUT_B74n DIFFOUT_B75p DIFFOUT_B75n DIFFOUT_B76p DIFFOUT_B76n DIFFOUT_B77p DIFFOUT_B77n DIFFOUT_B78p DIFFOUT_B78n Pin List F1517 AW24 AV24 AU22 AW23 AU23 AT22 AV22 AW22 AR22 AR21 AK22 AJ22 AL23 AK23 AH22 AH21 AN21 AM21 AW21 AV21 AU21 AT21 AT20 AU20 AV19 AW19 AM19 AN19 AH19 AH20 AL18 AM18 AK18 AJ19 AP17 AR18 AP20 AR19 AT19 AU19 AP18 AP19 AT18 AU18 AT17 AU17 AR16 AT16 AW18 AV18 DQ Group for DQS X4 Mode (2) DQ18B DQ18B DQ19B DQ19B DQSn19B DQS19B DQ19B DQ19B DQ20B DQ20B DQS20B DQSn20B DQ20B DQ20B DQ21B DQ21B DQ21B DQ21B DQS21B DQSn21B DQ22B DQ22B DQ Group for DQS X8/X9 Mode (2) DQ17B DQ17B DQ Group for DQS X16/X18 Mode (2) DQ Group for DQS X32/X36 Mode (2) DQ22B DQ22B DQ22B DQ22B DQS22B/CQ22B DQSn22B/DQ22B DQ22B DQ22B Page 7 of 35 Pin Information for HardCopy® III HC335FF1517 Version 1.0 Bank Number 4C 4C 4C 4C 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B VREF Group VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 Pin Name /Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Optional Function(s) Configuration Function for Stratix III Dedicated Tx_Rx Only (1) Channel (2) DIFFIO_RX_B40p DIFFIO_RX_B40n DIFFIO_RX_B41p DIFFIO_RX_B41n DIFFIO_RX_B42p DIFFIO_RX_B42n DIFFIO_RX_B43p DIFFIO_RX_B43n DIFFIO_RX_B44p DIFFIO_RX_B44n DIFFIO_RX_B45p DIFFIO_RX_B45n DIFFIO_RX_B46p DIFFIO_RX_B46n DIFFIO_RX_B47p DIFFIO_RX_B47n DIFFIO_RX_B48p DIFFIO_RX_B48n DIFFIO_RX_B49p DIFFIO_RX_B49n DIFFIO_RX_B50p DIFFIO_RX_B50n DIFFIO_RX_B51p DIFFIO_RX_B51n DIFFIO_RX_B52p DIFFIO_RX_B52n Emulated LVDS Output Channel (2) DIFFOUT_B79p DIFFOUT_B79n DIFFOUT_B80p DIFFOUT_B80n DIFFOUT_B81p DIFFOUT_B81n DIFFOUT_B82p DIFFOUT_B82n DIFFOUT_B83p DIFFOUT_B83n DIFFOUT_B84p DIFFOUT_B84n DIFFOUT_B85p DIFFOUT_B85n DIFFOUT_B86p DIFFOUT_B86n DIFFOUT_B87p DIFFOUT_B87n DIFFOUT_B88p DIFFOUT_B88n DIFFOUT_B89p DIFFOUT_B89n DIFFOUT_B90p DIFFOUT_B90n DIFFOUT_B91p DIFFOUT_B91n DIFFOUT_B92p DIFFOUT_B92n DIFFOUT_B93p DIFFOUT_B93n DIFFOUT_B94p DIFFOUT_B94n DIFFOUT_B95p DIFFOUT_B95n DIFFOUT_B96p DIFFOUT_B96n DIFFOUT_B97p DIFFOUT_B97n DIFFOUT_B98p DIFFOUT_B98n DIFFOUT_B99p DIFFOUT_B99n DIFFOUT_B100p DIFFOUT_B100n DIFFOUT_B101p DIFFOUT_B101n DIFFOUT_B102p DIFFOUT_B102n DIFFOUT_B103p DIFFOUT_B103n Pin List F1517 AV16 AW17 AW15 AW16 AV15 AW14 AT15 AU15 AV13 AW13 AK17 AL17 AH17 AJ16 AH18 AJ18 AP16 AR15 AN14 AP14 AN15 AP15 AU14 AT14 AR12 AT12 AR13 AT13 AW11 AW12 AV12 AU12 AT11 AU11 AK15 AL16 AL15 AM15 AL14 AK14 AV10 AW10 AV9 AW9 AT10 AU9 AM13 AN13 AN12 AP12 DQ Group for DQS X4 Mode (2) DQS22B DQSn22B DQ22B DQ22B DQ23B DQ23B DQ23B DQ23B DQS23B DQSn23B DQ24B DQ24B DQS24B DQSn24B DQ24B DQ24B DQ25B DQ25B DQ25B DQ25B DQS25B DQSn25B DQ26B DQ26B DQS26B DQSn26B DQ26B DQ26B DQ27B DQ27B DQ27B DQ27B DQS27B DQSn27B DQ28B DQ28B DQS28B DQSn28B DQ28B DQ28B DQ29B DQ29B DQ29B DQ29B DQS29B DQSn29B DQ30B DQ30B DQS30B DQSn30B DQ Group for DQS X8/X9 Mode (2) DQ22B/CQn22B DQ22B DQ22B DQ22B DQ27B DQ27B DQ27B DQ27B DQS27B/CQ27B DQSn27B/DQ27B DQ27B DQ27B DQ27B/CQn27B DQ27B DQ27B DQ27B DQ28B DQ28B DQ28B DQ28B DQS28B/CQ28B DQSn28B/DQ28B DQ28B DQ28B DQ28B/CQn28B DQ28B DQ28B DQ28B DQ29B DQ29B DQ29B DQ29B DQS29B/CQ29B DQSn29B/DQ29B DQ29B DQ29B DQ29B/CQn29B DQ29B DQ29B DQ29B DQ30B DQ30B DQ30B DQ30B DQS30B/CQ30B DQSn30B/DQ30B DQ30B DQ30B DQ30B/CQn30B DQ30B DQ Group for DQS X16/X18 Mode (2) DQ Group for DQS X32/X36 Mode (2) DQ29B DQ29B DQ29B DQ29B DQ29B DQ29B DQ29B DQ29B DQS29B/CQ29B DQSn29B/DQ29B DQ29B DQ29B DQ29B DQ29B DQ29B DQ29B DQ29B/CQn29B DQ29B DQ29B DQ29B DQ29B DQ29B DQ29B DQ29B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQS30B/CQ30B DQSn30B/DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B/CQn30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQS30B/CQ30B DQSn30B/DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B/CQn30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B DQ30B Page 8 of 35 Pin Information for HardCopy® III HC335FF1517 Version 1.0 Bank Number 4B 4B 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A VREF Group VREFB4BN0 VREFB4BN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 Pin Name /Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Optional Function(s) Configuration Function for Stratix III Dedicated Tx_Rx Only (1) Channel (2) DIFFIO_RX_B53p DIFFIO_RX_B53n DIFFIO_RX_B54p DIFFIO_RX_B54n DIFFIO_RX_B55p DIFFIO_RX_B55n DIFFIO_RX_B56p DIFFIO_RX_B56n DIFFIO_RX_B57p DIFFIO_RX_B57n DIFFIO_RX_B58p DIFFIO_RX_B58n DIFFIO_RX_B59p DIFFIO_RX_B59n DIFFIO_RX_B60p DIFFIO_RX_B60n DIFFIO_RX_B61p DIFFIO_RX_B61n DIFFIO_RX_B62p DIFFIO_RX_B62n DIFFIO_RX_B63p DIFFIO_RX_B63n RUP4A RDN4A DIFFIO_RX_B64p DIFFIO_RX_B64n Emulated LVDS Output Channel (2) DIFFOUT_B104p DIFFOUT_B104n DIFFOUT_B105p DIFFOUT_B105n DIFFOUT_B106p DIFFOUT_B106n DIFFOUT_B107p DIFFOUT_B107n DIFFOUT_B108p DIFFOUT_B108n DIFFOUT_B109p DIFFOUT_B109n DIFFOUT_B110p DIFFOUT_B110n DIFFOUT_B111p DIFFOUT_B111n DIFFOUT_B112p DIFFOUT_B112n DIFFOUT_B113p DIFFOUT_B113n DIFFOUT_B114p DIFFOUT_B114n DIFFOUT_B115p DIFFOUT_B115n DIFFOUT_B116p DIFFOUT_B116n DIFFOUT_B117p DIFFOUT_B117n DIFFOUT_B118p DIFFOUT_B118n DIFFOUT_B119p DIFFOUT_B119n DIFFOUT_B120p DIFFOUT_B120n DIFFOUT_B121p DIFFOUT_B121n DIFFOUT_B122p DIFFOUT_B122n DIFFOUT_B123p DIFFOUT_B123n DIFFOUT_B124p DIFFOUT_B124n DIFFOUT_B125p DIFFOUT_B125n DIFFOUT_B126p DIFFOUT_B126n DIFFOUT_B127p DIFFOUT_B127n DIFFOUT_B128p DIFFOUT_B128n Pin List F1517 AP11 AR10 AR9 AT9 AN11 AP10 AT7 AT8 AG15 AH16 AG14 AH14 AH15 AJ15 AU8 AV7 AW8 AW7 AV6 AW6 AW4 AW5 AV3 AV4 AW2 AW3 AT6 AU6 AR6 AR7 AT5 AU5 AK13 AL13 AH13 AJ13 AJ12 AK12 AN9 AP9 AN7 AP7 AN8 AP8 AL9 AM9 AL10 AM10 AK11 AL11 DQ Group for DQS X4 Mode (2) DQ30B DQ30B DQ31B DQ31B DQ31B DQ31B DQS31B DQSn31B DQ32B DQ32B DQS32B DQSn32B DQ32B DQ32B DQ33B DQ33B DQ33B DQ33B DQS33B DQSn33B DQ34B DQ34B DQS34B DQSn34B DQ34B DQ34B DQ35B DQ35B DQ35B DQ35B DQS35B DQSn35B DQ36B DQ36B DQS36B DQSn36B DQ36B DQ36B DQ37B DQ37B DQ37B DQ37B DQS37B DQSn37B DQ38B DQ38B DQS38B DQSn38B DQ38B DQ38B DQ Group for DQS X8/X9 Mode (2) DQ30B DQ30B DQ35B DQ35B DQ35B DQ35B DQS35B/CQ35B DQSn35B/DQ35B DQ35B DQ35B DQ35B/CQn35B DQ35B DQ35B DQ35B DQ36B DQ36B DQ36B DQ36B DQS36B/CQ36B DQSn36B/DQ36B DQ36B DQ36B DQ36B/CQn36B DQ36B DQ36B DQ36B DQ37B DQ37B DQ37B DQ37B DQS37B/CQ37B DQSn37B/DQ37B DQ37B DQ37B DQ37B/CQn37B DQ37B DQ37B DQ37B DQ38B DQ38B DQ38B DQ38B DQS38B/CQ38B DQSn38B/DQ38B DQ38B DQ38B DQ38B/CQn38B DQ38B DQ38B DQ38B DQ Group for DQS X16/X18 Mode (2) DQ30B DQ30B DQ37B DQ37B DQ37B DQ37B DQ37B DQ37B DQ37B DQ37B DQS37B/CQ37B DQSn37B/DQ37B DQ37B DQ37B DQ37B DQ37B DQ37B DQ37B DQ37B/CQn37B DQ37B DQ37B DQ37B DQ37B DQ37B DQ37B DQ37B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQS38B/CQ38B DQSn38B/DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B/CQn38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ Group for DQS X32/X36 Mode (2) DQ30B DQ30B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQS38B/CQ38B DQSn38B/DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B/CQn38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B DQ38B Page 9 of 35 Pin Information for HardCopy® III HC335FF1517 Version 1.0 Bank Number VREF Group 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 Pin Name /Function nIO_PULLUP nCEO DCLK nCSO ASDO PLL_R4_CLKn PLL_R4_CLKp IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Optional Function(s) PLL_R4_CLKn PLL_R4_CLKp PLL_R4_CLKOUT0n PLL_R4_FB_CLKOUT0p RDN5A RUP5A Configuration Function for Stratix III Dedicated Tx_Rx Only (1) Channel (2) nIO_PULLUP nCEO DCLK nCSO ASDO DIFFIO_TX_R1n DIFFIO_TX_R1p DIFFIO_RX_R1n DIFFIO_RX_R1p DIFFIO_TX_R2n DIFFIO_TX_R2p DIFFIO_RX_R2n DIFFIO_RX_R2p DIFFIO_TX_R3n DIFFIO_TX_R3p DIFFIO_RX_R3n DIFFIO_RX_R3p DIFFIO_TX_R4n DIFFIO_TX_R4p DIFFIO_RX_R4n DIFFIO_RX_R4p DIFFIO_TX_R5n DIFFIO_TX_R5p DIFFIO_RX_R5n DIFFIO_RX_R5p DIFFIO_TX_R6n DIFFIO_TX_R6p DIFFIO_RX_R6n DIFFIO_RX_R6p DIFFIO_TX_R7n DIFFIO_TX_R7p DIFFIO_RX_R7n DIFFIO_RX_R7p DIFFIO_TX_R8n DIFFIO_TX_R8p DIFFIO_RX_R8n DIFFIO_RX_R8p DIFFIO_TX_R9n DIFFIO_TX_R9p DIFFIO_RX_R9n DIFFIO_RX_R9p DIFFIO_TX_R10n DIFFIO_TX_R10p DIFFIO_RX_R10n DIFFIO_RX_R10p DIFFIO_TX_R11n DIFFIO_TX_R11p DIFFIO_RX_R11n Emulated LVDS Output Channel (2) DIFFOUT_R1n DIFFOUT_R1p DIFFOUT_R2n DIFFOUT_R2p DIFFOUT_R3n DIFFOUT_R3p DIFFOUT_R4n DIFFOUT_R4p DIFFOUT_R5n DIFFOUT_R5p DIFFOUT_R6n DIFFOUT_R6p DIFFOUT_R7n DIFFOUT_R7p DIFFOUT_R8n DIFFOUT_R8p DIFFOUT_R9n DIFFOUT_R9p DIFFOUT_R10n DIFFOUT_R10p DIFFOUT_R11n DIFFOUT_R11p DIFFOUT_R12n DIFFOUT_R12p DIFFOUT_R13n DIFFOUT_R13p DIFFOUT_R14n DIFFOUT_R14p DIFFOUT_R15n DIFFOUT_R15p DIFFOUT_R16n DIFFOUT_R16p DIFFOUT_R17n DIFFOUT_R17p DIFFOUT_R18n DIFFOUT_R18p DIFFOUT_R19n DIFFOUT_R19p DIFFOUT_R20n DIFFOUT_R20p DIFFOUT_R21n DIFFOUT_R21p DIFFOUT_R22n Pin List DQ Group for F1517 DQS X4 Mode (2) AP6 AU3 AP5 AM7 AT4 AU1 AU2 AL7 AK8 AN5 AM6 AL5 DQ1R AL6 DQ1R AR3 DQSn1R AR4 DQS1R AK5 DQ1R AK6 DQ1R AT2 DQSn2R AT3 DQS2R AJ6 DQ2R AJ7 DQ2R AP4 DQ2R AN4 DQ2R AH6 DQ3R AH7 DQ3R AT1 DQSn3R AR1 DQS3R AH8 DQ3R AG9 DQ3R AP1 DQSn4R AP2 DQS4R AL3 DQ4R AL4 DQ4R AM3 DQ4R AM4 DQ4R AH11 DQ5R AH12 DQ5R AN2 DQSn5R AN3 DQS5R AG10 DQ5R AG11 DQ5R AN1 DQSn6R AM1 DQS6R AJ3 DQ6R AJ4 DQ6R AL1 DQ6R AL2 DQ6R AF12 DQ7R AG13 DQ7R AK2 DQSn7R DQ Group for DQS X8/X9 Mode (2) DQ1R DQ1R DQ1R DQ1R/CQn1R DQ1R DQ1R DQSn1R/DQ1R DQS1R/CQ1R DQ1R DQ1R DQ1R DQ1R DQ2R DQ2R DQ2R DQ2R/CQn2R DQ2R DQ2R DQSn2R/DQ2R DQS2R/CQ2R DQ2R DQ2R DQ2R DQ2R DQ3R DQ3R DQ3R DQ3R/CQn3R DQ3R DQ3R DQSn3R/DQ3R DQS3R/CQ3R DQ3R DQ3R DQ3R DQ3R DQ Group for DQS X16/X18 Mode (2) DQ Group for DQS X32/X36 Mode (2) DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R/CQn1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQSn1R/DQ1R DQS1R/CQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R Page 10 of 35 Pin Information for HardCopy® III HC335FF1517 Version 1.0 Bank Number 5A 5A 5A 5A 5A 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 6C 6C 6C VREF Group VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 Pin Name /Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO CLK8n CLK8p CLK10p CLK10n IO PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Optional Function(s) PLL_R3_CLKOUT0n PLL_R3_FB_CLKOUT0p CLK9n CLK9p CLK8n CLK8p CLK10p CLK10n CLK11p Configuration Function for Stratix III Dedicated Tx_Rx Only (1) Channel (2) DIFFIO_RX_R11p DIFFIO_TX_R12n DIFFIO_TX_R12p DIFFIO_RX_R12n DIFFIO_RX_R12p DIFFIO_TX_R13n DIFFIO_TX_R13p DIFFIO_RX_R13n DIFFIO_RX_R13p DIFFIO_TX_R14n DIFFIO_TX_R14p DIFFIO_RX_R14n DIFFIO_RX_R14p DIFFIO_TX_R15n DIFFIO_TX_R15p DIFFIO_RX_R15n DIFFIO_RX_R15p DIFFIO_TX_R16n DIFFIO_TX_R16p DIFFIO_RX_R16n DIFFIO_RX_R16p DIFFIO_TX_R17n DIFFIO_TX_R17p DIFFIO_RX_R17n DIFFIO_RX_R17p DIFFIO_TX_R18n DIFFIO_TX_R18p DIFFIO_RX_R18n DIFFIO_RX_R18p DIFFIO_TX_R19n DIFFIO_TX_R19p DIFFIO_RX_R19n DIFFIO_RX_R19p DIFFIO_TX_R20n DIFFIO_TX_R20p DIFFIO_RX_R20n DIFFIO_RX_R20p DIFFIO_TX_R21n DIFFIO_TX_R21p DIFFIO_RX_R21n DIFFIO_RX_R21p DIFFIO_TX_R22n DIFFIO_TX_R22p DIFFIO_RX_R22n DIFFIO_RX_R22p DIFFIO_RX_R23p Emulated LVDS Output Channel (2) DIFFOUT_R22p DIFFOUT_R23n DIFFOUT_R23p DIFFOUT_R24n DIFFOUT_R24p DIFFOUT_R25n DIFFOUT_R25p DIFFOUT_R26n DIFFOUT_R26p DIFFOUT_R27n DIFFOUT_R27p DIFFOUT_R28n DIFFOUT_R28p DIFFOUT_R29n DIFFOUT_R29p DIFFOUT_R30n DIFFOUT_R30p DIFFOUT_R31n DIFFOUT_R31p DIFFOUT_R32n DIFFOUT_R32p DIFFOUT_R33n DIFFOUT_R33p DIFFOUT_R34n DIFFOUT_R34p DIFFOUT_R35n DIFFOUT_R35p DIFFOUT_R36n DIFFOUT_R36p DIFFOUT_R37n DIFFOUT_R37p DIFFOUT_R38n DIFFOUT_R38p DIFFOUT_R39n DIFFOUT_R39p DIFFOUT_R40n DIFFOUT_R40p DIFFOUT_R41n DIFFOUT_R41p DIFFOUT_R42n DIFFOUT_R42p DIFFOUT_R43n DIFFOUT_R43p DIFFOUT_R44n DIFFOUT_R44p DIFFOUT_R45p Pin List DQ Group for F1517 DQS X4 Mode (2) AK3 DQS7R AE13 DQ7R AE14 DQ7R AK1 AJ1 AE4 DQ8R AE5 DQ8R AD4 DQSn8R AD5 DQS8R AD7 DQ8R AD8 DQ8R AF3 DQSn9R AF4 DQS9R AE6 DQ9R AD6 DQ9R AE2 DQ9R AE3 DQ9R AC9 DQ10R AC10 DQ10R AF1 DQSn10R AE1 DQS10R AB11 DQ10R AB12 DQ10R AD1 DQSn11R AD2 DQS11R AC6 DQ11R AC7 DQ11R AC3 DQ11R AC4 DQ11R AA11 DQ12R AA12 DQ12R AC1 DQSn12R AB1 DQS12R AB9 DQ12R AA10 DQ12R AB2 DQSn13R AB3 DQS13R AA7 DQ13R AB7 DQ13R AB4 DQ13R AB5 DQ13R AA5 AA6 AA3 AA4 AA1 AA2 W2 W1 Y4 DQ Group for DQS X8/X9 Mode (2) DQ8R DQ8R DQ8R DQ8R/CQn8R DQ8R DQ8R DQSn8R/DQ8R DQS8R/CQ8R DQ8R DQ8R DQ8R DQ8R DQ9R DQ9R DQ9R DQ9R/CQn9R DQ9R DQ9R DQSn9R/DQ9R DQS9R/CQ9R DQ9R DQ9R DQ9R DQ9R DQ10R DQ10R DQ10R DQ10R/CQn10R DQ10R DQ10R DQSn10R/DQ10R DQS10R/CQ10R DQ10R DQ10R DQ10R DQ10R DQ Group for DQS X16/X18 Mode (2) DQ Group for DQS X32/X36 Mode (2) DQ8R DQ8R DQ8R DQ8R DQ8R DQ8R DQ8R DQ8R/CQn8R DQ8R DQ8R DQ8R DQ8R DQ8R DQ8R DQSn8R/DQ8R DQS8R/CQ8R DQ8R DQ8R DQ8R DQ8R DQ8R DQ8R DQ8R DQ8R Page 11 of 35 Pin Information for HardCopy® III HC335FF1517 Version 1.0 Bank Number 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A VREF Group VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 Pin Name /Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Configuration Optional Function for Stratix III Function(s) Only (1) CLK11n PLL_R2_FB_CLKOUT0p PLL_R2_CLKOUT0n Dedicated Tx_Rx Channel (2) DIFFIO_RX_R23n DIFFIO_TX_R23p DIFFIO_TX_R23n DIFFIO_RX_R24p DIFFIO_RX_R24n DIFFIO_TX_R24p DIFFIO_TX_R24n DIFFIO_RX_R25p DIFFIO_RX_R25n DIFFIO_TX_R25p DIFFIO_TX_R25n DIFFIO_RX_R26p DIFFIO_RX_R26n DIFFIO_TX_R26p DIFFIO_TX_R26n DIFFIO_RX_R27p DIFFIO_RX_R27n DIFFIO_TX_R27p DIFFIO_TX_R27n DIFFIO_RX_R28p DIFFIO_RX_R28n DIFFIO_TX_R28p DIFFIO_TX_R28n DIFFIO_RX_R29p DIFFIO_RX_R29n DIFFIO_TX_R29p DIFFIO_TX_R29n DIFFIO_RX_R30p DIFFIO_RX_R30n DIFFIO_TX_R30p DIFFIO_TX_R30n DIFFIO_RX_R31p DIFFIO_RX_R31n DIFFIO_TX_R31p DIFFIO_TX_R31n DIFFIO_RX_R32p DIFFIO_RX_R32n DIFFIO_TX_R32p DIFFIO_TX_R32n DIFFIO_RX_R33p DIFFIO_RX_R33n DIFFIO_TX_R33p DIFFIO_TX_R33n DIFFIO_RX_R34p DIFFIO_RX_R34n DIFFIO_TX_R34p DIFFIO_TX_R34n DIFFIO_RX_R35p DIFFIO_RX_R35n DIFFIO_TX_R35p Emulated LVDS Output Channel (2) DIFFOUT_R45n DIFFOUT_R46p DIFFOUT_R46n DIFFOUT_R47p DIFFOUT_R47n DIFFOUT_R48p DIFFOUT_R48n DIFFOUT_R49p DIFFOUT_R49n DIFFOUT_R50p DIFFOUT_R50n DIFFOUT_R51p DIFFOUT_R51n DIFFOUT_R52p DIFFOUT_R52n DIFFOUT_R53p DIFFOUT_R53n DIFFOUT_R54p DIFFOUT_R54n DIFFOUT_R55p DIFFOUT_R55n DIFFOUT_R56p DIFFOUT_R56n DIFFOUT_R57p DIFFOUT_R57n DIFFOUT_R58p DIFFOUT_R58n DIFFOUT_R59p DIFFOUT_R59n DIFFOUT_R60p DIFFOUT_R60n DIFFOUT_R61p DIFFOUT_R61n DIFFOUT_R62p DIFFOUT_R62n DIFFOUT_R63p DIFFOUT_R63n DIFFOUT_R64p DIFFOUT_R64n DIFFOUT_R65p DIFFOUT_R65n DIFFOUT_R66p DIFFOUT_R66n DIFFOUT_R67p DIFFOUT_R67n DIFFOUT_R68p DIFFOUT_R68n DIFFOUT_R69p DIFFOUT_R69n DIFFOUT_R70p Pin List DQ Group for F1517 DQS X4 Mode (2) Y3 W6 W5 W4 DQ14R W3 DQ14R V6 DQ14R V5 DQ14R V2 DQS14R V1 DQSn14R V8 DQ15R W7 DQ15R V4 DQS15R V3 DQSn15R U7 DQ15R U6 DQ15R T1 DQ16R U1 DQ16R Y10 DQ16R Y9 DQ16R U4 DQS16R U3 DQSn16R W10 DQ17R V9 DQ17R P1 DQS17R R1 DQSn17R W12 DQ17R Y12 DQ17R R2 DQ18R T2 DQ18R V11 DQ18R W11 DQ18R R4 DQS18R R3 DQSn18R U10 DQ19R U9 DQ19R T5 DQS19R T4 DQSn19R T7 DQ19R T6 DQ19R K1 L1 R13 DQ20R R12 DQ20R L4 DQS20R L3 DQSn20R M5 DQ20R M4 DQ20R J2 DQ21R J1 DQ21R M7 DQ21R DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) DQ17R DQ17R DQ17R DQ17R DQS17R/CQ17R DQSn17R/DQ17R DQ17R DQ17R DQ17R/CQn17R DQ17R DQ17R DQ17R DQ18R DQ18R DQ18R DQ18R DQS18R/CQ18R DQSn18R/DQ18R DQ18R DQ18R DQ18R/CQn18R DQ18R DQ18R DQ18R DQ19R DQ19R DQ19R DQ19R DQS19R/CQ19R DQSn19R/DQ19R DQ19R DQ19R DQ19R/CQn19R DQ19R DQ19R DQ19R DQ19R DQ19R DQ19R DQ19R DQ19R DQ19R DQ19R DQ19R DQS19R/CQ19R DQSn19R/DQ19R DQ19R DQ19R DQ19R DQ19R DQ19R DQ19R DQ19R/CQn19R DQ19R DQ19R DQ19R DQ19R DQ19R DQ19R DQ19R DQ Group for DQS X32/X36 Mode (2) DQ24R DQ24R DQ24R Page 12 of 35 Pin Information for HardCopy® III HC335FF1517 Version 1.0 Bank Number 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A VREF Group VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 Pin Name /Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PLL_R1_CLKp PLL_R1_CLKn IO IO IO IO IO IO IO IO IO IO IO PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Configuration Function for Stratix III Dedicated Tx_Rx Only (1) Channel (2) DIFFIO_TX_R35n DIFFIO_RX_R36p DIFFIO_RX_R36n DIFFIO_TX_R36p DIFFIO_TX_R36n DIFFIO_RX_R37p DIFFIO_RX_R37n DIFFIO_TX_R37p DIFFIO_TX_R37n DIFFIO_RX_R38p DIFFIO_RX_R38n DIFFIO_TX_R38p DIFFIO_TX_R38n DIFFIO_RX_R39p DIFFIO_RX_R39n DIFFIO_TX_R39p DIFFIO_TX_R39n DIFFIO_RX_R40p DIFFIO_RX_R40n DIFFIO_TX_R40p DIFFIO_TX_R40n DIFFIO_RX_R41p DIFFIO_RX_R41n DIFFIO_TX_R41p DIFFIO_TX_R41n DIFFIO_RX_R42p DIFFIO_RX_R42n DIFFIO_TX_R42p DIFFIO_TX_R42n DIFFIO_RX_R43p DIFFIO_RX_R43n DIFFIO_TX_R43p DIFFIO_TX_R43n RUP6A DIFFIO_RX_R44p RDN6A DIFFIO_RX_R44n PLL_R1_FB_CLKOUT0p DIFFIO_TX_R44p PLL_R1_CLKOUT0n DIFFIO_TX_R44n PLL_R1_CLKp PLL_R1_CLKn Optional Function(s) RDN7A RUP7A DIFFIO_RX_T1n DIFFIO_RX_T1p DIFFIO_RX_T2n DIFFIO_RX_T2p DIFFIO_RX_T3n Emulated LVDS Output Channel (2) DIFFOUT_R70n DIFFOUT_R71p DIFFOUT_R71n DIFFOUT_R72p DIFFOUT_R72n DIFFOUT_R73p DIFFOUT_R73n DIFFOUT_R74p DIFFOUT_R74n DIFFOUT_R75p DIFFOUT_R75n DIFFOUT_R76p DIFFOUT_R76n DIFFOUT_R77p DIFFOUT_R77n DIFFOUT_R78p DIFFOUT_R78n DIFFOUT_R79p DIFFOUT_R79n DIFFOUT_R80p DIFFOUT_R80n DIFFOUT_R81p DIFFOUT_R81n DIFFOUT_R82p DIFFOUT_R82n DIFFOUT_R83p DIFFOUT_R83n DIFFOUT_R84p DIFFOUT_R84n DIFFOUT_R85p DIFFOUT_R85n DIFFOUT_R86p DIFFOUT_R86n DIFFOUT_R87p DIFFOUT_R87n DIFFOUT_R88p DIFFOUT_R88n DIFFOUT_T1n DIFFOUT_T1p DIFFOUT_T2n DIFFOUT_T2p DIFFOUT_T3n DIFFOUT_T3p DIFFOUT_T4n DIFFOUT_T4p DIFFOUT_T5n DIFFOUT_T5p DIFFOUT_T6n Pin List DQ Group for F1517 DQS X4 Mode (2) N6 DQ21R G1 DQS21R H1 DQSn21R N8 DQ22R N7 DQ22R J3 DQS22R K2 DQSn22R P10 DQ22R P9 DQ22R G2 DQ23R F2 DQ23R N11 DQ23R P12 DQ23R H4 DQS23R H3 DQSn23R N10 DQ24R N9 DQ24R J5 DQS24R J4 DQSn24R M9 DQ24R M8 DQ24R G4 DQ25R G3 DQ25R K5 DQ25R K4 DQ25R E1 DQS25R F1 DQSn25R K7 DQ26R K6 DQ26R D2 DQS26R D1 DQSn26R L7 DQ26R L6 DQ26R F4 E3 J7 J6 C2 C1 H9 DQ1T H10 DQ1T G10 DQSn1T G11 DQS1T J9 DQ1T G9 DQ1T F7 DQSn2T G7 DQS2T G8 DQ2T F8 DQ2T E7 DQ2T DQ Group for DQS X8/X9 Mode (2) DQ24R DQS24R/CQ24R DQSn24R/DQ24R DQ24R DQ24R DQ24R/CQn24R DQ24R DQ24R DQ24R DQ25R DQ25R DQ25R DQ25R DQS25R/CQ25R DQSn25R/DQ25R DQ25R DQ25R DQ25R/CQn25R DQ25R DQ25R DQ25R DQ26R DQ26R DQ26R DQ26R DQS26R/CQ26R DQSn26R/DQ26R DQ26R DQ26R DQ26R/CQn26R DQ26R DQ26R DQ26R DQ1T DQ1T DQ1T DQ1T/CQn1T DQ1T DQ1T DQSn1T/DQ1T DQS1T/CQ1T DQ1T DQ1T DQ1T DQ Group for DQS X16/X18 Mode (2) DQ Group for DQS X32/X36 Mode (2) DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQS26R/CQ26R DQSn26R/DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R/CQn26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T/CQn1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T Page 13 of 35 Pin Information for HardCopy® III HC335FF1517 Version 1.0 Bank Number 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B VREF Group VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 Pin Name /Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Optional Function(s) Configuration Function for Stratix III Dedicated Tx_Rx Only (1) Channel (2) DIFFIO_RX_T3p DIFFIO_RX_T4n DIFFIO_RX_T4p DIFFIO_RX_T5n DIFFIO_RX_T5p DIFFIO_RX_T6n DIFFIO_RX_T6p DIFFIO_RX_T7n DIFFIO_RX_T7p DIFFIO_RX_T8n DIFFIO_RX_T8p DIFFIO_RX_T9n DIFFIO_RX_T9p DIFFIO_RX_T10n DIFFIO_RX_T10p DIFFIO_RX_T11n DIFFIO_RX_T11p DIFFIO_RX_T12n DIFFIO_RX_T12p DIFFIO_RX_T13n DIFFIO_RX_T13p DIFFIO_RX_T14n DIFFIO_RX_T14p DIFFIO_RX_T15n DIFFIO_RX_T15p Emulated LVDS Output Channel (2) DIFFOUT_T6p DIFFOUT_T7n DIFFOUT_T7p DIFFOUT_T8n DIFFOUT_T8p DIFFOUT_T9n DIFFOUT_T9p DIFFOUT_T10n DIFFOUT_T10p DIFFOUT_T11n DIFFOUT_T11p DIFFOUT_T12n DIFFOUT_T12p DIFFOUT_T13n DIFFOUT_T13p DIFFOUT_T14n DIFFOUT_T14p DIFFOUT_T15n DIFFOUT_T15p DIFFOUT_T16n DIFFOUT_T16p DIFFOUT_T17n DIFFOUT_T17p DIFFOUT_T18n DIFFOUT_T18p DIFFOUT_T19n DIFFOUT_T19p DIFFOUT_T20n DIFFOUT_T20p DIFFOUT_T21n DIFFOUT_T21p DIFFOUT_T22n DIFFOUT_T22p DIFFOUT_T23n DIFFOUT_T23p DIFFOUT_T24n DIFFOUT_T24p DIFFOUT_T25n DIFFOUT_T25p DIFFOUT_T26n DIFFOUT_T26p DIFFOUT_T27n DIFFOUT_T27p DIFFOUT_T28n DIFFOUT_T28p DIFFOUT_T29n DIFFOUT_T29p DIFFOUT_T30n DIFFOUT_T30p DIFFOUT_T31n Pin List DQ Group for F1517 DQS X4 Mode (2) F6 DQ2T J12 DQ3T J11 DQ3T K10 DQSn3T K11 DQS3T L12 DQ3T K12 DQ3T D4 DQSn4T E4 DQS4T D6 DQ4T E6 DQ4T C5 DQ4T D5 DQ4T B4 DQ5T A3 DQ5T B3 DQSn5T C3 DQS5T A2 DQ5T A4 DQ5T C8 DQSn6T D8 DQS6T D9 DQ6T E9 DQ6T C7 DQ6T D7 DQ6T L13 DQ7T K13 DQ7T M14 DQSn7T M15 DQS7T N13 DQ7T M13 DQ7T B6 DQSn8T C6 DQS8T A7 DQ8T B7 DQ8T A5 DQ8T A6 DQ8T H12 DQ9T G12 DQ9T E13 DQSn9T F13 DQS9T F12 DQ9T F11 DQ9T D12 DQSn10T E12 DQS10T D10 DQ10T E10 DQ10T C11 DQ10T D11 DQ10T J13 DQ11T DQ Group for DQS X8/X9 Mode (2) DQ1T DQ2T DQ2T DQ2T DQ2T/CQn2T DQ2T DQ2T DQSn2T/DQ2T DQS2T/CQ2T DQ2T DQ2T DQ2T DQ2T DQ3T DQ3T DQ3T DQ3T/CQn3T DQ3T DQ3T DQSn3T/DQ3T DQS3T/CQ3T DQ3T DQ3T DQ3T DQ3T DQ4T DQ4T DQ4T DQ4T/CQn4T DQ4T DQ4T DQSn4T/DQ4T DQS4T/CQ4T DQ4T DQ4T DQ4T DQ4T DQ9T DQ9T DQ9T DQ9T/CQn9T DQ9T DQ9T DQSn9T/DQ9T DQS9T/CQ9T DQ9T DQ9T DQ9T DQ9T DQ10T DQ Group for DQS X16/X18 Mode (2) DQ1T DQ1T DQ1T DQSn1T/DQ1T DQS1T/CQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ2T DQ2T DQ2T DQ2T DQ2T DQ2T DQ2T DQ2T/CQn2T DQ2T DQ2T DQ2T DQ2T DQ2T DQ2T DQSn2T/DQ2T DQS2T/CQ2T DQ2T DQ2T DQ2T DQ2T DQ2T DQ2T DQ2T DQ2T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T/CQn9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ Group for DQS X32/X36 Mode (2) DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T/CQn1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQSn1T/DQ1T DQS1T/CQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T Page 14 of 35 Pin Information for HardCopy® III HC335FF1517 Version 1.0 Bank Number 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C VREF Group VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 Pin Name /Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Optional Function(s) Configuration Function for Stratix III Dedicated Tx_Rx Only (1) Channel (2) DIFFIO_RX_T16n DIFFIO_RX_T16p DIFFIO_RX_T17n DIFFIO_RX_T17p DIFFIO_RX_T18n DIFFIO_RX_T18p DIFFIO_RX_T19n DIFFIO_RX_T19p DIFFIO_RX_T20n DIFFIO_RX_T20p DIFFIO_RX_T21n DIFFIO_RX_T21p DIFFIO_RX_T22n DIFFIO_RX_T22p DIFFIO_RX_T23n DIFFIO_RX_T23p DIFFIO_RX_T24n DIFFIO_RX_T24p DIFFIO_RX_T25n DIFFIO_RX_T25p DIFFIO_RX_T26n DIFFIO_RX_T26p DIFFIO_RX_T27n DIFFIO_RX_T27p DIFFIO_RX_T28n Emulated LVDS Output Channel (2) DIFFOUT_T31p DIFFOUT_T32n DIFFOUT_T32p DIFFOUT_T33n DIFFOUT_T33p DIFFOUT_T34n DIFFOUT_T34p DIFFOUT_T35n DIFFOUT_T35p DIFFOUT_T36n DIFFOUT_T36p DIFFOUT_T37n DIFFOUT_T37p DIFFOUT_T38n DIFFOUT_T38p DIFFOUT_T39n DIFFOUT_T39p DIFFOUT_T40n DIFFOUT_T40p DIFFOUT_T41n DIFFOUT_T41p DIFFOUT_T42n DIFFOUT_T42p DIFFOUT_T43n DIFFOUT_T43p DIFFOUT_T44n DIFFOUT_T44p DIFFOUT_T45n DIFFOUT_T45p DIFFOUT_T46n DIFFOUT_T46p DIFFOUT_T47n DIFFOUT_T47p DIFFOUT_T48n DIFFOUT_T48p DIFFOUT_T49n DIFFOUT_T49p DIFFOUT_T50n DIFFOUT_T50p DIFFOUT_T51n DIFFOUT_T51p DIFFOUT_T52n DIFFOUT_T52p DIFFOUT_T53n DIFFOUT_T53p DIFFOUT_T54n DIFFOUT_T54p DIFFOUT_T55n DIFFOUT_T55p DIFFOUT_T56n Pin List DQ Group for F1517 DQS X4 Mode (2) H13 DQ11T J14 DQSn11T K14 DQS11T J15 DQ11T H15 DQ11T B9 DQSn12T C10 DQS12T A9 DQ12T A8 DQ12T A10 DQ12T B10 DQ12T L16 DQ13T L15 DQ13T M16 DQSn13T M17 DQS13T J16 DQ13T K16 DQ13T E15 DQSn14T F15 DQS14T F14 DQ14T G14 DQ14T F16 DQ14T G15 DQ14T D14 DQ15T C14 DQ15T C13 DQSn15T D13 DQS15T C15 DQ15T D15 DQ15T A11 DQSn16T A12 DQS16T B12 DQ16T B13 DQ16T A13 DQ16T A14 DQ16T G18 DQ17T F18 DQ17T E16 DQSn17T F17 DQS17T H18 DQ17T G17 DQ17T C16 DQSn18T D17 DQS18T A15 DQ18T B15 DQ18T A16 DQ18T B16 DQ18T A17 DQ19T C18 DQ19T C17 DQSn19T DQ Group for DQS X8/X9 Mode (2) DQ10T DQ10T DQ10T/CQn10T DQ10T DQ10T DQSn10T/DQ10T DQS10T/CQ10T DQ10T DQ10T DQ10T DQ10T DQ11T DQ11T DQ11T DQ11T/CQn11T DQ11T DQ11T DQSn11T/DQ11T DQS11T/CQ11T DQ11T DQ11T DQ11T DQ11T DQ12T DQ12T DQ12T DQ12T/CQn12T DQ12T DQ12T DQSn12T/DQ12T DQS12T/CQ12T DQ12T DQ12T DQ12T DQ12T DQ17T DQ17T DQ17T DQ17T/CQn17T DQ17T DQ17T DQSn17T/DQ17T DQS17T/CQ17T DQ17T DQ17T DQ17T DQ17T DQ Group for DQS X16/X18 Mode (2) DQ9T DQSn9T/DQ9T DQS9T/CQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ10T DQ10T DQ10T DQ10T DQ10T DQ10T DQ10T DQ10T/CQn10T DQ10T DQ10T DQ10T DQ10T DQ10T DQ10T DQSn10T/DQ10T DQS10T/CQ10T DQ10T DQ10T DQ10T DQ10T DQ10T DQ10T DQ10T DQ10T DQ Group for DQS X32/X36 Mode (2) DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T/CQn9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQSn9T/DQ9T DQS9T/CQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T DQ9T Page 15 of 35 Pin Information for HardCopy® III HC335FF1517 Version 1.0 Bank Number 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8B VREF Group VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8BN0 Pin Name /Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Optional Function(s) Configuration Function for Stratix III Dedicated Tx_Rx Only (1) Channel (2) DIFFIO_RX_T28p DIFFIO_RX_T29n DIFFIO_RX_T29p PLL_T2_CLKOUT4 PLL_T2_CLKOUT3 DIFFIO_RX_T30n DIFFIO_RX_T30p PLL_T2_CLKOUT0n PLL_T2_CLKOUT0p PLL_T2_FBn/CLKOUT2 PLL_T2_FBp/CLKOUT1 CLK13n CLK13p CLK12n CLK12p CLK14p CLK14n CLK15p CLK15n PLL_T1_FBp/CLKOUT1 PLL_T1_FBn/CLKOUT2 PLL_T1_CLKOUT0p PLL_T1_CLKOUT0n DIFFIO_RX_T31n DIFFIO_RX_T31p DIFFIO_RX_T32n DIFFIO_RX_T32p DIFFIO_RX_T33p DIFFIO_RX_T33n DIFFIO_RX_T34p DIFFIO_RX_T34n DIFFIO_RX_T35p DIFFIO_RX_T35n PLL_T1_CLKOUT3 PLL_T1_CLKOUT4 DIFFIO_RX_T36p DIFFIO_RX_T36n DIFFIO_RX_T37p DIFFIO_RX_T37n DIFFIO_RX_T38p DIFFIO_RX_T38n DIFFIO_RX_T39p DIFFIO_RX_T39n DIFFIO_RX_T40p DIFFIO_RX_T40n DIFFIO_RX_T41p Emulated LVDS Output Channel (2) DIFFOUT_T56p DIFFOUT_T57n DIFFOUT_T57p DIFFOUT_T58n DIFFOUT_T58p DIFFOUT_T59n DIFFOUT_T59p DIFFOUT_T60n DIFFOUT_T60p DIFFOUT_T61n DIFFOUT_T61p DIFFOUT_T62n DIFFOUT_T62p DIFFOUT_T63n DIFFOUT_T63p DIFFOUT_T64n DIFFOUT_T64p DIFFOUT_T65p DIFFOUT_T65n DIFFOUT_T66p DIFFOUT_T66n DIFFOUT_T67p DIFFOUT_T67n DIFFOUT_T68p DIFFOUT_T68n DIFFOUT_T69p DIFFOUT_T69n DIFFOUT_T70p DIFFOUT_T70n DIFFOUT_T71p DIFFOUT_T71n DIFFOUT_T72p DIFFOUT_T72n DIFFOUT_T73p DIFFOUT_T73n DIFFOUT_T74p DIFFOUT_T74n DIFFOUT_T75p DIFFOUT_T75n DIFFOUT_T76p DIFFOUT_T76n DIFFOUT_T77p DIFFOUT_T77n DIFFOUT_T78p DIFFOUT_T78n DIFFOUT_T79p DIFFOUT_T79n DIFFOUT_T80p DIFFOUT_T80n DIFFOUT_T81p Pin List DQ Group for F1517 DQS X4 Mode (2) D18 DQS19T A18 DQ19T B18 DQ19T E18 E19 M19 M18 J17 K17 K18 L18 G19 H19 A19 B19 C19 D19 D20 C20 B21 A21 H21 G21 M21 M20 J22 H22 L21 K22 F21 F20 E22 DQ20T E21 DQ20T D21 DQS20T C21 DQSn20T F22 DQ20T F23 DQ20T D22 DQ21T C22 DQ21T C23 DQ21T D23 DQ21T E24 DQS21T D24 DQSn21T B22 DQ22T A22 DQ22T B24 DQS22T A23 DQSn22T A24 DQ22T A25 DQ22T B25 DQ23T DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) DQ Group for DQS X32/X36 Mode (2) DQ22T DQ22T DQ22T DQ22T DQS22T/CQ22T DQSn22T/DQ22T DQ22T DQ22T DQ22T/CQn22T DQ22T DQ22T DQ22T DQ27T DQ29T DQ30T Page 16 of 35 Pin Information for HardCopy® III HC335FF1517 Version 1.0 Bank Number 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8A 8A 8A VREF Group VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 Pin Name /Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Optional Function(s) Configuration Function for Stratix III Dedicated Tx_Rx Only (1) Channel (2) DIFFIO_RX_T41n DIFFIO_RX_T42p DIFFIO_RX_T42n DIFFIO_RX_T43p DIFFIO_RX_T43n DIFFIO_RX_T44p DIFFIO_RX_T44n DIFFIO_RX_T45p DIFFIO_RX_T45n DIFFIO_RX_T46p DIFFIO_RX_T46n DIFFIO_RX_T47p DIFFIO_RX_T47n DIFFIO_RX_T48p DIFFIO_RX_T48n DIFFIO_RX_T49p DIFFIO_RX_T49n DIFFIO_RX_T50p DIFFIO_RX_T50n DIFFIO_RX_T51p DIFFIO_RX_T51n DIFFIO_RX_T52p DIFFIO_RX_T52n DIFFIO_RX_T53p DIFFIO_RX_T53n Emulated LVDS Output Channel (2) DIFFOUT_T81n DIFFOUT_T82p DIFFOUT_T82n DIFFOUT_T83p DIFFOUT_T83n DIFFOUT_T84p DIFFOUT_T84n DIFFOUT_T85p DIFFOUT_T85n DIFFOUT_T86p DIFFOUT_T86n DIFFOUT_T87p DIFFOUT_T87n DIFFOUT_T88p DIFFOUT_T88n DIFFOUT_T89p DIFFOUT_T89n DIFFOUT_T90p DIFFOUT_T90n DIFFOUT_T91p DIFFOUT_T91n DIFFOUT_T92p DIFFOUT_T92n DIFFOUT_T93p DIFFOUT_T93n DIFFOUT_T94p DIFFOUT_T94n DIFFOUT_T95p DIFFOUT_T95n DIFFOUT_T96p DIFFOUT_T96n DIFFOUT_T97p DIFFOUT_T97n DIFFOUT_T98p DIFFOUT_T98n DIFFOUT_T99p DIFFOUT_T99n DIFFOUT_T100p DIFFOUT_T100n DIFFOUT_T101p DIFFOUT_T101n DIFFOUT_T102p DIFFOUT_T102n DIFFOUT_T103p DIFFOUT_T103n DIFFOUT_T104p DIFFOUT_T104n DIFFOUT_T105p DIFFOUT_T105n DIFFOUT_T106p Pin List DQ Group for F1517 DQS X4 Mode (2) A26 DQ23T C25 DQ23T D25 DQ23T B27 DQS23T A27 DQSn23T J23 DQ24T K23 DQ24T M23 DQS24T L24 DQSn24T L22 DQ24T M22 DQ24T F24 DQ25T E25 DQ25T F26 DQ25T G26 DQ25T G25 DQS25T F25 DQSn25T D26 DQ26T C26 DQ26T E28 DQS26T D28 DQSn26T D27 DQ26T E27 DQ26T A29 DQ27T A28 DQ27T C28 DQ27T B28 DQ27T D29 DQS27T C29 DQSn27T J24 DQ28T K25 DQ28T J25 DQS28T H25 DQSn28T K26 DQ28T J26 DQ28T B30 DQ29T A30 DQ29T A31 DQ29T B31 DQ29T D30 DQS29T C31 DQSn29T G27 DQ30T H27 DQ30T G28 DQS30T F28 DQSn30T F29 DQ30T E30 DQ30T E31 DQ31T D31 DQ31T F30 DQ31T DQ Group for DQS X8/X9 Mode (2) DQ27T DQ27T DQ27T DQS27T/CQ27T DQSn27T/DQ27T DQ27T DQ27T DQ27T/CQn27T DQ27T DQ27T DQ27T DQ28T DQ28T DQ28T DQ28T DQS28T/CQ28T DQSn28T/DQ28T DQ28T DQ28T DQ28T/CQn28T DQ28T DQ28T DQ28T DQ29T DQ29T DQ29T DQ29T DQS29T/CQ29T DQSn29T/DQ29T DQ29T DQ29T DQ29T/CQn29T DQ29T DQ29T DQ29T DQ30T DQ30T DQ30T DQ30T DQS30T/CQ30T DQSn30T/DQ30T DQ30T DQ30T DQ30T/CQn30T DQ30T DQ30T DQ30T DQ35T DQ35T DQ35T DQ Group for DQS X16/X18 Mode (2) DQ29T DQ29T DQ29T DQ29T DQ29T DQ29T DQ29T DQS29T/CQ29T DQSn29T/DQ29T DQ29T DQ29T DQ29T DQ29T DQ29T DQ29T DQ29T/CQn29T DQ29T DQ29T DQ29T DQ29T DQ29T DQ29T DQ29T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQS30T/CQ30T DQSn30T/DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T/CQn30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ37T DQ37T DQ37T DQ Group for DQS X32/X36 Mode (2) DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQS30T/CQ30T DQSn30T/DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T/CQn30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ30T DQ38T DQ38T DQ38T Page 17 of 35 Pin Information for HardCopy® III HC335FF1517 Version 1.0 Bank Number 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A VREF Group VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 Pin Name /Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO GND GND GND GND GND PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Optional Function(s) Configuration Function for Stratix III Dedicated Tx_Rx Only (1) Channel (2) DIFFIO_RX_T54p DIFFIO_RX_T54n DIFFIO_RX_T55p DIFFIO_RX_T55n DIFFIO_RX_T56p DIFFIO_RX_T56n DIFFIO_RX_T57p DIFFIO_RX_T57n DIFFIO_RX_T58p DIFFIO_RX_T58n DIFFIO_RX_T59p DIFFIO_RX_T59n DIFFIO_RX_T60p DIFFIO_RX_T60n DIFFIO_RX_T61p DIFFIO_RX_T61n DIFFIO_RX_T62p DIFFIO_RX_T62n DIFFIO_RX_T63p DIFFIO_RX_T63n RUP8A RDN8A DIFFIO_RX_T64p DIFFIO_RX_T64n Emulated LVDS Output Channel (2) DIFFOUT_T106n DIFFOUT_T107p DIFFOUT_T107n DIFFOUT_T108p DIFFOUT_T108n DIFFOUT_T109p DIFFOUT_T109n DIFFOUT_T110p DIFFOUT_T110n DIFFOUT_T111p DIFFOUT_T111n DIFFOUT_T112p DIFFOUT_T112n DIFFOUT_T113p DIFFOUT_T113n DIFFOUT_T114p DIFFOUT_T114n DIFFOUT_T115p DIFFOUT_T115n DIFFOUT_T116p DIFFOUT_T116n DIFFOUT_T117p DIFFOUT_T117n DIFFOUT_T118p DIFFOUT_T118n DIFFOUT_T119p DIFFOUT_T119n DIFFOUT_T120p DIFFOUT_T120n DIFFOUT_T121p DIFFOUT_T121n DIFFOUT_T122p DIFFOUT_T122n DIFFOUT_T123p DIFFOUT_T123n DIFFOUT_T124p DIFFOUT_T124n DIFFOUT_T125p DIFFOUT_T125n DIFFOUT_T126p DIFFOUT_T126n DIFFOUT_T127p DIFFOUT_T127n DIFFOUT_T128p DIFFOUT_T128n Pin List DQ Group for F1517 DQS X4 Mode (2) G29 DQ31T D33 DQS31T D32 DQSn31T M24 DQ32T N25 DQ32T M25 DQS32T L25 DQSn32T M26 DQ32T N26 DQ32T C32 DQ33T B33 DQ33T A32 DQ33T A33 DQ33T B34 DQS33T A34 DQSn33T A35 DQ34T A36 DQ34T B37 DQS34T B36 DQSn34T A37 DQ34T A38 DQ34T D34 DQ35T C34 DQ35T E33 DQ35T E34 DQ35T D35 DQS35T C35 DQSn35T J27 DQ36T K27 DQ36T M27 DQS36T L27 DQSn36T K28 DQ36T L28 DQ36T G31 DQ37T F31 DQ37T F33 DQ37T G33 DQ37T G32 DQS37T F32 DQSn37T J30 DQ38T J31 DQ38T H30 DQS38T H31 DQSn38T J29 DQ38T K29 DQ38T T24 AN6 Y20 L32 AV2 DQ Group for DQS X8/X9 Mode (2) DQ35T DQS35T/CQ35T DQSn35T/DQ35T DQ35T DQ35T DQ35T/CQn35T DQ35T DQ35T DQ35T DQ36T DQ36T DQ36T DQ36T DQS36T/CQ36T DQSn36T/DQ36T DQ36T DQ36T DQ36T/CQn36T DQ36T DQ36T DQ36T DQ37T DQ37T DQ37T DQ37T DQS37T/CQ37T DQSn37T/DQ37T DQ37T DQ37T DQ37T/CQn37T DQ37T DQ37T DQ37T DQ38T DQ38T DQ38T DQ38T DQS38T/CQ38T DQSn38T/DQ38T DQ38T DQ38T DQ38T/CQn38T DQ38T DQ38T DQ38T DQ Group for DQS X16/X18 Mode (2) DQ37T DQ37T DQ37T DQ37T DQ37T DQS37T/CQ37T DQSn37T/DQ37T DQ37T DQ37T DQ37T DQ37T DQ37T DQ37T DQ37T/CQn37T DQ37T DQ37T DQ37T DQ37T DQ37T DQ37T DQ37T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQS38T/CQ38T DQSn38T/DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T/CQn38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ Group for DQS X32/X36 Mode (2) DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQS38T/CQ38T DQSn38T/DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T/CQn38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T DQ38T Page 18 of 35 Pin Information for HardCopy® III HC335FF1517 Version 1.0 Bank Number VREF Group Pin Name /Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Optional Function(s) Configuration Function for Stratix III Dedicated Tx_Rx Only (1) Channel (2) Emulated LVDS Output Channel (2) Pin List DQ Group for F1517 DQS X4 Mode (2) AV5 AV8 AV11 AV14 AV17 AV20 AV23 AV26 AV29 AV32 AV35 AV38 AR2 AR5 AR8 AR11 AR14 AR17 AR20 AR23 AR26 AR29 AR32 AR35 AR38 AM2 AM5 AM8 AM11 AM14 AM17 AM20 AM23 AM26 AM29 AM32 AM35 AM38 AJ2 AJ5 AJ8 AJ11 AJ14 AJ17 AJ20 AJ23 AJ26 AJ29 AJ32 AJ35 DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) DQ Group for DQS X32/X36 Mode (2) Page 19 of 35 Pin Information for HardCopy® III HC335FF1517 Version 1.0 Bank Number VREF Group Pin Name /Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Optional Function(s) Configuration Function for Stratix III Dedicated Tx_Rx Only (1) Channel (2) Emulated LVDS Output Channel (2) Pin List DQ Group for F1517 DQS X4 Mode (2) AJ38 AG17 AG19 AG21 AG23 AG25 AF2 AF5 AF8 AF11 AF14 AF16 AF18 AF20 AF22 AF24 AF26 AF29 AF32 AF35 AF38 AE15 AE17 AE19 AE21 AE23 AE25 AD14 AD16 AD18 AD20 AD22 AD24 AD26 AC2 AC5 AC8 AC11 AC13 AC15 AC17 AC19 AC21 AC23 AC25 AC29 AC32 AC35 AC38 AB14 DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) DQ Group for DQS X32/X36 Mode (2) Page 20 of 35 Pin Information for HardCopy® III HC335FF1517 Version 1.0 Bank Number VREF Group Pin Name /Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Optional Function(s) Configuration Function for Stratix III Dedicated Tx_Rx Only (1) Channel (2) Emulated LVDS Output Channel (2) Pin List DQ Group for F1517 DQS X4 Mode (2) AB16 AB18 AB20 AB22 AB24 AB26 AA13 AA15 AA17 AA19 AA21 AA23 AA25 AA27 Y2 Y5 Y8 Y11 Y14 Y16 Y18 Y22 Y24 Y26 Y29 Y32 Y35 Y38 W13 W15 W17 W21 W23 W25 W27 V14 V16 V18 V20 V22 V24 V26 U2 U5 U8 U11 U15 U17 U19 U21 DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) DQ Group for DQS X32/X36 Mode (2) Page 21 of 35 Pin Information for HardCopy® III HC335FF1517 Version 1.0 Bank Number VREF Group Pin Name /Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Optional Function(s) Configuration Function for Stratix III Dedicated Tx_Rx Only (1) Channel (2) Emulated LVDS Output Channel (2) Pin List DQ Group for F1517 DQS X4 Mode (2) U23 U25 U27 U29 U32 U35 U38 T14 T16 T18 T20 T22 T26 R15 R17 R19 R21 R23 R25 P2 P5 P8 P11 P14 P16 P18 P20 P22 P24 P26 P29 P32 P35 P38 N15 N17 N19 N21 N23 L2 L5 L8 L11 L14 L17 L20 L23 L26 L29 L35 DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) DQ Group for DQS X32/X36 Mode (2) Page 22 of 35 Pin Information for HardCopy® III HC335FF1517 Version 1.0 Bank Number VREF Group Pin Name /Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Optional Function(s) Configuration Function for Stratix III Dedicated Tx_Rx Only (1) Channel (2) Emulated LVDS Output Channel (2) Pin List DQ Group for F1517 DQS X4 Mode (2) L38 H2 H5 H8 H11 H14 H17 H20 H23 H26 H29 H32 H35 H38 E2 E5 E8 E11 E14 E17 E20 E23 E26 E29 E32 E35 E38 B2 B5 B8 B11 B14 B17 B20 B23 B26 B29 B32 B35 B38 Y19 P25 AF15 AE16 AE18 AE20 AE22 AE24 AD15 AD17 DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) DQ Group for DQS X32/X36 Mode (2) Page 23 of 35 Pin Information for HardCopy® III HC335FF1517 Version 1.0 Bank Number VREF Group Pin Name /Function VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Optional Function(s) Configuration Function for Stratix III Dedicated Tx_Rx Only (1) Channel (2) Emulated LVDS Output Channel (2) Pin List DQ Group for F1517 DQS X4 Mode (2) AD19 AD21 AD23 AD25 AC16 AC18 AC20 AC22 AC24 AB15 AB17 AB19 AB21 AB23 AB25 AA16 AA18 AA20 AA22 AA24 Y15 Y17 Y21 Y23 Y25 W16 W18 W20 W22 W24 V15 V17 V19 V21 V23 V25 U16 U18 U20 U22 U24 T15 T17 T19 T21 T23 T25 R16 R18 R20 DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) DQ Group for DQS X32/X36 Mode (2) Page 24 of 35 Pin Information for HardCopy® III HC335FF1517 Version 1.0 Bank Number VREF Group Pin Name /Function VCCL VCCL VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCPT VCCPT VCCPT VCCPT DNU VCCPGM VCCPGM TEMPDIODEn TEMPDIODEp VCC_CLKIN3C VCC_CLKIN4C VCC_CLKIN7C VCC_CLKIN8C VCCA_PLL_B1 VCCA_PLL_B2 VCCA_PLL_L1 VCCA_PLL_L2 VCCA_PLL_L3 VCCA_PLL_L4 VCCA_PLL_R1 VCCA_PLL_R2 VCCA_PLL_R3 VCCA_PLL_R4 VCCA_PLL_T1 VCCA_PLL_T2 VCCD_PLL_B1 VCCD_PLL_B2 VCCD_PLL_L1 PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Optional Function(s) Configuration Function for Stratix III Dedicated Tx_Rx Only (1) Channel (2) Emulated LVDS Output Channel (2) Pin List DQ Group for F1517 DQS X4 Mode (2) R22 R24 P21 AF17 AF19 AF21 AF23 AF25 AE26 AC14 AC26 AA14 AA26 W14 W26 U14 U26 R14 P15 P17 P19 P23 J32 AL32 AL8 J8 W19 AJ31 AJ10 G5 H6 AL21 AK20 J19 K20 AK21 AL19 L31 W32 AA32 AK32 K9 W8 AA8 AJ9 J21 K19 AJ21 AK19 M30 DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) DQ Group for DQS X32/X36 Mode (2) Page 25 of 35 Pin Information for HardCopy® III HC335FF1517 Version 1.0 Bank Number VREF Group Pin Name /Function VCCD_PLL_L2 VCCD_PLL_L3 VCCD_PLL_L4 VCCD_PLL_R1 VCCD_PLL_R2 VCCD_PLL_R3 VCCD_PLL_R4 VCCD_PLL_T1 VCCD_PLL_T2 VCCIO1A VCCIO1A VCCIO1A VCCIO1A VCCIO1A VCCIO1C VCCIO1C VCCIO1C VCCIO1C VCCIO2A VCCIO2A VCCIO2A VCCIO2A VCCIO2A VCCIO2C VCCIO2C VCCIO2C VCCIO2C VCCIO3A VCCIO3A VCCIO3A VCCIO3A VCCIO3A VCCIO3B VCCIO3B VCCIO3B VCCIO3B VCCIO3B VCCIO3C VCCIO3C VCCIO3C VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4B VCCIO4B VCCIO4B VCCIO4B VCCIO4B PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Optional Function(s) Configuration Function for Stratix III Dedicated Tx_Rx Only (1) Channel (2) Emulated LVDS Output Channel (2) Pin List DQ Group for F1517 DQS X4 Mode (2) W31 AA31 AK31 L9 W9 AA9 AH10 K21 L19 K33 M31 K36 F37 B39 R33 V30 V34 T37 AH34 AV39 AP37 AK37 AH30 AB33 AD37 AB30 Y39 AH28 AU36 AP31 AN34 AL30 AK25 AU28 AU31 AN24 AN27 AL22 AT24 AP21 AL12 AU4 AU7 AN10 AK10 AK16 AU10 AU13 AP13 AN16 DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) DQ Group for DQS X32/X36 Mode (2) Page 26 of 35 Pin Information for HardCopy® III HC335FF1517 Version 1.0 Bank Number VREF Group Pin Name /Function VCCIO4C VCCIO4C VCCIO4C VCCIO5A VCCIO5A VCCIO5A VCCIO5A VCCIO5A VCCIO5C VCCIO5C VCCIO5C VCCIO5C VCCIO6A VCCIO6A VCCIO6A VCCIO6A VCCIO6A VCCIO6C VCCIO6C VCCIO6C VCCIO6C VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7B VCCIO7B VCCIO7B VCCIO7B VCCIO7B VCCIO7C VCCIO7C VCCIO7C VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8B VCCIO8B VCCIO8B VCCIO8B VCCIO8B VCCIO8C VCCIO8C VCCIO8C VCCPD1A VCCPD1C VCCPD2A PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Optional Function(s) Configuration Function for Stratix III Dedicated Tx_Rx Only (1) Channel (2) Emulated LVDS Output Channel (2) Pin List DQ Group for F1517 DQS X4 Mode (2) AN18 AW20 AU16 AH9 AV1 AP3 AK4 AK7 AB10 AE7 AD3 AB6 M10 M6 K3 F3 B1 V10 Y1 V7 T3 J10 M12 G6 F9 C4 G16 K15 G13 C9 C12 D16 J18 F19 C36 K30 J28 G30 C33 F27 K24 G24 C27 C30 G22 C24 A20 P27 V27 AF27 DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) DQ Group for DQS X32/X36 Mode (2) Page 27 of 35 Pin Information for HardCopy® III HC335FF1517 Version 1.0 Bank Number VREF Group 1A 1C 2A 2C 3A 3B 3C 4A 4B 4C 5A 5C 6A 6C 7A 7B 7C 8A 8B 8C VREFB1AN0 VREFB1CN0 VREFB2AN0 VREFB2CN0 VREFB3AN0 VREFB3BN0 VREFB3CN0 VREFB4AN0 VREFB4BN0 VREFB4CN0 VREFB5AN0 VREFB5CN0 VREFB6AN0 VREFB6CN0 VREFB7AN0 VREFB7BN0 VREFB7CN0 VREFB8AN0 VREFB8BN0 VREFB8CN0 Pin Name /Function VCCPD2C VCCPD3A VCCPD3B VCCPD3C VCCPD4A VCCPD4B VCCPD4C VCCPD5A VCCPD5C VCCPD6A VCCPD6C VCCPD7A VCCPD7B VCCPD7C VCCPD8A VCCPD8B VCCPD8C VREFB1AN0 VREFB1CN0 VREFB2AN0 VREFB2CN0 VREFB3AN0 VREFB3BN0 VREFB3CN0 VREFB4AN0 VREFB4BN0 VREFB4CN0 VREFB5AN0 VREFB5CN0 VREFB6AN0 VREFB6CN0 VREFB7AN0 VREFB7BN0 VREFB7CN0 VREFB8AN0 VREFB8BN0 VREFB8CN0 NC NC NC NC NC (6) NC NC (6) NC (7) NC (6) NC (6) NC (4) NC (5) NC (5) PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Optional Function(s) Configuration Function for Stratix III Dedicated Tx_Rx Only (1) Channel (2) Emulated LVDS Output Channel (2) VREFB1AN0 VREFB1CN0 VREFB2AN0 VREFB2CN0 VREFB3AN0 VREFB3BN0 VREFB3CN0 VREFB4AN0 VREFB4BN0 VREFB4CN0 VREFB5AN0 VREFB5CN0 VREFB6AN0 VREFB6CN0 VREFB7AN0 VREFB7BN0 VREFB7CN0 VREFB8AN0 VREFB8BN0 VREFB8CN0 Pin List DQ Group for F1517 DQS X4 Mode (2) Y27 AG26 AG24 AG22 AG16 AG18 AG20 AF13 AB13 P13 Y13 N14 N16 N18 N24 N22 N20 K31 V32 AJ30 Y34 AP30 AM24 AN20 AM12 AM16 AN17 AK9 AB8 L10 Y6 F10 H16 G20 H28 H24 G23 H33 AM33 AG12 H7 AH1 AP35 AH2 AH3 AH4 AH5 K8 Y33 AL20 DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) DQ Group for DQS X32/X36 Mode (2) Page 28 of 35 Pin Information for HardCopy® III HC335FF1517 Version 1.0 Bank Number VREF Group Pin Name /Function NC (5) NC (5) NC (6) NC (6) NC (6) NC (6) NC (6) NC (6) NC (6) NC (6) NC (6) NC (6) NC (6) NC (6) NC (6) NC (7) NC (6) NC (6) NC (6) NC (6) NC (6) NC (6) NC (6) NC (6) NC (6) NC (6) NC (8) NC (6) NC (6) NC (6) NC (7) NC (6) NC (6) NC (6) NC (6) NC (7) NC (6) NC (6) NC (6) NC (6) NC (6) NC (6) NC (9) NC NC (6) NC (6) NC (6) NC (6) NC (8) NC (6) PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Optional Function(s) Configuration Function for Stratix III Dedicated Tx_Rx Only (1) Channel (2) Emulated LVDS Output Channel (2) Pin List DQ Group for F1517 DQS X4 Mode (2) Y7 J20 AH37 AH38 AH39 AG1 AG2 AG3 AG4 AG5 AG6 AG7 AG8 AG35 AG36 AG37 AG38 AG39 AF6 AF7 AF9 AF10 AF33 AF34 AF36 AF37 AE8 AE9 AE10 AE11 AE12 AE29 AE30 AE31 AE32 AE33 AE34 AE35 AD9 AD10 AD11 AD12 AD13 AD27 AD28 AD29 AD30 AD31 AD32 AC12 DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) DQ Group for DQS X32/X36 Mode (2) Page 29 of 35 Pin Information for HardCopy® III HC335FF1517 Version 1.0 Bank Number VREF Group Pin Name /Function NC (6) NC (6) NC (9) NC (6) NC (6) NC (9) NC (6) NC (6) NC (6) NC (8) NC (6) NC (6) NC (6) NC (6) NC NC (9) NC (6) NC (6) NC (6) NC (6) NC (6) NC (6) NC (7) NC (6) NC (6) NC (6) NC (6) NC (7) NC (6) NC (6) NC (6) NC (8) NC (6) NC (6) NC (6) NC (6) NC (6) NC (6) NC (6) NC (6) NC (6) NC (6) NC (7) NC (6) NC (6) NC NC NC (6) NC (6) NC (6) PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Optional Function(s) Configuration Function for Stratix III Dedicated Tx_Rx Only (1) Channel (2) Emulated LVDS Output Channel (2) Pin List DQ Group for F1517 DQS X4 Mode (2) AC27 AC28 AB27 AB28 V12 V13 U12 U13 U28 T8 T9 T10 T11 T12 T13 T27 T28 T29 T30 T31 R5 R6 R7 R8 R9 R10 R11 R28 R29 R30 R31 R32 P3 P4 P6 P7 P30 P31 P33 P34 N1 N2 N3 N4 N5 N12 N28 N32 N33 N34 DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) DQ Group for DQS X32/X36 Mode (2) Page 30 of 35 Pin Information for HardCopy® III HC335FF1517 Version 1.0 Bank Number VREF Group Pin Name /Function NC (6) NC (6) NC (6) NC (6) NC (6) NC (6) NC (6) NC (6) NC (6) NC (6) NC (7) NC (6) NC (6) NC NC (3) NC (3) NC (3) Optional Function(s) Configuration Function for Stratix III Dedicated Tx_Rx Only (1) Channel (2) Emulated LVDS Output Channel (2) MSEL2 MSEL1 MSEL0 DQ Group for F1517 DQS X4 Mode (2) N35 N36 N37 N38 N39 M1 M2 M3 M35 M36 M37 M38 M39 L30 D3 F5 M11 DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) DQ Group for DQS X32/X36 Mode (2) Notes on Pin Table: (1) These pins should be connected on the board to properly configure the FPGA prototype. See Stratix ® III device pin table for details. (2) The individual index number of the pin in this column may not be the same as its companion Stratix III device, but the functionality of the pin is fully migratable. (3) These NO CONNECT (NC) pins are MSEL configuration input pins in the Stratix III device and should be connected on the board to configure the FPGA prototype. (4) This NC pin is a VCCBAT pin in the Stratix III device and should be connected for the FPGA prototype. (5) This NC pin is a VCCPT pin in the Stratix III device and should be connected for the FPGA prototype. (6) This NC pin is an IO pin in the Stratix III device and can be left unconnected. (7) This NC pin is a VCCIO pin in the Stratix III device and should be connected to VCCIO power for the FPGA prototype. (8) This NC pin is a VREF pin in the Stratix III device and should be connected to the VREF input reference voltage for the FPGA prototype. (9) This NC pin is a VCCPD pin in the Stratix III device and should be connected to VCCPD power for the FPGA prototype. PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Pin List Page 31 of 35 Pin Information for HardCopy® III HC335FF1517 Version 1.0 Pin Name Pin Type (1st, 2nd, & 3rd Function) Pin Description Supply and Reference Pins VCCL supplies power to the core voltage power supply pins. VCC supplies power to the periphery circuitry. Reference pins for I/O banks. The RUP pins share the same VCCIO with the I/O bank where they are located. The external precision resistor RUP must be connected to the designated RUP pin within the bank. If not required, this pin is a regular I/O pin. VCCL VCC RUP[1..8]A Power Power I/O, Input RDN[1..8]A I/O, Input VCCIO[1..8][A,B,C] Power Reference pins for I/O banks. The RDN pins share the same GND with the I/O bank where they are located. The external precision resistor RDN must be connected to the designated RDN pin within the bank. If not required, this pin is a regular I/O pin. These are I/O supply voltage pins for banks 1 through 8. Each bank can support a different voltage level. VCCIO supplies power to the output buffers for all LVDS, LVCMOS(1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V), HSTL(12, 15, 18), SSTL(15, 18, 2), 3.0-V PCI/PCI-X I/O, and 3.0 V LVTTL I/O standards. VCCIO also supplies power to the input buffers used for LVCMOS(1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V), 3.0-V PCI/PCI-X and 3.0 V LVTTL I/O standards. VREF[1..8][A,B,C] Power Input reference voltage for each I/O bank. If a bank uses a voltage-referenced I/O standard, these pins are used as the voltage-referenced pins for the bank. VCCA_PLL[L[1:4],R[1:4],T[1:2],B[1:2]] Power Analog power for PLLs[L[1:4],R[1:4],T[1:2],B[1:2]]. You must power up these pins even if the PLL is not used. You are advised to keep this pin isolated from other VCC for better jitter performance. VCCD_PLL[L[1:4],R[1:4],T[1:2],B[1:2]] Power Digital power for PLLs[L[1:4],R[1:4],T[1:2],B[1:2]]. You must power up these pins even if the PLL is not used. VCCPT VCCPGM Power Power Power supply for the programmable power technology. Power supply for configuration pins. Can be connected to 1.8 V, 2.5 V or 3.0 V depending on the particular design. VCCPD[1..8][A,B,C] Power Dedicated power pins. This supply is used to power the I/O pre-drivers. This can be connected to 3.0 V or 2.5 V. VCCPD for 3.0-V I/O standard is 3.0 V, and VCCPD for 2.5-V/1.8-V/1.2-V I/O standards is 2.5 V. VCC_CLKIN[3,4,7,8] GND DNU NC Power Ground Do Not Use No Connect nIO_PULLUP Input Differential clock input power supply for top and bottom I/O banks. Device ground pins. Do not connect to power or ground or any other signal; must be left floating. Do not drive signals into these pins. Dedicated Configuration/JTAG Pins Dedicated input that chooses whether the internal pull-up resistors on the user I/O pins are on or off during power up. A logic high (0.9 V) turns off the weak pull-ups, while a logic low turns them on. Pin used in conjunction with the temperature-sensing diode (bias-high input) inside the HardCopy III device. TEMPDIODEp Input TEMPDIODEn Input Pin used in conjunction with the temperature-sensing diode (bias-low input) inside the HardCopy III device. nCE Input Dedicated active-low chip enable. When nCE is low, the device is enabled. When nCE is high, the device is disabled. nCONFIG Input Dedicated power up block control input. Pulling this pin low during user-mode will cause the HardCopy III to enter a reset state & tri-state all I/O pins. Returning this pin to a logic high level will initiate the power up and initialization sequence. It is not available as a user I/O pin. CONF_DONE Bidirectional (open-drain) Output Bidirectional (open-drain) This is a dedicated power up block status pin. As a status output, the CONF_DONE pin drives low before and during initialization. Driven this pin high indicates that the device is entering user mode. Output that drives low when device initialization is complete. This is a dedicated power up block status pin. The HardCopy III drives nSTATUS low indicates that the device is being initialized. As a status output, the nSTATUS is pulled low if an error occurs during initialization. As a status input, this pin delays the completion of the Initialization phase when nSTATUS is driven low by an external source during initialization. It is not available as a user I/O pin. PORSEL Input TCK TMS TDI TDO TRST Input Input Input Output Input Dedicated input which selects between a POR time of 12 ms or 100 ms. A logic high (1.5 V, 1.8 V, 2.5 V,3.0 V) selects a POR time of 12 ms and a logic low selects POR time of 100 ms. Dedicated JTAG input pin. Connect TCK to GND if the JTAG circuitry is not used. Dedicated JTAG input pin. Connect TMS to VCCPD if the JTAG circuitry is not used. Dedicated JTAG input pin. Connect TDI to VCCPD if the JTAG circuitry is not used. Dedicated JTAG output pin. Dedicated active-low JTAG input pin. TRST is used to asynchronously reset the JTAG boundary-scan circuit. nCEO nSTATUS PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Pin Definitions Page 32 of 35 Pin Information for HardCopy® III HC335FF1517 Version 1.0 Pin Name Pin Type (1st, 2nd, & 3rd Function) CLK[1,3,8,10]p CLK[1,3,8,10]n CLK[0,2,4,5,6,7,9,11..15]p Clock, Input Clock, Input I/O, Clock CLK[0,2,4,5,6,7,9,11..15]n PLL_[L1,L4,R1,R4]_CLKp PLL_[L1,L4,R1,R4]_CLKn PLL_[L2,L3,R2,R3]_CLKOUT0n I/O, Clock Clock, Input Clock, Input I/O, Clock PLL_[L2,L3,R2,R3]_FB_CLKOUT0p PLL_[T1,T2,B1,B2]_FBp/CLKOUT1 PLL_[T1,T2,B1,B2]_FBn/CLKOUT2 PLL_[T1,T2,B1,B2]_CLKOUT[3,4] PLL_[T1,T2,B1,B2]_CLKOUT0[p,n] I/O, Clock I/O, Clock I/O, Clock I/O, Clock I/O, Clock Pin Description Clock and PLL Pins Dedicated high speed clock input pins 1, 3, 8, and 10 that can also be used for data inputs. OCT Rd is not supported on these pins. Dedicated negative clock input pins for differential clock input that can also be used for data inputs. OCT Rd is not supported on these pins. These pins can be used as I/O pins or clock input pins. OCT Rd is supported on these pins. These pins can be used as I/O pins or negative clock input pins for differential clock inputs. OCT Rd is supported on these pins. Dedicated clock input pins to PLL L1, L4, R1, and R4 respectively. Dedicated negative clock input pins for dfferential clock input to PLL L1, L4, R1, and R4 respectively. Each left and right PLL supports 2 clock I/O pins, configured either as 2 single-ended I/O or one differential I/O pair. When using both pins as single-ended I/Os, PLL_#_CLKOUT0n can be the clock output while the PLL_#_FB_CLKOUT0p is the external feedback input pin. Dual-purpose I/O pins that can be used as two single-ended outputs or one differential external feedback input pin. These pins can be used as I/O pins or two single-ended clock ouput pins. I/O pins that be used as two single-ended clock output pins or one differential clock output pair. Optional/Dual-Purpose Configuration Pins Dedicated control signal from Stratix III devices, but kept in HardCopy III for compatibility reasons. Dedicated control signal from Stratix III devices, but kept in HardCopy III for compatibility reasons. Dedicated configuration clock pin on Stratix III devices, but kept in HardCopy III for compatibility reasons. It's not required to clock this pin for HardCopy III. nCSO ASDO DCLK I/O Output I/O Output Input (PS, FPP) Output (AS) DIFFIO_RX[##]p/n I/O, RX channel DIFFIO_TX[##]p/n I/O, TX channel These are true LVDS transmitter channels on side I/O banks. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. DIFFOUT_[##]p/n I/O, TX channel These are emulated LVDS output channels. On column I/O banks, there are true LVDS input buffers but no true LVDS output buffers. However, all column user I/Os, including I/Os with true LVDS input buffers, can be configured as emulated LVDS output buffers.Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. DQS[1..44][T,B], DQS[1..40][L,R] I/O,DQS Differential I/O Pins These are true LVDS receiver channels on side and column I/O banks. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. External Memory Interface Pins Optional data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase-shift circuitry. The shifted DQS signal can also drive to internal logic. Optional complementary data strobe signal for use in QDRII SRAM. These pins drive to dedicated DQS phase-shift circuitry. DQSn[1..44][T,B], DQSn[1..40][L,R] I/O,DQSn DQ[1..44][T,B],DQ[1..40][L,R] I/O,DQ Optional data signal for use in external memory interfacing. The order of the DQ bits within a designated DQ bus is not important; however, use caution when making pin assignments if you plan on migrating to a different memory interface that has a different DQ bus width. Analyze the available DQ pins across all pertinent DQS columns in the pin list. CQ[1..44][T,B], CQ[1..40][L,R] DQS Optional data strobe signal for use in QDRII SRAM. These are the pins for echo clocks. CQn[1..44][T,B], CQ[1..40][L,R] DQS Optional complementary data strobe signal for use in QDRII SRAM. These are the pins for echo clocks. Notes: (1) These pin definitions are prepared based on the device with the largest density, HC335. Refer to the pin list for the availability of pins in each density. PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Pin Definitions Page 33 of 35 Pin Information for HardCopy® III HC335FF1517 Version 1.0 PLL_T2 7C VREFB7CN0 7B VREFB7BN0 7A VREFB7AN0 PLL_R1 VREFB6CN0 VREFB6AN0 PLL_T1 6A 8C VREFB8CN0 6C 8B VREFB8BN0 1A 8A VREFB8AN0 1C VREFB1CN0 VREFB1AN0 PLL_L1 PLL_R3 5C 5A 2A PLL_L4 3A VREFB3AN0 3B VREFB3BN0 3C VREFB3CN0 PLL_B1 PLL_B2 4C VREFB4CN0 4B VREFB4BN0 4A VREFB4AN0 VREFB5AN0 VREFB5CN0 PLL_L3 2C PLL_R2 VREFB2AN0 VREFB2CN0 PLL_L2 PLL_R4 Notes: 1. This is a top view of the silicon die. For flip chip packages, the die is mounted upside down in the package; therefore, to obtain the top package view, flip this diagram on its vertical axis. 2. This is a pictorial representation only to get an idea of placement on the device. Refer to the pin list and the Quartus® II software for exact locations. PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Bank & PLL Diagram Page 34 of 35 Pin Information for HardCopy® III HC335FF1517 Version 1.0 Version Number 1.0 Date 7/24/2009 PT-HC335FF1517-1.0 Copyright © 2009 Altera Corp. Changes Made Initial release. Revision History Page 35 of 35