PRELIMINARY ICS853017 QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL RECEIVER GENERAL DESCRIPTION FEATURES The ICS853017 is a quad 1-to-1, 2.5V/3.3V/5V difICS ferential LVPECL/ECL receiver and a member of the HiPerClockS™ HiperclocksTM family of High Performance Clock Solutions from IDT. The ICS853017 operates with a positive or negative power supply at 2.5V, 3.3V or 5V, and can accept both single-ended and differential inputs. For singleended operation, an internally generated voltage, which is available on output pin VBB, can be used as a switching bias voltage on the unused input of the differential pair. VBB can also be used to rebias AC coupled inputs. • Four differential LVPECL / ECL 1:1 receivers • Four differential LVPECL clock input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Output frequency: >2GHz (typical) • Translates any single ended input signal to LVPECL levels with resistor bias on nPCLKx input • Output skew: TBD • Part-to-part skew: TBD • Propagation delay: 320ps (typical) • LVPECL mode operating voltage supply range: VCC = 2.375V to 5.25V • ECL mode operating voltage supply range: VCC = 0V, VEE = -5.25V to -2.375V • -40°C to 85°C ambient operating temperature • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages BLOCK DIAGRAM PIN ASSIGNMENT D0 nD0 Q0 nQ0 D1 nD1 Q1 nQ1 D2 nD2 Q2 nQ2 D3 nD3 Q3 nQ3 VCC D0 nD0 D1 nD1 D2 nD2 D3 nD3 VBB 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 VEE ICS853017 20-Lead, 300-MIL SOIC 7.5mm x 12.8mm x 2.3mm body package M Package Top View VBB The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. IDT ™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL RECEIVER 1 ICS853017AM REV. B OCTOBER 24, 2007 ICS853017 QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL RECEIVER PRELIMINARY TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 20 VCC Power 2 D0 Input 3 nD0 Input 4 D1 Input 5 nD1 Input 6 D2 Input 7 nD2 Input 8 D3 Input 9 nD3 Input 10 VBB Power Bias Voltage. 11 VEE Power Negative supply pin. 12, 13 nQ3, Q3 Output Differential output pair. LVPECL interface levels. 14, 15 nQ2, Q2 Output Differential output pair. LVPECL interface levels. 17, 18 nQ1, Q1 Output Differential output pair. LVPECL interface levels. 19, 20 nQ0, Q0 Output Differential output pair. LVPECL interface levels. Core supply pins. Pulldown Pullup/ Pulldown Pulldown Pullup/ Pulldown Pulldown Pullup/ Pulldown Pulldown Pullup/ Pulldown Non-inver ting differential clock input. Inver ting differential clock input. VCC/2 default when left floating. Non-inver ting differential clock input. Inver ting differential clock input. VCC/2 default when left floating. Non-inver ting differential clock input. Inver ting differential clock input. VCC/2 default when left floating. Non-inver ting differential clock input. Inver ting differential clock input. VCC/2 default when left floating. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter RPULLDOWN Input Pulldown Resistor Test Conditions Minimum Typical 75 Maximum Units kΩ RVCC/2 Pullup/Pulldown Resistors 50 kΩ TABLE 3. CLOCK INPUT FUNCTION TABLE Inputs Outputs Input to Output Mode Polarity HIGH Differential to Differential Non Inver ting HIGH LOW Differential to Differential Non Inver ting D0:D3 nD0:nD3 Q0:Q3 nQ0:nQ3, 0 1 LOW 1 0 0 Biased; NOTE 1 LOW HIGH Single Ended to Differential Non Inver ting 1 Biased; NOTE 1 HIG H LOW Single Ended to Differential Non Inver ting Biased; NOTE 1 0 HIGH LOW Single Ended to Differential Inver ting Biased; NOTE 1 1 LOW HIGH Single Ended to Differential Inver ting NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels". IDT ™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL RECEIVER 2 ICS853017AM REV. B OCTOBER 24, 2007 ICS853017 QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL RECEIVER PRELIMINARY ABSOLUTE MAXIMUM RATINGS Inputs, VI (LVPECL mode) 5.5V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These -5.5V (ECL mode, VCC = 0) ratings are stress specifications only. Functional operation of -0.5V to VCC + 0.5V Inputs, VI (ECL mode) 0.5V to VEE - 0.5V Supply Voltage, VCC Negative Supply Voltage, VEE Outputs, IO Continuous Current Surge Current VBB Sing/Source, IBB product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. 50mA 100mA Exposure to absolute maximum rating conditions for extended periods may affect product reliability. ± 0.5mA Operating Temperature Range, TA -40°C to +85°C Storage Temperature, TSTG -65°C to 150°C Package Thermal Impedance, θJA 46.2°C/W (0 lfpm) (Junction-to-Ambient) TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 5.25V; VEE = 0V Symbol Parameter VCC Core Supply Voltage IEE Power Supply Current Test Conditions Minimum Typical Maximum 2.375 3. 3 5.25 Units V 46 mA TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V Symbol Parameter VOH Output High Voltage; NOTE 1 Min -40°C Typ Max Min 2.275 25°C Typ Max Min 2.295 Max 2.33 V VOL Output Low Voltage; NOTE 1 Input High Voltage, Single-Ended 2.075 2.075 2.075 V VIL Input Low Voltage, Single-Ended 1.43 1.43 1.43 V V BB Output Voltage Reference; NOTE 2 1.86 V PP Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input D0, D1, D2, D3 High Current nD0, nD1, nD2, nD3 D0, D1, D2, D3 Input Low Current nD0, nD1, nD2, nD3 IIH IIL 1.52 Units VIH VCMR 1.545 85°C Typ 1.535 1.86 800 1.86 800 1.2 3.3 1.2 3.3 -10 3 1.2 200 -150 -150 Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50Ω to VCC - 2V. NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for Dx, nDx is VCC + 0.3V. IDT ™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL RECEIVER V 800 200 -1 0 V mV 3.3 V 200 µA -10 µA -150 µA ICS853017AM REV. B OCTOBER 24, 2007 ICS853017 QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL RECEIVER PRELIMINARY TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V Symbol Parameter -40°C Min 25°C Typ Max Min 85°C Typ Max Min Typ Max Units VOH Output High Voltage; NOTE 1 1.475 1.495 1.53 V VOL Output Low Voltage; NOTE 1 0.745 0.72 0.735 V VIH Input High Voltage, Single-Ended 1.275 VIL Input Low Voltage, Single-Ended 0.63 VPP IIH Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 Input D0, D1, D2, D3 High Current nD0, nD1, nD2, nD3 IIL Input Low Current VCMR D0, D1, D2, D3 1.275 1.275 0.63 800 0.63 800 1.2 2.5 V 800 1.2 2.5 200 -10 V 1.2 200 -10 nD0, nD1, nD2, nD3 -150 -150 Input and output parameters var y 1:1 with VCC. VEE can var y +0.925V to -0.5V. NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for Dx, nDx is VCC + 0.3V. mV 2.5 V 200 µA -10 µA -150 µA TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 5V; VEE = 0V -40°C 25°C 85°C Symbol Parameter VOH Output High Voltage; NOTE 1 3.975 3.995 4.03 V VOL Output Low Voltage; NOTE 1 3.245 3.22 3.235 V VIH Input High Voltage, Single-Ended 3.775 3.775 3.775 V VIL Input Low Voltage, Single-Ended 3.13 3.13 3.13 V VPP IIH Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 Input D0, D1, D2, D3 High Current nD0, nD1, nD2, nD3 IIL Input Low Current VCMR Min D0, D1, D2, D3 Typ Max Min 80 0 Typ Max 800 1.2 5 1.2 5 200 -10 1.2 200 -10 4 Typ Max 800 nD0, nD1, nD2, nD3 -200 -200 Input and output parameters var y 1:1 with VCC. VEE can var y +0.925V to -0.5V. NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for Dx, nDx is VCC + 0.3V. IDT ™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL RECEIVER Min Units mV 5 V 200 µA -10 µA -200 µA ICS853017AM REV. B OCTOBER 24, 2007 ICS853017 QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL RECEIVER PRELIMINARY TABLE 4C. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V -40°C 25°C 85°C Symbol Parameter VOH Output High Voltage; NOTE 1 -1.025 -1.005 -0.97 V VOL -1.755 -1.78 -1.765 V IIH Output Low Voltage; NOTE 1 Input High Voltage, Single-Ended Input Low Voltage, Single-Ended Output Voltage Reference; NOTE 2 Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input D0:D3, nD0:nD3 High Current IIL Input Low Current VIH VIL VBB VPP VCMR Min Typ Max Min Typ Max V -1.87 -1.87 -1.87 V -1.44 -1.44 -1.44 V 800 800 VEE+1.2V 0 800 VEE+1.2V 0 20 0 200 t sk(o) t sk(pp) Par t-to-Par t Skew; NOTE 3, 4 tR/tF Output Rise/Fall Time t p LH t p HL OR 20% to 80% 0 V 200 µA -10 µA -200 µA 25°C Typ mV VCC = 2.375V TO 5.25V; VEE = 0V -40°C Min VEE+1.2V -10 TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V Output Frequency Propagation Delay, Low-to-High; NOTE 1 Propagation Delay, High-to-Low; NOTE 1 Output Skew; NOTE 2, 4 Units -1.225 nD0:nD3 -200 -200 Input and output parameters var y 1:1 with VCC. VEE can var y +0.925V to -0.5V. NOTE 1: Outputs terminated with 50Ω to VCC - 2V. NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for Dx, nDx is VCC + 0.3V. fMAX Max -1.225 -10 Parameter Typ -1.225 D0:D3 Symbol Min Max Min Typ 85°C Max Min Typ Max Units >2 >2 >2 GHz 320 320 320 ps 320 320 320 ps TBD TBD TB D ps TBD TBD TBD ps 175 175 175 ps All parameters tested ≤ 1GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. IDT ™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL RECEIVER 5 ICS853017AM REV. B OCTOBER 24, 2007 ICS853017 QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL RECEIVER PRELIMINARY PARAMETER MEASUREMENT INFORMATION 2V VCC Qx SCOPE VCC nD0:nD3 LVPECL V nQx V Cross Points PP CMR D0:D3 VEE VEE -3.5V to -0.375V DIFFERENTIAL INPUT LEVEL OUTPUT LOAD AC TEST CIRCUIT nQx PART 1 Qx nQx nQy nQy Qx PART 2 Qy Qy tsk(pp) tsk(o) PART-TO-PART SKEW OUTPUT SKEW nD0:nD3 nD0:D3 80% 80% VSW I N G Clock Outputs nQ0:nQ3 20% 20% tR tF Q0:Q3 tp LH OUTPUT RISE/FALL TIME IDT ™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL RECEIVER tp HL PROPAGATION DELAY 6 ICS853017AM REV. B OCTOBER 24, 2007 ICS853017 QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL RECEIVER PRELIMINARY APPLICATION INFORMATION RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: DX INPUTS For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the Dx input to ground. LVPECL OUTPUTS All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC R1 1K Single Ended Clock Input PCLK V_REF nPCLK C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT IDT ™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL RECEIVER 7 ICS853017AM REV. B OCTOBER 24, 2007 ICS853017 QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL RECEIVER PRELIMINARY LVPECL CLOCK INPUT INTERFACE here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The PCLKx /nPCLKx accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and V CMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS PCLKx/nPCLKx input driven by the most common driver types. The input interfaces suggested 2.5V 3.3V 3.3V 3.3V 2.5V 3.3V R1 50 CML R3 120 R2 50 SSTL Zo = 50 Ohm R4 120 Zo = 60 Ohm PCLK PCLK Zo = 60 Ohm Zo = 50 Ohm nPCLK nPCLK HiPerClockS PCLK/nPCLK R1 120 FIGURE 2A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A CML DRIVER HiPerClockS PCLK/nPCLK R2 120 FIGURE 2B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 R4 125 3.3V Zo = 50 Ohm Zo = 50 Ohm C1 LVDS R3 1K R4 1K PCLK PCLK R5 100 Zo = 50 Ohm nPCLK LVPECL R1 84 C2 nPCLK Zo = 50 Ohm HiPerClockS Input R1 1K R2 84 FIGURE 2C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER HiPerClockS PC L K /n PC LK R2 1K FIGURE 2D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER 3.3V 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 84 R4 84 PCLK nPCLK R5 100 - 200 R6 100 - 200 R1 125 HiPerClockS PCLK/nPCLK R2 125 FIGURE 2E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE IDT ™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL RECEIVER 8 ICS853017AM REV. B OCTOBER 24, 2007 ICS853017 QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL RECEIVER PRELIMINARY TERMINATION FOR 3.3V LVPECL OUTPUTS transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω 3.3V Zo = 50Ω 125Ω FOUT 125Ω FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω FIN 50Ω Zo = 50Ω VCC - 2V 1 RTT = Z ((VOH + VOL) / (VCC – 2)) – 2 o RTT 84Ω FIGURE 3A. LVPECL OUTPUT TERMINATION 84Ω FIGURE 3B. LVPECL OUTPUT TERMINATION TERMINATION FOR 5V LVPECL OUTPUT This section shows examples of 5V LVPECL output termination. Figure 4A shows standard termination for 5V LVPECL. The termination requires matched load of 50Ω resistors pull down to V CC - 2V = 3V at the receiver. Figure 4B shows Thevenin equivalence of Figure 4A. In actual application where the 3V DC power supply is not available, this approached is normally used. 5V 5V 5V 5V R3 84 PECL PECL Zo = 50 Ohm R4 84 Zo = 50 Ohm + + Zo = 50 Ohm Zo = 50 Ohm - R1 50 - PECL R1 125 R2 50 PECL R2 125 3V FIGURE 4A. STANDARD 5V LVPECL OUTPUT TERMINATION IDT ™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL RECEIVER FIGURE 4B. 5V LVPECL OUTPUT TERMINATION EXAMPLE 9 ICS853017AM REV. B OCTOBER 24, 2007 ICS853017 QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL RECEIVER PRELIMINARY TERMINATION FOR 2.5V LVPECL OUTPUT Figure 5A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground level. The R3 in Figure 5B can be eliminated and the termination is shown in Figure 5C. 2.5V VCC=2.5V 2.5V 2.5V VCC=2.5V R1 250 Zo = 50 Ohm R3 250 + Zo = 50 Ohm + Zo = 50 Ohm - Zo = 50 Ohm 2,5V LVPECL Driv er - R1 50 2,5V LVPECL Driv er R2 62.5 R2 50 R4 62.5 R3 18 FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE IDT ™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL RECEIVER 10 ICS853017AM REV. B OCTOBER 24, 2007 ICS853017 QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL RECEIVER PRELIMINARY POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS853017. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS853017 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 5.5V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 5.5V * 46mA = 253mW Power (outputs)MAX = 30.94mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30.94mW = 123.76mW Total Power_MAX (5.5V, with all outputs switching) = 123.76mW + 253mW = 376.76mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 46.2°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.377W * 46.2°C/W = 102.4°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 20-PIN SOIC, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 83.2°C/W 46.2°C/W 65.7°C/W 39.7°C/W 57.5°C/W 36.8°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. IDT ™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL RECEIVER 11 ICS853017AM REV. B OCTOBER 24, 2007 ICS853017 QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL RECEIVER PRELIMINARY 3. Calculations and Equations. LVPECL output driver circuit and termination are shown in Figure 6. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 6. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC • For logic high, VOUT = VOH_MAX = VCC_MAX – 0.935V (VCC_MAX - VOH_MAX) = 0.935V • For logic low, VOUT = VOL_MAX = VCC_MAX – 1.67V (VCC_MAX - VOL_MAX) = 1.67V Pd_H = [(VOH_MAX – (VCC_MAX - 2V))/R ] * (VCC_MAX - VOH_MAX) = [(2V - (V L CC_MAX - VOH_MAX))/R ] * (VCC _MAX- VOH_MAX) = L [(2V - 0.935V)/50Ω] * 0.935V = 19.92mW Pd_L = [(VOL_MAX – (VCC_MAX - 2V))/R ] * (VCC_MAX - VOL_MAX) = [(2V - (V L CC_MAX - VOL_MAX))/R ] * (VCC_MAX - VOL_MAX) = L [(2V - 1.67V)/50Ω] * 1.67V = 11.02mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW IDT ™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL RECEIVER 12 ICS853017AM REV. B OCTOBER 24, 2007 ICS853017 QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL RECEIVER PRELIMINARY RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 20 LEAD SOIC θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 83.2°C/W 46.2°C/W 65.7°C/W 39.7°C/W 57.5°C/W 36.8°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS853017 is: 187 Pin compatible with MC100EP58 PACKAGE OUTLINE - M SUFFIX FOR 20 LEAD SOIC TABLE 8. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N Maximum 20 A -- 2.65 A1 0.10 -- A2 2.05 2.55 B 0.33 0.51 C 0.18 0.32 D 12.60 13.00 E 7.40 7.60 e H 1.27 BASIC 10.00 10.65 h 0.25 0.75 L 0.40 1.27 α 0° 8° Reference Document: JEDEC Publication 95, MS-013, MO-119 IDT ™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL RECEIVER 13 ICS853017AM REV. B OCTOBER 24, 2007 ICS853017 QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL RECEIVER PRELIMINARY TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS853017AM ICS853017AM 20 lead SOIC tube -40°C to 85°C ICS853017AMT ICS853017AM 20 lead SOIC 1000 tape & reel -40°C to 85°C ICS853017AMLF TBD 20 lead "Lead-Free" SOIC tube -40°C to 85°C ICS853017AMLFT TBD 20 lead "Lead-Free" SOIC 1000 tape & reel -40°C to 85°C Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL RECEIVER 14 ICS853017AM REV. B OCTOBER 24, 2007 ICS853017 QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL RECEIVER PRELIMINARY Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA