89497

REVISIONS
LTR
DESCRIPTION
DATE (YR-MO-DA)
APPROVED
A
Add device types 03 and 04. Add case outline M. Add vendor CAGE
01295 as source of supply for device types 03 and 04. Update
boilerplate. Editorial changes throughout.
94-11-01
M. A. Frye
B
Corrected number of leads for case outline package T in section 1.2.4
from 32 to 28. Updated boilerplate as part of 5 year review. ksr
06-02-27
Raymond Monnin
C
Updated drawing in accordance with current MIL-PRF-38535
requirements. - glg
14-01-27
Charles Saffle
REV
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
SHEET
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
REV
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
SHEET
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
REV STATUS
REV
C
C
C
C
C
C
C
C
C
C
C
C
C
C
OF SHEETS
SHEET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PMIC N/A
PREPARED BY
Rajesh Pithadia
STANDARD
MICROCIRCUIT
DRAWING
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil
CHECKED BY
Kenneth Rice
APPROVED BY
THIS DRAWING IS
AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
DLA LAND AND MARITIME
Michael Frye
DRAWING APPROVAL DATE
MICROCIRCUIT, MEMORY, DIGITAL,
CMOS, 256K X 4 VIDEO RAM,
MONOLITHIC SILICON
92-12-16
REVISION LEVEL
C
SIZE
CAGE CODE
A
67268
SHEET
DSCC FORM 2233
APR 97
5962-89497
1
OF
50
5962-E147-14
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and
M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part
or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
|
|
|
Federal
stock class
designator
\
|
|
|
RHA
designator
(see 1.2.1)
89497
01
|
|
|
Device
type
(see 1.2.2)
/
M
|
|
|
Device
class
designator
(see 1.2.3)
X
|
|
|
Case
outline
(see 1.2.4)
A
|
|
|
Lead
finish
(see 1.2.5)
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
Generic number 1/
01
02
03
04
Circuit function
Access time
Access time
120 ns
100 ns
120 ns
100 ns
35 ns
30 ns
35 ns
30 ns
256K x 4, multiport video RAM
256K x 4, multiport video RAM
256K x 4, multiport video RAM
256K x 4, multiport video RAM
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level
as follows:
Device class
Device requirements documentation
M
Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN
class level B microcircuits in accordance with MIL-PRF-38535, appendix A
Q or V
Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
T
U
X
Y
Z
M
Descriptive designator
See figure 1
CDFP4-F28
See figure 1
See figure 1
See figure 1
See figure 1
Terminals
28
28
28
28
28
28
Package style
"J" lead chip carrier
Flat pack
Dual-in-line
"J" lead chip carrier
Rectangular leadless chip carrier
Zig-zag in-line
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix
A for device class M.
1/ Generic numbers are listed on the Standard Microcircuit Drawing Source Approval Bulletin at the end of this document and
will also be listed in MIL-HDBK-103.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-89497
A
REVISION LEVEL
C
SHEET
2
1.3 Absolute maximum ratings. 2/
Voltage range on any pin except DQ and SDQ ---Voltage range on DQ and SDQ -----------------------Voltage range on VCC ------------------------------------Short circuit output current (per output) -------------Power dissipation (PD) ----------------------------------Storage temperature range ----------------------------Lead temperature (soldering, 10 seconds) --------Thermal resistance, junction-to-case (θJC):
Case U -----------------------------------------------------Cases X, Y, Z, and T -----------------------------------Case M -----------------------------------------------------Junction temperature (TJ) 4/ ----------------------------
-1 V dc to 7 V dc
-1 V dc to VCC
0 V dc to 7 V dc
50 mA
1W
-65°C to 150°C
+300°C
See MIL-STD-1835
10°C/W 3/
5°C/W 3/
+175°C
1.4 Recommended operating conditions.
Supply voltage range (VCC) 5/ -------------------------Supply voltage (VSS) --------------------------------------High level input voltage range (VIH)-------------------Low level input voltage range (VIL) 6/ --------------System transition times, rise and fall (tt) ------------Case operating temperature range (TC) --------------
+4.5 V dc to +5.5 V dc
0.0 V dc
2.9 V dc to VCC
-1.0 V dc to 0.6 V dc
3 ns to 50 ns
-55°C to +125°C
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 MIL-STD-1835 -
Test Method Standard Microcircuits.
Interface Standard For Microcircuit Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 MIL-HDBK-780 -
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at http://quicksearch.dla.mil or from the Standardization Document Order
Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
3/ When the thermal resistance for this case is specified in MIL-STD-1835, that value shall supersede the value indicated
herein.
4/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in
accordance with method 5004 of MIL-STD-883.
5/ All voltage values in this drawing are with respect to VSS.
6/ The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this drawing for
voltage levels only.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-89497
A
REVISION LEVEL
C
SHEET
3
JEDEC INTERNATIONAL (JEDEC)
JESD 78
-
IC Latch-Up Test.
(Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington, VA
22201; http://www.jedec.org.)
(Non-Government standards and other publications are normally available from the organizations that prepare or distribute the
documents. These documents also may be available in or through libraries or other informational services.)
2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless
a specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.
3.2.3 Truth table(s). The truth table shall be as specified on figure 3.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the
full case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in Table I.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be
in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-89497
A
REVISION LEVEL
C
SHEET
4
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see
6.6.2 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of
supply for this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MILPRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for
device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DLA Land and Maritime-VA of change of
product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing.
3.9 Verification and review for device class M. For device class M, DLA Land and Maritime, DLA Land and Maritime's agent,
and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore
documentation shall be made available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 41 (see MIL-PRF-38535, appendix A).
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-89497
A
REVISION LEVEL
C
SHEET
5
Table I. Electrical performance characteristics.
Test
High level output
voltage
Low level output
voltage
1/
Input leakage
current
Output leakage current 2/
Operation current
(standby) 3/
Operation current
(active) 3/
Standby current
(standby) 3/
Standby current
(active) 3/
RAS-only refresh current
(standby)
3/
RAS-only refresh current
(active)
3/
Page mode current
(standby)
3/
Page mode current
(active)
3/
CAS-before-RAS current
(standby)
3/
CAS-before-RAS current
(active)
3/
│
│Symbol/
│alten.
│symbol
│
│
│VOH
│
│
│VOL
│
│
│IL
│
│
│
│IO
│
│
│ICC1
│
│
│
│
│ICC1A
│
│
│
│ICC2
│
│
│
│ICC2A
│
│
│
│ICC3
│
│
│
│ICC3A
│
│
│
│ICC4
│
│
│
│ICC4A
│
│
│
│ICC5
│
│
│
│ICC5A
│
│
│
│
Conditions
│
-55°C ≤ TC ≤ +125°C
│
4.5 V ≤ VCC ≤ 5.5 V
│ unless otherwise specified
│
│ IOH = -5 mA
│
│
│ IOL = 4.2 mA
│
│
│ VI = 0 to 5.8 V, VCC = 5 V
│ All other pins open
│
│
│ VO = 0 to VCC, VCC = 5.5 V
│
│
│ tc(RW) = minimum
│ tc(SC) = minimum
│
│
│
│
│
│
│
│ All clocks = VCC
│ tc(SC) = minimum
│
│
│
│
│
│
│ tc(RW) = minimum
│ tc(SC) = minimum
│
│
│
│
│
│
│ tc(P) = minimum
│ tc(SC) = minimum
│
│
│ tC(P) = minimum
│ tC(SC) = minimum
│
│
│ tc(RW) = minimum
│ tc(SC) = minimum
│
│
│
│
│
│
│Group A
│subgroups
│
│
│
│ 1,2,3
│
│
│ 1,2,3
│
│
│ 1,2,3
│
│
│
│ 1,2,3
│
│
│ 1,2,3
│
│
│
│
│ 1,2,3
│
│
│
│ 1,2,3
│
│
│
│ 1,2,3
│
│
│
│ 1,2,3
│
│
│
│ 1,2,3
│
│
│
│ 1,2,3
│
│
│
│ 1,2,3
│
│
│
│ 1,2,3
│
│
│
│ 1,2,3
│
│
│
│Device
│ type
│
│
│
│ All
│
│
│ All
│
│
│ 01,02
│
│ 03,04
│
│ All
│
│
│ 01,03
│
│ 02,04
│
│
│ 01,03
│
│ 02,04
│
│ All
│
│
│
│ 01,03
│
│ 02,04
│
│ 01,03
│
│ 02,04
│
│ 01,03
│
│ 02,04
│
│ 01,03
│
│ 02,04
│
│ 01,03
│
│ 02,04
│
│ 01,03
│
│ 02,04
│
│ 01,03
│
│ 02,04
│
│
Limits
│
│
│ Min │ Max
│
│
│
│
│ 2.4 │
│
│
│
│
│
│ 0.4
│
│
│
│
│
│ ±1.0
│
│
│
│ ±10
│
│
│
│ ±10
│
│
│
│
│
│ 90
│
│
│
│ 100
│
│
│
│
│
│ 110
│
│
│
│ 120
│
│
│
│ 15
│
│
│
│
│
│
│
│ 50
│
│
│
│ 55
│
│
│
│ 90
│
│
│
│ 100
│
│
│
│ 120
│
│
│
│ 125
│
│
│
│ 60
│
│
│
│ 65
│
│
│
│ 90
│
│
│
│ 100
│
│
│
│ 80
│
│
│
│ 90
│
│
│
│ 110
│
│
│
│ 115
│
│ Unit
│
│
│
│
│V
│
│
│V
│
│
│ μA
│
│
│
│ μA
│
│
│ mA
│
│
│
│
│ mA
│
│
│
│ mA
│
│
│
│ mA
│
│
│
│ mA
│
│
│
│ mA
│
│
│
│ mA
│
│
│
│ mA
│
│
│
│ mA
│
│
│
│ mA
│
│
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-89497
A
REVISION LEVEL
C
SHEET
6
Table I. Electrical performance characteristics - continued.
Test
Data transfer current
(standby)
3/
Data transfer current
(active)
3/
Input capacitance, address
inputs
Input capacitance, strobe
inputs
Input capacitance, write
enable input
Input capacitance, serial
clock input
Input capacitance, special
function
Input capacitance, serial
enable
Input capacitance,
transfer register input
Output capacitance, SDQ
and DQ
Output capacitance, QSF
Functional tests
Access time from
CAS
Access time from
column address
Access time from
CAS high
│
│Symbol/
│alten.
│symbol
│
│
│ICC6
│
│
│
│ICC6A
│
│
│
│CI(A)
│
│
│CI(RC)
│
│
│CI(W)
│
│
│CI(SC)
│
│
│CI(DSF)
│
│
│CI(SE)
│
│
│CI(TRG)
│
│
│CO(O)
│
│
│CO(QSF)
│
│
│
│
│
│ta(C)
│
│tCAL
│
│
│ta(CA)
│
│tAA
│
│
│ta(CP)
│
│ tCPA
│
│
│
Conditions
│
-55°C ≤ TC ≤ +125°C
│
4.5 V ≤ VCC ≤ 5.5 V
│ unless otherwise specified
│
│ tc(RW) = minimum
│ tc(SC) = minimum
│
│
│
│
│
│
│ See 4.4.1e
│ f = 1 MHz, VIN = 0 V
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│ See 4.4.1e
│ f = 1 MHz, VIN = 0 V
│
│
│
│
│ See 4.4.1c
│
│
│ (See figures 4 and 5)
│ td(RLCL) = max, CL = 80 pF
│
│
│
│ (See figures 4 and 5)
│ td(RLCL) = max, CL = 80 pF
│
│
│
│ (See figures 4 and 5)
│ td(RLCL) = min, CL = 80 pF
│
│
│
│Group A
│subgroups
│
│
│
│ 1,2,3
│
│
│
│ 1,2,3
│
│
│
│ 4
│
│
│ 4
│
│
│ 4
│
│
│ 4
│
│
│ 4
│
│
│ 4
│
│
│ 4
│
│
│ 4
│
│
│ 4
│
│
│ 7,8A,8B
│
│
│ 9,10,11
│
│
│
│
│ 9,10,11
│
│
│
│
│ 9,10,11
│
│
│
│
│Device
│ type
│
│
│
│ 01,03
│
│ 02,04
│
│ 01,03
│
│ 02,04
│
│ All
│
│
│ All
│
│
│ All
│
│
│ All
│
│
│ All
│
│
│ All
│
│
│ All
│
│
│ All
│
│
│ All
│
│
│ All
│
│
│ 01,03
│
│ 02,04
│
│
│ 01,03
│
│ 02,04
│
│
│ 01,03
│
│ 02,04
│
│
│ Limits
│
│
│ Min │
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│ L
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
Max
90
100
125
130
9
10
10
10
10
10
10
11
17
H
30
25
60
50
65
55
│
│ Unit
│
│
│
│
│ mA
│
│
│
│ mA
│
│
│
│ pF
│
│
│ pF
│
│
│ pF
│
│
│ pF
│
│
│ pF
│
│
│ pF
│
│
│ pF
│
│
│ pF
│
│
│ pF
│
│
│V
│
│
│ ns
│
│
│
│
│ ns
│
│
│
│
│ ns
│
│
│
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-89497
A
REVISION LEVEL
C
SHEET
7
Table I. Electrical performance characteristics - continued.
Test
Access time from
RAS high
Access time of Q
from TRG low
Access time of SQ
from SC high 4/
Access time of SQ
from SE low
4/
Access time of QSF
from SC low
Disable time, random
output from CAS high
Disable time, random
output from TRG high 5/
Disable time, serial
output from SE high 5/
Cycle time, read
6/
Cycle time, write
Cycle time, readmodify write
Cycle time, pagemode read, write
│
│Symbol/
│alten.
│symbol
│
│
│ta(R)
│tRAC
│
│
│ta(G)
│tOE
│
│
│ta(SQ)
│tSAC
│
│
│ta(SE)
│
│tSEA
│
│
│
│ta(QSF)
│
│
│
│tdis(CH)
│tOFF
│
│
│tdis(G)
│tOD
│
│
│tdis(SE)
│tSEZ
│
│
│tc(rd)
│tRC
│
│
│tc(W)
│tRC
│
│
│tc(rdW)
│tRWC
│
│
│
│
│tc(P)
│tPC
│
│
│
Conditions
│
-55°C ≤ TC ≤ +125°C
│
4.5 V ≤ VCC ≤ 5.5 V
│ unless otherwise specified
│
│(See figures 4 and 5)
│ td(RLCL) = min, CL = 80 pF
│
│
│ (See figures 4 and 5)
│ CL = 80 pF
│
│
│ (See figures 4 and 5)
│ CL = 30 pF
│
│
│ (See figures 4 and 5)
│ CL = 30 pF
│
│
│
│
│ (See figures 4 and 5)
│ CL = 30 pF
│
│
│ (See figures 4 and 5)
│ CL = 80 pF
│
│
│ (See figures 4 and 5)
│ CL = 80 pF
│
│
│ (See figures 4 and 5)
│ CL = 30 pF
│
│
│ (See figures 4 and 5)
│ CL = 80 pF
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│Group A
│subgroups
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│
│
│ 9,10,11
│
│
│
│Device
│ type
│
│
│
│ 01,03
│
│ 02,04
│
│ 01,03
│
│ 02,04
│
│ 01,03
│
│ 02,04
│
│ 01
│
│ 03
│
│ 02,04
│
│ 01,02
│
│
│
│ 01
│
│ 02-04
│
│ 01
│
│ 02-04
│
│ All
│
│
│
│ 01,03
│
│ 02,04
│
│ 01,03
│
│ 02,04
│
│ 01
│
│ 03
│
│ 02,04
│
│ 01
│
│ 02
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
Limits
│
Unit
│
│
Min │ Max │
│
│
│
│
│ 120 │ ns
│
│
│ 100 │
│
│
│ 30 │ ns
│
│
│ 25 │
│
│
│ 35 │ ns
│
│
│ 30 │
│
│
│ 30 │ ns
│
│
│ 25 │
│
│
│ 20 │
│
│
│ 60 │ ns
│
│
│
│
│
│
0 │ 30 │ ns
│
│
0 │ 20 │
│
│
0 │ 30 │ ns
│
│
0 │ 20 │
│
│
0 │ 20 │ ns
│
│
│
│
│
│
220 │
│ ns
│
│
190 │
│
│
│
220 │
│ ns
│
│
190 │
│
│
│
295 │
│ ns
│
│
290 │
│
│
│
250 │
│
│
│
70 │
│ ns
│
│
60 │
│
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-89497
A
REVISION LEVEL
C
SHEET
8
Table I. Electrical performance characteristics - continued.
Test
Cycle time, page-mode
read-modify-write
Cycle time,
transfer read
Cycle time,
transfer write
Cycle time, serial
clock
7/
Pulse duration,
CAS high
Pulse duration,
CAS low 8/ 9/
Pulse duration,
RAS high
Pulse duration,
RAS low 9/ 10/
Pulse duration,
W low
Pulse duration,
TRG low
Pulse duration,
SC high
Pulse duration,
SC low
│
│Symbol/
│alten.
│symbol
│
│
│tc(RDWP)
│tPRWC
│
│
│
│
│
│
│tc(TRD)
│tRC
│
│
│tc(TW)
│tRC
│
│
│tc(SC)
│
│
│
│tw(CH)
│tCP
│
│
│tw(CL)
│tCAS
│
│
│tw(RH)
│tRP
│
│
│tw(RL)
│tRAS
│
│
│tw(WL)
│tWP
│
│
│tw(TRG)
│
│
│
│tw(SCH)
│tSAS
│
│
│tw(SCL)
│tSP
│
│
│
Conditions
│
-55°C ≤ TC ≤ +125°C
│
4.5 V ≤ VCC ≤ 5.5 V
│ unless otherwise specified
│
│ (See figures 4 and 5)
│ CL = 80 pF
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│Group A
│subgroups
│
│
│
│ 9,10,11
│
│
│
│
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│Device
│ type
│
│
│
│ 01
│
│ 02
│
│ 03
│
│ 04
│
│ 01,03
│
│ 02,04
│
│ 01,03
│
│ 02,04
│
│ 01,03
│
│ 02,04
│
│ 01,03
│
│ 02,04
│
│ 01,03
│
│ 02,04
│
│ 01,03
│
│ 02,04
│
│ 01,03
│
│ 02,04
│
│ All
│
│
│
│ 01,03
│
│ 02,04
│
│ 01,03
│
│ 02,04
│
│ 01,03
│
│ 02,04
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
Limits
│
Min │ Max
│
│
130 │
│
110 │
│
125 │
│
105 │
│
220 │
│
190 │
│
220 │
│
190 │
│
35 │
│
30 │
│
30 │
│
20 │
│
30 │75,000
│
25 │75,000
│
90 │
│
80 │
│
120 │75,000
│
100 │75,000
│
25 │
│
│
│
30 │
│
25 │
│
12 │
│
10 │
│
12 │
│
10 │
│
│ Unit
│
│
│
│
│ ns
│
│
│
│
│
│
│
│ ns
│
│
│
│ ns
│
│
│
│ ns
│
│
│
│ ns
│
│
│
│ ns
│
│
│
│ ns
│
│
│
│ ns
│
│
│
│ ns
│
│
│
│ ns
│
│
│
│ ns
│
│
│
│ ns
│
│
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-89497
A
REVISION LEVEL
C
SHEET
9
Table I. Electrical performance characteristics - continued.
│
│Symbol/
│alten.
│symbol
│
│
Setup time,
│tsu(CA)
column address
│tASC
│
│
Setup time, DSF before CAS │tsu(SFC)
low
│
│
Setup time, row
│tsu(RA)
address
│tASR
│
│
Setup time, W
│tsu(WMR)
before RAS low
│tWSR
│
│
Setup time, DQ
│tsu(DQR)
before RAS low
│tTMS
│
│
Setup time, TRG
│tsu(TRG)
before RAS low
│tTLS
│
│
Setup time, SE before RAS │tsu(SE)
low
9/ 11/
│tESR
│
│
Setup time, DSF before RAS │tsu(SFR)
low
│
│
Setup time, data before
│tsu(DCL)
CAS low
12/
│tDS
│
│
Setup time, data
│tsu(DWL)
before W low 12/
│tDS
│
│
Setup time, read
│tsu(rd)
command
│tRCS
│
│
Setup time, early write
│tsu(WCL)
command before CAS low │tWCS
│
│
Setup time, write
│tsu(WCH)
before CAS high
│tCWL
│
│
Setup time, write
│tsu(WRH)
before RAS high
│tRWL
│
Test
│
│
Conditions
│
-55°C ≤ TC ≤ +125°C
│
4.5 V ≤ VCC ≤ 5.5 V
│ unless otherwise specified
│
│ (See figures 4 and 5)
│ CL = 80 pF
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│Group A
│subgroups
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│Device
│ type
│
│
│
│ All
│
│
│
│ All
│
│
│ All
│
│
│
│ All
│
│
│
│ All
│
│
│
│ All
│
│
│
│ All
│
│
│
│ All
│
│
│ All
│
│
│
│ All
│
│
│
│ All
│
│
│
│ All
│
│
│
│ 01,03
│
│ 02,04
│
│ 01,03
│
│ 02,04
│
│
│ Limits
│ Unit
│
│
│
│ Min │ Max │
│
│
│
│
│
│
│ 0 │
│ ns
│
│
│
│
│
│
│
│
│
│ 0 │
│ ns
│
│
│
│
│
│
│ 0 │
│ ns
│
│
│
│
│
│
│
│
│
│ 0 │
│ ns
│
│
│
│
│
│
│
│
│
│ 0 │
│ ns
│
│
│
│
│
│
│
│
│
│ 0 │
│ ns
│
│
│
│
│
│
│
│
│
│ 0 │
│ ns
│
│
│
│
│
│
│
│
│
│ 0 │
│ ns
│
│
│
│
│
│
│ 0 │
│ ns
│
│
│
│
│
│
│
│
│
│ 0 │
│ ns
│
│
│
│
│
│
│
│
│
│ 5 │
│ ns
│
│
│
│
│
│
│
│
│
│ 0 │
│ ns
│
│
│
│
│
│
│
│
│
│ 30 │
│ ns
│
│
│
│ 25 │
│
│
│
│
│ 30 │
│ ns
│
│
│
│ 25 │
│
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-89497
A
REVISION LEVEL
C
SHEET
10
Table I. Electrical performance characteristics - continued.
Test
Setup time, SD
before SC high
Hold time, column address
after CAS low
Hold time, DSF after CAS
low
Hold time, row address
address after RAS low
Hold time, TRG
after RAS low
Hold time, SE after
RAS low 9/ 11/
Hold time, write mask
transfer enable after
RAS low
Hold time, DQ after RAS
low (write mask
operation)
Hold time, DSF after RAS
low
Hold time, column address
after RAS low 13/
Hold time, data
after CAS low
Hold time, data after RAS
low
13/
Hold time, data
after W low
│
│Symbol/
│alten.
│symbol
│
│
│tsu(SDS)
│tSDS
│
│
│th(CLCA)
│tCAH
│
│
│th(SFC)
│
│
│th(RA)
│tRAH
│
│
│th(TRG)
│tTLH
│
│
│th(SE)
│tREH
│
│
│th(RWM)
│tRWH
│
│
│th(RDQ)
│tMH
│
│
│th(SFR)
│
│
│th(RLCA)
│tAR
│
│
│th(CLD)
│tDH
│
│
│th(RLD)
│tDHR
│
│
│th(WLD)
│tDH
│
│
│
Conditions
│
-55°C ≤ TC ≤ +125°C
│
4.5 V ≤ VCC ≤ 5.5 V
│ unless otherwise specified
│
│ (See figures 4 and 5)
│ CL = 80 pF
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│Group A
│subgroups
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│Device
│ type
│
│
│
│ 01,02
│
│ 03,04
│
│ 01
│
│ 02-04
│
│ All
│
│
│ All
│
│
│
│ All
│
│
│
│ All
│
│
│
│ All
│
│
│
│ All
│
│
│
│ All
│
│
│ 01-03
│
│ 04
│
│ 01,03
│
│ 02,04
│
│ 01-03
│
│ 04
│
│ 01,03
│
│ 02,04
│
│
│ Limits
│ Unit
│
│
│
│ Min │ Max │
│
│
│
│
│
│
│ 3 │
│ ns
│
│
│
│ 0 │
│
│
│
│
│ 25 │
│ ns
│
│
│
│ 20 │
│
│
│
│
│ 20 │
│ ns
│
│
│
│
│
│
│ 15 │
│ ns
│
│
│
│
│
│
│
│
│
│ 15 │
│ ns
│
│
│
│
│
│
│
│
│
│ 15 │
│ ns
│
│
│
│
│
│
│
│
│
│ 15 │
│ ns
│
│
│
│
│
│
│
│
│
│ 15 │
│ ns
│
│
│
│
│
│
│
│
│
│ 15 │
│ ns
│
│
│
│
│
│
│ 50 │
│ ns
│
│
│
│ 45 │
│
│
│
│
│ 25 │
│ ns
│
│
│
│ 20 │
│
│
│
│
│ 50 │
│ ns
│
│
│
│ 45 │
│
│
│
│
│ 25 │
│ ns
│
│
│
│ 20 │
│
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-89497
A
REVISION LEVEL
C
SHEET
11
Table I. Electrical performance characteristics - continued.
Test
Hold time, TRG after W low
(output enable
9/
controlled write)
Hold time, read
after CAS
14/
Hold time, read
after RAS
14/
Hold time, write
after CAS low
Hold time, write after
RAS low
13/
Hold time, SD
after SC high
Hold time, SQ
after SC high
9/
Delay time, RAS
low to CAS high
Delay time, CAS
high to RAS low
Delay time, CAS
low to RAS high
Delay time, CAS
low to W low
15/ 16/
│
│Symbol/
│alten.
│symbol
│
│
│th(WLG)
│tOEH
│
│
│th(CHrd)
│tRCH
│
│
│th(RHrd)
│tRRH
│
│
│th(CLW)
│tWCH
│
│
│th(RLW)
│tWCR
│
│
│th(SDS)
│tSDH
│
│
│th(SHSQ)
│tSOH
│
│
│td(RLCH)
│tCSH
│
│
│td(CHRL)
│tCRP
│
│
│
│
│td(CLRH)
│tRSH
│
│
│
│
│td(CLWL)
│
│tCWD
│
│
│
│
│
│
Conditions
│
-55°C ≤ TC ≤ +125°C
│
4.5 V ≤ VCC ≤ 5.5 V
│ unless otherwise specified
│
│ (See figures 4 and 5)
│ CL = 80 pF
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│Group A
│subgroups
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│
│
│ 9,10,11
│
│
│
│
│
│ 9,10,11
│
│
│
│
│
│
│
│Device
│ type
│
│
│
│ 01,03
│
│ 02,04
│
│ All
│
│
│
│ All
│
│
│
│ 01,03
│
│ 02,04
│
│ 01,03
│
│ 02,04
│
│ 01,02
│
│ 03,04
│
│ All
│
│
│
│ 01,03
│
│ 02,04
│
│ 01
│
│ 02
│
│ 03,04
│
│ 01
│
│ 02,03
│
│ 04
│
│ 01
│
│ 02
│
│ 03
│
│ 04
│
│
│ Limits
│ Unit
│
│
│
│ Min │ Max │
│
│
│
│
│
│
│ 30 │
│ ns
│
│
│
│ 25 │
│
│
│
│
│ 0 │
│ ns
│
│
│
│
│
│
│
│
│
│ 10 │
│ ns
│
│
│
│
│
│
│
│
│
│ 35 │
│ ns
│
│
│
│ 30 │
│
│
│
│
│ 55 │
│ ns
│
│
│
│ 50 │
│
│
│
│
│ 20 │
│ ns
│
│
│
│ 5 │
│
│
│
│
│ 5 │
│ ns
│
│
│
│
│
│
│
│
│
│ 120 │
│ ns
│
│
│
│ 100 │
│
│
│
│
│ 10 │
│ ns
│
│
│
│ 5 │
│
│
│
│
│ 0 │
│
│
│
│
│ 35 │
│ ns
│
│
│
│ 30 │
│
│
│
│
│ 25 │
│
│
│
│
│ 75 │
│ ns
│
│
│
│ 60 │
│
│
│
│
│ 65 │
│
│
│
│
│ 55 │
│
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-89497
A
REVISION LEVEL
C
SHEET
12
Table I. Electrical performance characteristics - continued.
│
│Symbol/
│alten.
│symbol
│
│
Delay time, RAS low to
│td(RLCL)
CAS low
17/
│tRCD
│
│
Delay time, column
│td(CARH)
address to RAS high
│tRAL
│
│
Delay time, RAS low to W
│td(RLWL)
low
15/
│tRWD
│
│
│
│
Delay time, column address │td(CAWL)
to W low
9/ 15/
│tAWD
│
│
Delay time, RAS low to CAS │td(RLCH)R
high
9/ 18/
│tCHR
│
│
Delay time, CAS low
│td(CLRL)R
to RAS low
18/
│tCSR
│
│
Delay time, RAS high to
│td(RHCL)R
CAS low
9/ 18/
│tRPC
│
│
Delay time, CAS
│td(CLGH)
low to TRG high
│tCTH
│
│
Delay time, TRG high
│td(GHD)
before data applied at
│
DQ
15/
│tOD
│
│
Delay time, RAS low to
│td(RLTH)
TRG high
9/
│tRTH
│
│
Delay time, RAS low to
│td(RLSH)
first SC high after
│
TRG high
9/ 19/
│tRSD
│
│
Delay time, CAS low to
│td(CLSH)
first SC high after
│
TRG high
9/ 19/
│tCSD
│
Test
│
│
Conditions
│
-55°C ≤ TC ≤ +125°C
│
4.5 V ≤ VCC ≤ 5.5 V
│ unless otherwise specified
│
│ (See figures 4 and 5)
│ CL = 80 pF
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│Group A
│subgroups
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│
│ 9,10,11
│
│
│
│
│Device
│ type
│
│
│
│ 01,03
│
│ 02,04
│
│ 01,03
│
│ 02,04
│
│ 01
│
│ 03
│
│ 02,04
│
│ 01,03
│
│ 02,04
│
│ 01,02
│
│ 03,04
│
│ All
│
│
│
│ All
│
│
│
│ 01,03
│
│ 02,04
│
│ 01,03
│
│
│ 02,04
│
│ 01,03
│
│ 02,04
│
│ 01,03
│
│ 02,04
│
│
│ 01,03
│
│ 02,04
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
Limits
│ Unit
│
│
Min │ Max │
│
│
│
│
25 │ 90 │ ns
│
│
25 │ 75 │
│
│
60 │
│ ns
│
│
50 │
│
│
│
160 │
│ ns
│
│
155 │
│
│
│
130 │
│
│
│
100 │
│ ns
│
│
85 │
│
│
│
30 │
│ ns
│
│
25 │
│
│
│
10 │
│ ns
│
│
│
│
│
│
10 │
│ ns
│
│
│
│
│
│
30 │
│ ns
│
│
25 │
│
│
│
30 │
│ ns
│
│
│
│
25 │
│
│
│
95 │
│ ns
│
│
90 │
│
│
│
140 │
│ ns
│
│
130 │
│
│
│
│
│
45 │
│ ns
│
│
40 │
│
│
│
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-89497
A
REVISION LEVEL
C
SHEET
13
Table I. Electrical performance characteristics - continued.
│
│Symbol/
│alten.
│symbol
│
│
Delay time, SC high to TRG │td(SCTR)
high
9/ 19/ 20/
│tTTSC
│
│
Delay time, TRG high to
│td(THRH)
RAS high
19/
│tTRL
│
│
Delay time, SC high to RAS │td(SCRL)
low
9/ 11/ 21/
│tSRS
│
│
│
│
Delay time, SC high to SE
│td(SCSE)
high in serial 9/ 22/
│tSWH
input mode
│
│
Delay time, RAS high to SC │td(RHSC)
high
9/ 11/
│tSRD
│
│
Delay time, TRG
│td(THRL)
high to RAS low 23/
│
│
│
Delay time, TRG high to SC │td(THSC)
high
23/
│tTSO
│
│
Delay time, SE low to SC
│td(SESC)
high
9/ 22/
│tSWS
│
│
Delay time, RAS high to
│td(RHMS)
last (most significant)
│
rising edge of SC before
│
boundary switch (split
│
read transfer cycles)
│
│
│
│
Delay time, first (TAP)
│td(TPRL)
rising edge of SC after
│
boundary switch to RAS
│
low (split read transfer
│
cycles)
│
│
Refresh time
│trf(MA)
interval, memory
│tREF
│
Test
│
│
Conditions
│
-55°C ≤ TC ≤ +125°C
│
4.5 V ≤ VCC ≤ 5.5 V
│ unless otherwise specified
│
│ (See figures 4 and 5)
│ CL = 80 pF
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│Group A
│subgroups
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│
│
│
│
│
│ 9,10,11
│
│
│
│
│
│ 9,10,11
│
│
│
│Device
│ type
│
│
│
│ 01,03
│
│ 02,04
│
│ All
│
│
│
│ 01,03
│
│ 02
│
│ 04
│
│ All
│
│
│
│ 01,03
│
│ 02,04
│
│ All
│
│
│
│ 01,03
│
│ 02,04
│
│ 01,03
│
│ 02,04
│
│ 01
│
│ 02
│
│ 03
│
│ 04
│
│ 01
│
│
│ 02
│
│
│ All
│
│
│
│
│ Limits
│ Unit
│
│
│
│ Min │ Max │
│
│
│
│
│
│
│ 20 │
│ ns
│
│
│
│ 15 │
│
│
│
│
│ -10 │
│ ns
│
│
│
│
│
│
│
│
│
│ 20 │
│ ns
│
│
│
│ 15 │
│
│
│
│
│ 10 │
│
│
│
│
│ 20 │
│ ns
│
│
│
│
│
│
│
│
│
│ 30 │
│ ns
│
│
│
│ 25 │
│
│
│
│
│tw(RH) │
│ ns
│
│
│
│
│
│
│
│
│
│ 40 │
│ ns
│
│
│
│ 35 │
│
│
│
│
│ 15 │
│ ns
│
│
│
│ 10 │
│
│
│
│
│ 30 │
│ ns
│
│
│
│ 25 │
│
│
│
│
│ 20 │
│
│
│
│
│ 15 │
│
│
│
│
│ 25 │
│ ns
│
│
│
│
│
│
│ 20 │
│
│
│
│
│
│
│
│
│ 8 │ ms
│
│
│
│
│
│
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-89497
A
REVISION LEVEL
C
SHEET
14
Table I. Electrical performance characteristics - continued.
1/
These devices exhibit simultaneous switching noise. This phenomenon exhibits itself upon the DQ pins when the SDQ
pins are switched and upon the SDQ pins when DQ pins are switched. This may cause the VOL and VOH to exceed the
limit for a short period of time, depending upon output loading and temperature. Care should be taken to provide
proper termination, decoupling, and layout of the device to minimize simultaneous switching effects.
2/
3/
8/
SE is disabled for SDQ output leakage tests.
ICC (standby) versus ICCA (active) denotes the following:
ICC (standby): SAM port is inactive (standby) and the DRAM port is active (except for ICC2).
ICCA (active): SAM port is active and the DRAM port is active (except for ICC2A).
ICC is measured with no load on DQ or SDQ pins.
SAM output timing may be measured with a load equivalent to 2 TTL gates plus 30 pF. Output reference levels:
VOH = 2.0 V, VOL = 0.8 V.
Disable times are specified when the output is no longer driven.
All cycle times assume tt = 5 ns.
When the odd tap is used (tap address can be 0-511, and odd taps are 1,3,5, etc.), the cycle time for SC in serial data out
cycle needs to be 70 ns minimum.
In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed. Depending on the user's transition times,
9/
10/
this may require additional CAS low time, tw(CL).
If not tested, shall be guaranteed to the limits in table IA.
In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed. Depending on the user's transition times,
11/
this may require additional RAS low time, tw(RL).
Register to memory (write) transfer cycles only.
4/
5/
6/
7/
12/
13/
14/
15/
These parameters are referenced to CAS leading edge in early-write cycles and ME / NE leading edge in late write or
read-write cycles.
The minimum value is measured when td(RLCL) is set to td(RLCL) minimum as a reference.
Either th(RHrd) or th(CHrd) must be satisfied for a read cycle.
Read-modify-write operation only.
16/
TRG must disable the output buffers prior to applying data to the DQ pins.
17/
Maximum value specified only to guarantee RAS access time.
18/
19/
20/
CAS -before- RAS refresh operation only.
Memory to register (read) transfer cycles only.
In a transfer read cycle, the state of SC when TRG rises is a don't care condition. However, to guarantee proper
sequencing of the internal clock circuitry, there can be no positive transitions of SC for at least 10 ns prior to when TRG
goes high.
21/
In a transfer write cycle, the state of SC when RAS falls is a don't care condition. However, to guarantee proper
22/
23/
sequencing of the internal clock circuitry, there can be no positive transitions of SC for at least 10 ns prior to when RAS
goes low.
Serial data-in cycles only.
Memory to register (read) and register to memory (write) transfer cycles only.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-89497
A
REVISION LEVEL
C
SHEET
15
TABLE IIA. Electrical test requirements. 1/ 2/ 3/ 4/ 5/ 6/ 7/
Line
no.
Test requirements
Subgroups
(in accordance with
MIL-STD-883,
TM 5005, table I)
Device
class M
Subgroups
(in accordance with
MIL-PRF-38535, table III)
Device
class Q
Device
class V
1, 7, 9
1, 7, 9
Not
required
Required
1
Interim electrical
parameters (see 4.2)
2
Static burn-in I and II
(method 1015)
3
Same as line 1
4
Dynamic burn-in
(method 1015)
5
Same as line 1
6
Final electrical
parameters
1*, 2, 3, 7*, 8A,
8B, 9, 10, 11
1*, 2, 3, 7*, 8A,
8B, 9, 10, 11
1*, 2, 3, 7*, 8A,
8B, 9, 10, 11
7
Group A test
requirements
1, 2, 3, 4**, 7,
8A, 8B, 9, 10, 11
1, 2, 3, 4**, 7,
8A, 8B, 9, 10, 11
1, 2, 3, 4**, 7,
8A, 8B, 9, 10, 11
8
Group C end-point
electrical parameters
2, 3, 7,
8A, 8B
2, 3, 7,
8A, 8B ∆
1, 2, 3, 7, 8A,
8B, 9, 10, 11 ∆
9
Group D end-point
electrical parameters
2, 3, 8A, 8B
2, 3, 8A, 8B
2, 3, 8A, 8B
10
Group E end-point
electrical parameters
(see 4.4)
1, 7, 9
1, 7, 9
1, 7, 9
Not
required
1*, 7* ∆
Required
Required
Required
1*, 7* ∆
1/ Blank spaces indicate tests are not applicable.
2/ Any or all subgroups may be combined when using high-speed testers.
3/ Subgroups 7 and 8 functional tests shall verify the functionality for unprogrammed devices or that the altered item
drawing pattern exists for programmed devices.
4/ * indicates PDA applies to subgroup 1 and 7.
5/ ** see 4.4.1e.
6/ ∆ indicates delta limit (see table IIB) shall be required where specified, and the delta values shall be computed with
reference to the previous interim electrical parameters (see line 1).
7/ See 4.4.1d.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-89497
A
REVISION LEVEL
C
SHEET
16
Case T - "J" lead chip carrier
Ltr
Inches
Millimeters
A
.128
.148
3.25
3.76
A1
.055
.075
1.40
1.91
b
.015
.022
0.38
0.56
b1
.015
.019
0.38
0.48
c
.004
.009
0.10
0.23
c1
.004
.006
0.10
0.15
D
.710
.730
18.03
18.54
1.27
1.27
E
e
.435
.050 BSC
.445
11.05
11.30
E1
.405
.415
10.29
10.54
E2
.370 BSC
m
.0002
.0015
.030
.040
N
9.40
9.40
0.005
0.038
0.76
1.01
28
R
Inches
.004
.007
.010
.020
.025
.150
.200
mm
0.10
0.18
0.25
0.51
0.64
3.81
5.08
FIGURE 1. Case outlines.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
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5962-89497
A
REVISION LEVEL
C
SHEET
17
Case X
Inches
Symbol
Min
Millimeters
Max
A
Min
Max
.175
4.45
b
.015
.021
0.38
0.53
b2
.045
.065
1.14
1.65
c
.008
.015
0.20
0.38
D
1.380
1.430
35.05
36.32
E
.380
.410
9.65
10.41
eA
.385
.420
9.79
10.67
e
.100 Nom.
2.54
L
.125
.175
3.18
4.45
Q
.015
.070
0.38
1.78
S
.035
.065
0.89
1.65
NOTE: Configurations A and C as specified in MIL-STD-1835 may be used.
FIGURE 1. Case outlines – Continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-89497
A
REVISION LEVEL
C
SHEET
18
Case Y
Inches
Symbol
Min
Millimeters
Max
Min
Max
A
.080
.101
2.032
2.565
A1
.120
.170
3.048
4.318
b
.016
.023
0.406
0.584
c
.006
.013
0.152
0.330
D
.720
.740
18.288
18.796
D1
.640
.660
16.256
16.764
e
.045
.055
1.143
1.397
eA
.370 Ref.
9.398
E
.408
.422
10.636
10.719
L
.059
.077
1.498
1.778
S
.030
.050
0.762
1.270
R
.025
.035
0.635
0.889
FIGURE 1. Case outlines - Continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-89497
A
REVISION LEVEL
C
SHEET
19
Case Z
28 lead rectangular leadless chip carrier
Inches
Symbol
Millimeters
Inches
Symbol
Millimeters
Min
Max
Min
Max
A
.080
.100
2.03
2.54
e
.050 BSC
1.27
b
.022
.028
0.56
0.71
h
.012 REF
0.30
b1
.006
.022
0.15
0.56
L
.070
.080
1.78
2.03
b2
.040
L1
.090
.110
2.29
2.79
D
.700
.740
17.78
18.80
L2
.003
.015
0.08
0.38
E
.392
.408
9.96
10.36
N
1.02
Min
Max
Min
Max
28 TERMINALS
NOTES:
1. All dimensions are in inches. All dimensioning and tolerance conform to ANSI Y14.5M-1982.
2. Unless otherwise specified, a minimum clearance of .015 inch (0.38 mm) shall be maintained between all metallized
features.
3. Index area: Details of pin 1 identifier are optional, but must be located within the zone indicated.
4. The cover shall not extend beyond the edges of the body.
5. Dimensions b1 and c1 apply to the base metal only. Dimension m applies to the plating/coating thickness.
6. N indicates the number of terminals.
7. A gauge makers tolerance is applied.
FIGURE 1. Case outlines - continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
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APR 97
SIZE
5962-89497
A
REVISION LEVEL
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SHEET
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Case M
│
│
│Symbol │
│
│
│ A1 │
│ A2 │
│ b
│
│ c
│
│ D
│
│ D1 │
│ e
│
│ eA │
│ E
│
│ L
│
│ S
│
Millimeters
Min │ Max
│
0.38 │ 1.27
11.18 │ 11.81
0.41 │ 0.58
0.20 │ 0.39
36.45 │ 37.21
32.77 │ 33.27
2.54 BSC
2.16 │ 2.92
2.54 │ 3.30
3.18 │ 5.08
0.88 │ 1.65
│
Inches
│ Min │ Max
│
│
│ .015
│ .050
│ .440
│ .465
│ .016
│ .023
│ .008
│ .015
│ 1.435 │ 1.465
│ 1.290 │ 1.310
│ .100 BSC
│ .085
│ .115
│ .100
│ .130
│ .125
│ .200
│ .035
│ .065
│
│
│
│
│
│
│
│
│
│
│
│
│
│
Note: The U.S. Government preferred system of measurement is the metric SI system. However, since this item was
originally designed using inch-pound units of measurement, in the event of conflict between the metric and
inch-pound units, the inch-pound units shall take precedence.
FIGURE 1. Case outlines - continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-89497
A
REVISION LEVEL
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SHEET
21
Device types
01, 02, 03, 04
Case
outlines
Terminal
number
M
T, U, X,
Y, Z
Terminal symbol
1
SC
DSF
2
SDQ0
DQ2
3
SDQ1
DQ3
4
TRG
SE
5
DQ0
SDQ2
6
DQ1
SDQ3
7
W
VSS
8
GND
SC
9
RAS
SDQ0
10
A8
SDQ1
11
A6
TRG
12
A5
DQ0
13
A4
DQ1
14
VCC
W
15
A7
NC/GND
16
A3
RAS
17
A2
A8
18
A1
A6
19
A0
A5
20
QSF
A4
21
CAS
VCC
22
DSF
A7
23
DQ2
A3
24
DQ3
A2
25
SE
A1
26
SDQ2
A0
27
SDQ3
QSF
28
VSS
CAS
FIGURE 2. Terminal connections.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
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REVISION LEVEL
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T
y
p
e
RAS fall
CAS
TRG
*
Address
CAS
fall
DSF
W
SE DSF
DQ0 - DQ3
Function
RAS
CAS
RAS
** CAS
W
R
L
X
X
X
X
X
X
X
X
X
C
_A
_S
_ - before - R
_A
_S
_ refresh
T
H
L
L
X
L
X
Row
Addr
Tap
Point
X
X
Register to memory transfer
(Transfer write)
T
H
L
L
H
X
X
Row
Addr
Tap
Point
X
X
Alternate transfer write
(Independent of S
_E
_)
T
H
L
L
L
H
X
Refresh
Addr
Tap
Point
X
X
Serial write-mode enable
(Pseudo-transfer write)
T
H
L
H
L
X
X
Row
Addr
Tap
Point
X
X
Memory to register transfer
(Transfer read)
T
H
L
H
H
X
X
Row
Addr
Tap
Point
X
X
Split register transfer
Read (must reload tap)
R
H
H
L
L
X
L
Row
Addr
Col
Addr
Write
Mask
Valid
Data
Load and use write mask
Write data to dram
R
H
H
L
L
X
H
Row
Addr
Col
A2-A8
Write
Mask
Addr
Mask
Load and use write mask
Block write to dram
R
H
H
L
H
X
L
Row
Addr
Col
Addr
X
Valid
Data
Persistent write - per - bit
Write data to dram
R
H
H
L
H
X
H
Row
Addr
Col
A2-A8
X
Addr
Mask
Persistent write - per - bit
Block write to dram
R
H
H
H
L
X
L
Row
Addr
Col
Addr
X
Valid
Data
Normal dram read/write
(Nonmasked)
R
H
H
H
L
X
H
Row
Addr
Col
A2-A8
X
Addr
Mask
Block write to dram
(Nonmasked)
R
H
H
H
H
X
L
Refresh
Addr
X
X
Write
Mask
Load write mask
R
H
H
H
H
X
H
Refresh
Addr
X
X
Color
Mask
Load color register
R = Random access operation
T = Transfer operation
X = Don't care
NOTES:
* Addr mask = 1 write to address location enabled.
Write mask = 1 write to I/O enabled.
In persistent write-per-bit function, W must be high during the refresh cycles.
** DQ0-3 are latched on the later of W or CAS falling edge.
FIGURE 3. Truth tables
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
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REVISION LEVEL
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23
Transfer operation logic ***
TRG
W
SE
DSF
Mode
L
L
L
L
L
L
L
L
H
H
L
X
H
X
X
X
H
L
L
H
Register to memory (write) transfer (serial write mode enable)
Alternate register to memory transfer
Serial write mode enable (pseudo write transfer)
Memory to register (read) transfer
Split register read transfer
H = High voltage level
L = Low voltage level
X = Don't care
R = Random access operation
T = Transfer operation
Serial operation logic
Last transfer cycle
Alternate register to memory
Serial write mode enable ****
Serial write mode enable ****
Memory to register
Memory to register
SE
H
L
H
L
H
SDQ
Input disabled
Input enable
Input disabled
Output enabled
HI - Z
H = High voltage level
L = Low voltage level
X = Don't care
R = Random access operation
T = Transfer operation
NOTES:
*** Above logic states are assumed valid on the falling edge of RAS .
**** Pseudo transfer write.
FIGURE 3. Truth tables - continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
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SIZE
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REVISION LEVEL
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FIGURE 4. Timing waveform diagrams.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
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A
REVISION LEVEL
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SHEET
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NOTE: See "write cycle state" table (of figure 4) for the logic state of "1", "2", "3", "4", and "5".
FIGURE 4. Timing waveform diagrams - Continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
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NOTE: See "write cycle state" table (of figure 4) for the logic state of "1", "2", "3", "4", and "5".
FIGURE 4. Timing waveform diagrams - Continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
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Write cycle state table
│
│
│
Cycle
│
│
│ Write mask load/use write DQs to I/Os
│
│
│ Write mask load/use block write
│
│
│ Use previous write mask, write DQs to I/Os
│
│
│ Use previous write mask, block write
│
│
│ Load write mask on later of W fall and CAS fall
│
│
│ Load color register on later of W fall and CAS fall
│
│
│ Write mask disabled, block write to all I/Os
│
│
│ Normal early or late write operation
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
State
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
1
L
L
H
H
│
│
│
H
│
│
│
│
│
│
│
│
H
L
L
2
L
H
L
H
L
H
H
L
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
3
L
L
L
L
4
Write
mask
Write
mask
Don't
care
Don't
care
Don't
│ care
│
│ Don't
H
│
│
│
│
│
│
│
│
H
H
H
care
Don't
care
Don't
care
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
5
Valid
date
ADDR
mask
Valid
data
ADDR
mask
Write
│ mask
│
│ Color
│
│
│
│
│
│
│
│
data
ADDR
mask
Valid
data
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
FIGURE 4. Timing waveform diagrams - Continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
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REVISION LEVEL
C
SHEET
28
NOTES:
1. See "write cycle state" table (of figure 4) for the logic state of "1", "2", "3", "4", and "5".
2. Same logic as delayed write cycle.
FIGURE 4. Timing waveform diagrams - Continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
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NOTES:
1. Access time is ta(CP) or ta(CA) dependent.
2. Output may go from high impedance state to an invalid state prior to the specified access time.
3. A write cycle or a read-modify-write cycle can be mixed with read cycles as long as the write and read-modify-write
timing specifications are not violated and the proper polarity of DSF is selected on the falling edges of RAS and
CAS to select the desired write mode (normal, block write, etc.).
FIGURE 4. Timing waveform diagrams - Continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
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APR 97
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NOTES:
1. Referenced to CAS or W , whichever occurs last.
2. See "write cycle state" table (of figure 4) for the logic state of "1", "2", "3", "4", and "5".
3. A read cycle or a read-modify-write cycle can be intermixed with write cycles, observing read and read-modify-write
timing specifications. TRG must remain high throughout the entire page-mode operation if the late write feature is
used, to guarantee page-mode cycle time. If the early write cycle timing is used, the state of TRG is don't care after
the minimum
period th(TRG) from the falling edge of RAS .
FIGURE 4. Timing waveform diagrams - Continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
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DSCC FORM 2234
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REVISION LEVEL
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NOTES:
1. Output may go from the high impedance state to an invalid data state prior to the specified access time.
2. See "write cycle state" table (of figure 4) for the logic state of "1", "2", "3", "4", and "5".
3. A read or a write cycle can be intermixed with read-modify-write cycles as long as the read and write timing
specifications are not violated.
FIGURE 4. Timing waveform diagrams - Continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-89497
A
REVISION LEVEL
C
SHEET
32
FIGURE 4. Timing waveform diagrams - Continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
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FIGURE 4. Timing waveform diagrams - Continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
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A
REVISION LEVEL
C
SHEET
34
FIGURE 4. Timing waveform diagrams - Continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-89497
A
REVISION LEVEL
C
SHEET
35
FIGURE 4. Timing waveform diagrams - Continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
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NOTES:
1. Random-mode Q outputs remain in the high-impedance state for the entire write-mode control.
2. SE must be high as RAS falls in order to perform a write-mode control cycle.
FIGURE 4. Timing waveform diagrams - Continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
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NOTES:
1. Random mode Q outputs remain in the high impedance state for the entire data register to memory transfer cycle. This
cycle is used to transfer data from the data register to the memory array. Every one of the 512 locations in each data
register is written into the corresponding 512 columns of the selected row. Data in the data register may proceed from a
serial shift-in or from a parallel load from one of the memory array rows. The above diagram assumes that the device is
in the serial write mode (i.e., SD is enabled by a previous write mode control cycle, thus allowing data to be shifted-in).
2. Successive transfer writes can be performed without serial clocks for applications requiring fast memory array clears.
FIGURE 4. Timing waveform diagrams - Continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
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Register transfer function table
│
│
Function
│
│
│
│ Register to memory transfer
│
│
│ Register to memory transfer, alternate
│ transfer write
│
│
│ Pseudo-transfer SDQ control, serial
│ input enabled
│
│
│ Memory to register transfer
│
│
│ Split register transfer
│
│
│
│
│ TRG
│
│ L
│
│
│ L
│
│
│
│ L
│
│
│
│ L
│
│
│ L
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
RAS fall
│
W
│ DSF (1)
│
L
│ H
│
│
L
│ H
│
│
│
L
│ L
│
│
│
H
│ L
│
│
H
│ H
│
│
│ SE (3)
│
│ L
│
│
│ X
│
│
│
│ H
│
│
│
│ X
│
│
│ X
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
FIGURE 4. Timing waveform diagrams - Continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-89497
A
REVISION LEVEL
C
SHEET
39
FIGURE 4. Timing waveform diagrams - Continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-89497
A
REVISION LEVEL
C
SHEET
40
NOTE:
Random mode (Q outputs) remains in the high-impedance state for the entire memory to data register transfer cycle.
The memory to data register transfer cycle is used to load the data registers in parallel from the memory array. The
512 locations in each data register are written into from the 512 corresponding columns of the selected row. The data
that is transferred into the data registers may be either shifted out or transferred back into another row. Once data is
transferred into the data registers, the SAM is in the serial read mode (i.e., the SQ is enabled), thus allowing data to be
shifted out of the registers. Also, the first bit to be read from the data register after TRG has gone high must be
activated by a positive transition of SC.
FIGURE 4. Timing waveform diagrams - Continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-89497
A
REVISION LEVEL
C
SHEET
41
NOTE: When the odd tap is used (tap addresses can be 0-511, and odd taps are 1, 3, 5... etc.), the cycle time for SC in
the first serial data out cycle needs to be 70 ns minimum.
FIGURE 4. Timing waveform diagrams - Continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-89497
A
REVISION LEVEL
C
SHEET
42
NOTE: For part numbers 01 and 02, QSF pin is open collector which requires 5 V with an 820 Ω pull-up resistor
FIGURE 5. Load circuit.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-89497
A
REVISION LEVEL
C
SHEET
43
TABLE IIB. Delta limits at +25°C.
Parameter 1/
Device types
All
ICC2 standby
±1.5 mA of specified
value in Table I
IIL
±1.5 mA of specified
value in Table I
IO
±1.5 mA of specified
value in Table I
1/ The above parameter shall be recorded
before and after the required burn-in and
life tests to determine the delta.
4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in
accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a.
Delete the sequence specified as initial (preburn-in) electrical parameters through interim (postburn-in)
electrical parameters of method 5004 and substitute lines 1 through 6 of table IIA herein.
b.
The test circuit shall be maintained by the manufacturer under document revision level control and shall be made
available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases,
and power dissipation, as applicable, in accordance with the intent specified in method 1015.
(1) Dynamic burn-in for device class M (method 1015 of MIL-STD-883, test condition D; for circuit, see 4.2.1b herein).
c.
Interim and final electrical test parameters shall be as specified in table IIA herein.
4.2.2 Additional criteria for device classes Q and V.
a.
The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with MILPRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
c.
Additional screening for device class V beyond the requirements of device class Q shall be as specified in appendix B
of MIL-PRF-38535.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-89497
A
REVISION LEVEL
C
SHEET
44
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with MIL-PRF38535 including groups A, B, C, D, and E inspections and as specified herein except where option 2 of MIL-PRF-38535 permits
alternate in-line control testing. Quality conformance inspection for device class M shall be in accordance with MIL-STD-883
(see 3.1 herein) and as specified herein. Inspections to be performed for device class M shall be those specified in method
5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4.1 Group A inspection.
a. Tests shall be as specified in table IIA herein.
b. Subgroups 5 and 6 of Table I of method 5005 of MIL-STD-883 shall be omitted.
c. For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table. For device classes Q and V,
subgroups 7 and 8 shall include verifying the functionality of the device.
d. O/V (latch-up) tests shall be measured only for initial qualification and after any design or process changes which may
affect the performance of the device. For device class M, procedures and circuits shall be maintained under document
revision level control by the manufacturer and shall be made available to the preparing activity or acquiring activity upon
request. For device classes Q and V, the procedures and circuits shall be under the control of the device manufacturer's
TRB in accordance with MIL-PRF-38535 and shall be made available to the preparing activity or acquiring activity upon
request. Testing shall be on all pins, on five devices with zero failures. Latch-up test shall be considered destructive.
Information contained in JESD78 may be used for reference.
e. Subgroup 4 (CIN and COUT measurements) shall be measured only for initial qualification and after any process or design
changes which may affect input or output capacitance. Capacitance shall be measured between the designated terminal
and GND at a frequency of 1 MHz. Sample size is 15 devices with no failures, and all input and output terminals tested.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a. Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control and
shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs,
outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005.
b. TA = +125°C, minimum.
c. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB, in accordance with MILPRF-38535, and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MILSTD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein). RHA levels for device classes Q and V shall be M, D, R, and H and for device class M shall be M and D.
a.
End-point electrical parameters shall be as specified in table IIA herein.
b. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to
radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device
classes must meet the postirradiation end-point electrical parameter limits as defined in table IA at TA = +25°C ±5°C,
after exposure, to the subgroups specified in table IIA herein.
4.5 Delta measurements for device classes Q and V. Delta measurements, as specified in table IIA, shall be made and
recorded before and after the required burn-in screens and steady-state life tests to determine delta compliance. The electrical
parameters to be measured, with associated delta limits are listed in table IIB. The device manufacturer may, at his option,
either perform delta measurements or within 24 hours after burn-in perform final electrical parameter tests, subgroups 1, 7,
and 9.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-89497
A
REVISION LEVEL
C
SHEET
45
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor
prepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform DLA Land and Maritime when a system application requires
configuration control and which SMD's are applicable to that system. DLA Land and Maritime will maintain a record of users and
this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic
devices (FSC 5962) should contact DLA Land and Maritime-VA, telephone (614) 692-8108.
6.4 Comments. Comments on this drawing should be directed to DLA Land and Maritime-VA, Columbus, Ohio 43218-3990,
or telephone (614) 692-0540.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-PRF38535 and MIL-HDBK-1331, and as follows:
CI CO -------------------------------------------GND --------------------------------------------ICC ----------------------------------------------IIL -----------------------------------------------IIH -----------------------------------------------TC ----------------------------------------------TA -----------------------------------------------VCC ----------------------------------------------VIC ---------------------------------------------------------------------O/V ---------------------------------------------O/I------------------------------------------------
Input and bidirectional output, terminal-to-GND capacitance.
Ground zero voltage potential.
Supply current.
Input current low
Input current high
Case temperature.
Ambient temperature
Positive supply voltage.
Positive input clamp voltage
Latch-up over-voltage
Latch-up over-current
6.5.1 Timing limits. The table of timing values shows either a minimum or a maximum limit for each parameter. Input
requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the
system must supply at least that much time (even though most devices do not require it). On the other hand, responses from
the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never
provides data later than that time.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
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REVISION LEVEL
C
SHEET
46
6.5.2 Waveforms.
Waveform
symbol
Input
Output
MUST BE
VALID
WILL BE
VALID
CHANGE FROM
H TO L
WILL CHANGE
FROM
H TO L
CHANGE FROM
L TO H
WILL CHANGE
FROM
L TO H
DON'T CARE
ANY CHANGE
PERMITTED
CHANGING
STATE
UNKNOWN
HIGH
IMPEDANCE
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535
and MIL-HDBK-103. The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DLA Land
and Maritime-VA and have agreed to this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DLA Land and Maritime-VA.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-89497
A
REVISION LEVEL
C
SHEET
47
APPENDIX A
Appendix A forms a part of SMD 5962-89497
FUNCTIONAL ALGORITHMS
A10. SCOPE
A10.1 Scope. Functional algorithms are test patterns which define the exact sequence of events used to verify proper
operation of a Random Access Memory (RAM). Each algorithm serves a specific purpose for the testing of the device. It is
understood that all manufacturers do not have the same test equipment; therefore, it becomes the responsibility of each
manufacturer to guarantee that the test patterns described herein are followed as closely as possible, or equivalent patterns be
used that serve the same purpose. Each manufacturer should demonstrate that this condition will be met. Algorithms shall be
applied to the device in a topologically pure fashion. This appendix is a mandatory part of the specification. The information
contained herein is intended for compliance.
A20. APPLICABLE DOCUMENTS. This section is not applicable to this appendix.
A30. ALGORITHMS
A30.1 Algorithm A (pattern 1).
A30.1.1 Output high impedance (toff). This pattern verifies the output buffer switches to high impedance (three-state) within
the specified tOFF after the rise of CAS . It is performed in the following manner.
Step 1: Perform 8 pump cycles.
Step 2: Load address location with data.
Step 3: Raise CAS and read address location and guarantee VOL < VOUT < VOH after TOFF delay.
A30.2 Algorithm B (pattern 2).
A30.2.1 VCC slew. This pattern indicates sense amplifier margin by slewing the supply voltage between memory
writing and reading. It is performed in the following manner:
Step 1:
Step 2:
Step 3:
Step 4:
Step 5:
Step 6:
Step 7:
Perform 8 pump cycles, 1 memory to register transfer and 2 SC cycles.
Load memory with background data with VCC at 5.0 V.
Change VCC to 5.5 V.
Read memory with background data.
Load memory with background data complement.
Change VCC to 4.5 V.
Read memory with background data complement.
A30.3 Algorithm C (pattern 3).
A30.3.1
manner:
March data. This pattern tests for address uniqueness and multiple selection. It is performed in the following
Step 1: Perform 8 pump cycles, 1 memory to register transfer and 2 SC cycles.
Step 2: Load memory with background data.
Step 3: Read location 0.
Step 4: Write data complement in location 0.
Step 5: Repeat steps 3 and 4 for all other locations in the memory (sequentially).
Step 6: Read data complement in maximum address location.
Step 7: Write data in maximum address location.
Step 8: Repeat steps 6 and 7 for all other locations in the memory from maximum to minimum address.
Step 9: Read data in maximum address location.
Step 10: Write data complement in maximum address location.
Step 11: Repeat steps 6 and 7 for all other locations in the memory from maximum to minimum address.
Step 12: Read memory with data complement.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-89497
A
REVISION LEVEL
C
SHEET
48
APPENDIX A – continued.
A30.4 Algorithm D (pattern 4).
A30.4.1 Refresh test (cell retention) +125°C only. This test is used to check the retention time of the memory cells. It is
performed in the following manner:
Step 1:
Step 2:
Step 3:
Step 4:
Step 5:
Perform 8 pump cycles.
Load memory with background data.
Pause TREF (stop all clocks).
Read memory with background data.
Repeat steps 2, 3, and 4 with data complement.
A30.5 Algorithm E (pattern 5).
A30.5.1 Read-modify-write (RMW). This pattern verifies the read-modify-write mode for the memory. It is performed in the
following manner:
Step 1:
Step 2:
Step 3:
Step 4:
Step 5:
Step 6:
Perform 8 pump cycles, 1 memory to register transfer and 2 SC cycles.
Load memory with background data.
Read minimum address location with data and load with data complement using RMW cycle.
Repeat step 3 for all address locations (sequentially).
Read maximum address location with data complement and load with data using RMW cycle.
Repeat step 5 for all address locations from maximum to minimum.
A30.6 Algorithm F (pattern 6).
A30.6.1 Page mode. This pattern verifies the Page mode for the memory. It is performed in the following manner:
Step 1:
Step 2:
Step 3:
Step 4:
Step 5:
Step 6:
Perform 8 pump cycles, 1 memory to register transfer and 2 SC cycles.
Load first page of memory with background data using page mode cycle.
Repeat step 2 for remaining rows.
Read first page of memory with data and load with data complement using page mode cycle.
Repeat step 4 for remaining rows.
Read first page of memory with data complement and write data starting at maximum Y address and
decrementing Y address.
Step 7: Repeat step 6 for remaining rows.
A30.7 Algorithm G (pattern 7).
A30.7.1 CAS-before-RAS counter test. This test is used to verify the functionality of the CAS before RAS internal address
counter.
Step 1:
Step 2:
Step 3:
Step 4:
Step 5:
Step 6:
Perform 8 pump cycles, 1 memory to register transfer and 2 SC cycles.
Write data to one column of memory.
Perform 512 CBR cycles presenting data complement, but not changing the address presented.
Read data complement from the column written to in step 2.
Perform 512 CBR cycles presenting data, but not changing the address presented.
Read data from the column written to in step 2.
A30.8 Algorithm H (pattern 8).
A30.8.1 Memory to register test. This test is used to verify the functionality of the memory to register transfer circuitry.
Step 1:
Step 2:
Step 3:
Step 4:
Step 5:
Step 6:
Perform 8 pump cycles, 1 memory to register transfer and 2 SC cycles.
Write one row of data to the memory.
Transfer this row to the serial register.
Read data out of the serial register.
Repeat steps 2 through 4 with data complement.
Repeat steps 2 through 5 for the remaining rows.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-89497
A
REVISION LEVEL
C
SHEET
49
APPENDIX A – continued.
A30.9 Algorithm I (pattern 9).
A30.9.1
circuitry.
Register to memory transfer test. This test is used to verify the functionality of the register to memory transfer
Step 1:
Step 2:
Step 3:
Step 4:
Step 5:
Step 6:
Step 7:
Perform 8 pump cycles, 1 memory to register transfer and 2 SC cycles.
Write one row of data complement to memory.
Transfer this row to the serial register.
Write entire memory array with data.
Transfer serial register to first row of memory.
Repeat step 5 for remaining rows of memory.
Read data complement for entire memory array.
A30.10 Algorithm J (pattern 10).
A30.10.1 Serial input test. This test is used to verify the functionality of the serial input circuitry.
Step 1:
Step 2:
Step 3:
Step 4:
Step 5:
Step 6:
Step 7:
Step 8:
Perform 8 pump cycles, 1 memory to register transfer and 2 SC cycles.
Write entire memory array with data.
Transfer the first row of memory to the serial register.
Perform a pseudo transfer write cycle.
Shift one row of data complement into serial register.
Transfer serial register to first memory row.
Repeat steps 5 through 6 until entire memory array is written to.
Read data complement from entire array.
A30.11 Algorithm K (pattern 11).
A30.11.1 Serial output test. This test is used to verify the functionality of the serial output and tap circuitry.
Step 1:
Step 2:
Step 3:
Step 4:
Step 5:
Step 6:
Step 7:
Step 8:
Perform 8 pump cycles, 1 memory to register transfer and 2 SC cycles.
Write one row of data into memory array.
Write data complement into tap point.
Perform memory to register transfer on row written to.
Read data complement from tap point.
Read data for all bits beyond tap point.
Increment tap point.
Repeat steps 2 through 7 511 times.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-89497
A
REVISION LEVEL
C
SHEET
50
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 14-01-27
Approved sources of supply for SMD 5962-89497 are listed below for immediate acquisition information only and shall be
added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to
include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of
compliance has been submitted to and accepted by DLA Land and Maritime-VA. This information bulletin is superseded
by the next dated revision of MIL-HDBK-103 and QML-38535. DLA Land and Maritime maintains an online database of all
current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
5962-8949701MTA
3/
5962-8949701MUA
3/
5962-8949701MXA
3/
5962-8949701MYA
3/
5962-8949701MZA
3/
5962-8949702MTA
3/
5962-8949702MUA
3/
5962-8949702MXA
3/
5962-8949702MYA
3/
5962-8949702MZA
3/
5962-8949703MMA
57300
MT42C4256CZ-12/883C
5962-8949703MMA
57300
SMJ44C251B-12SVM
5962-8949703MTA
57300
MT42C4256DCJ-12/883C
5962-8949703MUA
57300
MT42C4256F-12/883C
5962-8949703MXA
57300
SMJ44C251B-12JDM
5962-8949703MXA
57300
MT42C4256C-12/883C
5962-8949703MYA
57300
SMJ44C251B-12HJM
5962-8949703MZA
57300
SMJ44C251B-12HMM
5962-8949703MZA
57300
MT42C4256EC-12/883C
5962-8949704MMA
57300
MT42C4256CZ-10/883C
5962-8949704MMA
57300
SMJ44C251B-10SVM
See notes at end of table.
Page 1 of 2
Vendor
similar
PIN 2/
STANDARD MICROCIRCUIT DRAWING BULLETIN – Continued.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 3/
5962-8949704MTA
57300
MT42C4256DCJ-10/883C
5962-8949704MUA
57300
MT42C4256F-10/883C
5962-8949704MXA
57300
SMJ44C251B-10JDM
5962-8949704MXA
57300
MT42C4256C-10/883C
5962-8949704MYA
57300
SMJ44C251B-10HJM
5962-8949704MZA
57300
SMJ44C251B-10HMM
5962-8949704MZA
57300
MT42C4256EC-10/883C
1/ The lead finish shown for each PIN representing a hermetic package
is the most readily available from the manufacturer listed for that
part. If the desired lead finish is not listed contact the vendor to
determine its availability.
2/ Caution. Do not use this number for item acquisition. Items
acquired to this number may not satisfy the performance requirements
of this drawing.
3/ Not available from an approved source.
Vendor CAGE
number
Vendor name
and address
57300
Micross Components
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
The information contained herein is disseminated for convenience only and
the Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.
Page 2 of 2