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TSL1410R
1280 × 1 Linear Sensor Array with Hold
General Description
The TSL1410R linear sensor array consists of two sections of 640
photodiodes, each with associated charge amplifier circuitry,
aligned to form a contiguous 1280 × 1 pixel array. The device
incorporates a pixel data-hold function that provides
simultaneous-integration start and stop times for all pixels. The
pixels measure 63.5μm by 55.5μm with 63.5μm
center-to-center spacing and 8μm spacing between pixels.
Operation is simplified by internal logic that requires only a
serial-input (SI) pulse and a clock.
The device is intended for use in a wide variety of applications
including mark and code reading, OCR and contact imaging,
edge detection and positioning, and optical encoding.
Ordering Information and Content Guide appear at end of
datasheet.
Key Benefits & Features
The benefits and features of the TSL1410R Linear Sensor Array
with Hold, are listed below:
Figure 1:
Added Value of Using TSL1410R
Benefits
Features
• Provides High Density Pixel Count
• 1280 x 1 Sensor-Element Organization
• Enables High Resolution Scanning
• 400 Dots-Per-Inch (DPI) Sensor Pitch
• Enables Capacitive Threshold Sensing
• High Linearity and Uniformity
• Provides Full Dynamic Range
• Rail-to-Rail Output Swing (AO)
• Wide Dynamic Range... 4000:1 (72dB)
• Output Referenced to Ground
• Low Image Lag... 0.5% Typ
• Operation to 8MHz
• Single 3V to 5V Supply
• No External Load Resistor Required
• Replacement for TSL1410
ams Datasheet
[v1-00] 2016-May-13
Page 1
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TSL1410R − General Description
Block Diagram
The functional blocks of this device are shown below:
Figure 2:
TSL1410R Block Diagram
Pixel 1
(641)
Pixel
2
(642)
1 Integrator
Reset
2
S1
_
Pixel
3
(643)
Analog
Bus
2
1
13
Pixel
640
(1280)
3
Output
Buffer
V DD
6, 12
AO
+
S2
Sample/Hold/
Output
5
Gain
Trim
Switch Control Logic
7, 11
3, 9
Hold
CLK
Hold
4, 10
Q1
Q2
GND
Q3
SO
Q640 (Q1280)
6 4 0 -B i t S h i f t R e g i s te r ( 2 e a c h )
2, 8
SI
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ams Datasheet
[v1-00] 2016-May-13
TSL1410R − Detailed Description
Detailed Description
The sensor consists of 1280 photodiodes, called pixels,
arranged in a linear array. Light energy impinging on a pixel
generates photocurrent that is then integrated by the active
integration circuitry associated with that pixel.
During the integration period, a sampling capacitor connects
to the output of the integrator through an analog switch. The
amount of charge accumulated at each pixel is directly
proportional to the light intensity on that pixel and the
integration time.
The output and reset of the integrators are controlled by a
640-bit shift register and reset logic. An output cycle is initiated
by clocking in a logic 1 on SI. Another signal, called HOLD, is
generated from the rising edge of SI1 when SI1 and HOLD1 are
connected together. This causes all 640 sampling capacitors to
be disconnected from their respective integrators and starts an
integrator reset period. As the SI pulse is clocked through the
shift register, the charge stored on the sampling capacitors is
sequentially connected to a charge-coupled output amplifier
that generates a voltage on analog output AO. The integrator
reset period ends 18 clock cycles after the SI pulse is clocked in.
Then the next integration period begins. On the 640 th clock
rising edge, the SI pulse is clocked out on the SO1 pin
(section 1) and becomes the SI pulse for section 2 (when SO1
is connected to SI2). The rising edge of the 641 st clock cycle
terminates the SO1 pulse, and returns the analog output AO of
section 1 to high-impedance state. Similarly, SO2 is clocked out
on the 1280 th clock pulse. Note that a 1281 st clock pulse is
needed to terminate the SO2 pulse and return AO of Section 2
to the high-impedance state. If a minimum integration time is
desired, the next SI pulse may be presented after a minimum
delay of tqt (pixel charge transfer time) after the 1281st clock
pulse. Sections 1 and 2 may be operated in parallel or in serial
fashion.
AO is an op amp-type output that does not require an external
pull-down resistor. This design allows a rail-to-rail output
voltage swing. With V DD = 5V, the output is nominally 0V for no
light input, 2V for normal white level, and 4.8V for saturation
light level. When the device is not in the output phase, AO is in
a high-impedance state.
ams Datasheet
[v1-00] 2016-May-13
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TSL1410R − Detailed Description
The voltage developed at analog output (AO) is given by:
Vout = Vdrk + (Re) (Ee) (t int)
where:
• V out is the analog output voltage for white condition
• V drk is the analog output voltage for dark condition
• R e is the device responsivity for a given wavelength of
light given in V/(μJ/cm2)
• E e is the incident irradiance in μW/cm 2
• t int is integration time in seconds
A 0.1μF bypass capacitor should be connected between VDD
and ground as close as possible to the device.
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ams Datasheet
[v1-00] 2016-May-13
TSL1410R − Pin Assignments
Pin Assignments
The TSL1410R pin assignments are described below:
Figure 3:
Pin Diagram of TSL1410R Package (Top View)
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
ams Datasheet
[v1-00] 2016-May-13
VPP
SI1
HOLD1
CLK1
GND
AO1
SO1
SI2
HOLD2
CLK2
SO2
AO2
VDD
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TSL1410R − Pin Assignments
Figure 4:
Terminal Functions
Terminal
I/O
Description
Name
No.
VPP
1
SI1
2
I
Serial input (section 1). SI1 defines the start of the data-out
sequence.
HOLD1
3
I
Hold signal. HOLD1 shifts pixel data to parallel buffer. HOLD1 is
normally connected to SI1 and HOLD2 in serial mode and to SI1 in
parallel mode.
CLK1
4
I
Clock, section 1. CLK1 controls charge transfer, pixel output, and
reset.
GND
5
AO1
6
O
Analog output, section 1
SO1
7
O
Serial output (section 1). SO1 provides a signal to drive the SI2 input
in serial mode.
SI2
8
I
Serial input (section 2). SI2 defines the start of the data-out
sequence.
HOLD2
9
I
Hold signal. HOLD2 shifts pixel data to parallel buffer. HOLD2 is
normally connected to SI2 in parallel mode.
CLK2
10
I
Clock, section 2. CLK2 controls charge transfer, pixel output, and
reset.
SO2
11
O
Serial output (section 2). SO2 provides a signal to drive the SI input
of another device for cascading or as an end-of-data indication.
AO2
12
O
Analog output, section 2
VDD
13
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Normally grounded
Ground (substrate). All voltages are referenced to GND.
Supply voltage for both analog and digital circuitry.
ams Datasheet
[v1-00] 2016-May-13
TSL1410R − Absolute Maximum Ratings
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. These are stress
ratings only. Functional operation of the device at these or any
other conditions beyond those indicated under Recommended
Operating Conditions is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Absolute Maximum Ratings
Figure 5:
Absolute Maximum Ratings over Operating Free-Air Temperature Range (unless otherwise noted)
Symbol
Min
Max
Unit
Supply voltage range
-0.3
6
V
VI
Input voltage range
-0.3
VDD + 0.3V
V
IIK
Input clamp current, (VI < 0) or (VI > VDD)
-20
20
mA
IOK
Output clamp current, (VO < 0) or (VO > VDD)
-25
25
mA
VO
Voltage range applied to any output in the high impedance or
power-off state
-0.3
VDD + 0.3V
V
IO
Continuous output current, (VO = 0 to VDD)
-25
25
mA
Continuous current through VDD or GND
-40
40
mA
Analog output current range
-25
25
mA
5
mJ/cm2
VDD
IO
Parameter
Maximum light exposure at 638nm
TA
Tstrg
Operating free-air temperature range
-25
85
°C
Storage temperature range
-25
85
°C
260
°C
Lead temperature 1.6mm (1/16 inch) from case for 10 seconds
ams Datasheet
[v1-00] 2016-May-13
Page 7
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TSL1410R − Electrical Characteristics
Electrical Characteristics
All limits are guaranteed. The parameters with min and max
values are guaranteed with production tests or
SQC (Statistical Quality Control) methods.
Figure 6:
Recommended Operating Conditions
Symbol
Min
Nom
Max
Unit
Supply voltage
3
5
5.5
V
VI
Input voltage
0
VDD
V
VIH
High-level input voltage
VDD × 0.7
VDD
V
VIL
Low-level input voltage
0
VDD × 0.3
V
400
1100
nm
5
8000
kHz
VDD
λ
fclock
Parameter
Wavelength of light source
Clock frequency
tint
Sensor integration time, serial (1)
0.17775
100
ms
tint
Sensor integration time, parallel (1)
0.09775
100
ms
tsu(SI)
Setup time, serial input
20
ns
th(SI)
Hold time, serial input (2)
0
ns
TA
Operating free-air temperature
0
CL
Load capacitance
RL
Load resistance
300
70
°C
330
pF
Ω
Note(s):
1. Integration time is calculated as follows:
tint(min) = (1280 - 18) x clock period + 20μs
where 1280 is the number of pixels in series, 18 is the required logic setup clocks, and 20μs is the pixel charge transfer time (t qt)
2. SI must go low before the rising edge of the next clock pulse.
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ams Datasheet
[v1-00] 2016-May-13
TSL1410R − Electrical Characteristics
Figure 7:
Electrical Characteristics at fclock = 1MHz, VDD = 5V, TA = 25°C, λp = 640nm, tint = 5ms, RL = 330Ω,
Ee = 12.5μW/cm 2 (unless otherwise noted) (1)
Symbol
Parameter
Test
Conditions
Min
Typ
Max
Unit
1.6
2
2.4
V
0
0.1
0.3
V
Vout
Analog output voltage
(white, average over 1280 pixels)
See note (2)
Vdrk
Analog output voltage
(dark, average over 1280 pixels)
Ee = 0
Pixel response nonuniformity
See note (3)
Nonlinearity of analog output
voltage
See note (4)
±0.4%
Output noise voltage
See note (5)
1
Responsivity
See note (6)
20
30
VDD = 5V,
RL = 330Ω
4.5
4.8
PRNU
Re
Vsat
IDD
2.5
155
nJ/cm2
(7)
90
Dark signal nonuniformity
All pixels, Ee = 0 (8)
0.05
Image lag
See note (9)
0.5%
0.15
VDD = 5V, Ee = 0
30
45
VDD = 3V, Ee = 0
25
40
Supply current
ams Datasheet
[v1-00] 2016-May-13
V/
(μJ/cm2)
2.8
Saturation exposure
VDD = 3V
IL
38
V
VDD = 5V (7)
DSNU
mVrms
Analog output saturation voltage
VDD = 3V,
RL = 330Ω
SE
±20%
V
mA
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TSL1410R − Electrical Characteristics
Symbol
Parameter
Test
Conditions
Min
Typ
Max
Unit
IIH
High-level input current
VI = VDD
10
μA
IIL
Low-level input current
VI = 0
10
μA
Ci
Input capacitance, SI
25
pF
Ci
Input capacitance, CLK
25
pF
Note(s):
1. All measurements made with a 0.1μF capacitor connected between V DD and ground.
2. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640nm.
3. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the
device under test when the array is uniformly illuminated at the white irradiance level. PRNU includes DSNU.
4. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent
of analog output voltage (white).
5. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period.
6. R e(min) = [Vout(min) - Vdrk(max)] ÷ (Ee × tint)
7. SE (min) = [Vsat(min) - Vdrk(min)] × (Ee × tint) ÷ [Vout(max) - Vdrk(min)]
8. DSNU is the difference between the maximum and minimum output voltage for all pixels in the absence of illumination.
9. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after
a pixel is exposed to a white condition followed by a dark condition:
V out ( IL ) – V drk
IL = -------------------------------------------- × 100
V out ( white ) – V drk
Page 10
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ams Datasheet
[v1-00] 2016-May-13
TSL1410R − Electrical Characteristics
Figure 8:
Timing Requirements (see Figure 10 and Figure 11)
Symbol
Parameter
Min
Nom
Max
Unit
tsu(SI)
Setup time, serial input (1)
20
ns
th(SI)
Hold time, serial input (1), (2)
0
ns
tpd(SO)
Propagation delay time, SO
50
tw
Pulse duration, clock high or low
50
tr , tf
Input transition (rise and fall) time
0
Pixel charge transfer time
20
tqt
ns
ns
500
ns
μs
Note(s):
1. Input pulses have the following characteristics: tr = 6ns, t f = 6ns.
2. SI must go low before the rising edge of the next clock pulse.
Figure 9:
Dynamic Characteristics over Recommended Ranges of Supply Voltage and Operating Free-Air
Temperature (see Figure 16 and Figure 17)
Symbol
Parameter
ts
Analog output settling time to ±1%
tpd(SO)
Propagation delay time, SO1, SO2
ams Datasheet
[v1-00] 2016-May-13
Test Conditions
RL = 330Ω, CL = 50pF
Min
Typ
Max
Unit
120
ns
50
ns
Page 11
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TSL1410R − Typical Characteristics
Typical Characteristics
Figure 10:
Timing Waveforms (Serial Connection)
CLK
tqt
SI1
Internal
Reset
Integration
18 Clock Cycles
tint
Not Integrating
Integrating
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
1281 Clock Cycles
AO
Hi-Z
Hi-Z
Figure 11:
Operational Waveforms (Each Section)
tw
1
2
640
641
5V
2.5 V
CLK
0V
tsu(SI)
5V
SI
50%
0V
th(SI)
tpd(SO)
tpd(SO)
SO
ts
AO
Page 12
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Pixel 1
Pixel 640
ams Datasheet
[v1-00] 2016-May-13
TSL1410R − Typical Characteristics
Figure 12:
Photodiode Spectral Responsivity
1
TA = 25qC
Relative Responsivity
0.8
0.6
0.4
0.2
0
300
400
500
600
700
800
900
1000 1100
O ï Wavelength ï nm
Figure 13:
Normalized Idle Supply Current vs. Free-Air Temperature
IDD — Normalized Idle Supply Current
2
1.5
1
0.5
0
0
10
20
30
40
50
60
70
TA ï Free-Air Temperature ï qC
ams Datasheet
[v1-00] 2016-May-13
Page 13
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TSL1410R − Typical Characteristics
Figure 14:
White Output Voltage vs. Free-Air Temperature
2
Vout — Output Voltage — V
VDD = 5 V
tint = 0.5 ms to 15 ms
1.5
1
0.5
0
0
10
20
30
40
60
50
TA ï Free-Air Temperature ï qC
70
Figure 15:
Dark Output Voltage vs. Free-Air Temperature
0.10
VDD = 5 V
tint = 0.5 ms
tint = 1 ms
Vout — Output Voltage
0.09
0.08
tint = 15 ms
tint = 5 ms
tint = 2.5 ms
0.07
0.06
0
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10
20
30
40
60
50
TA ï Free-Air Temperature ï qC
70
ams Datasheet
[v1-00] 2016-May-13
TSL1410R − Typical Characteristics
Figure 16:
Settling Time vs. Load
600
VDD = 3 V
Vout = 1 V
Settling Time to 1% — ns
500
470 pF
400
220 pF
300
200
100 pF
100
10 pF
0
0
200
400
600
800
RL — Load Resistance ï W
1000
Figure 17:
Settling Time vs. Load
600
VDD = 5 V
Vout = 1 V
Settling Time to 1% — ns
500
470 pF
400
220 pF
300
200
100 pF
100
0
ams Datasheet
[v1-00] 2016-May-13
10 pF
0
200
400
600
800
RL — Load Resistance ï W
1000
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TSL1410R − Application Information
Application Information
Figure 18:
Operational Connections
1
1
2
3
4
SI1/HOLD1/HOLD2
CLK1 and CLK2
5
6
SO1
SI2
8
9
10
11
12
SERIAL
Page 16
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SI1/HOLD1
CLK1 and CLK2
5
6
7
13
2
3
4
SO2
AO1/AO2
VDD
7
AO1
SO1
8
SI2/HOLD2
9
10
11
12
13
SO2
AO2
VDD
PARALLEL
ams Datasheet
[v1-00] 2016-May-13
TSL1410R − Application Information
Integration Time
The integration time of the linear array is the period during
which light is sampled and charge accumulates on each pixel’s
integrating capacitor. The flexibility to adjust the integration
period is a powerful and useful feature of the ams TSL14xx
linear array family. By changing the integration time, a desired
output voltage can be obtained on the output pin while
avoiding saturation for a wide range of light levels.
The integration time is the time between the SI
(Start Integration) positive pulse and the HOLD positive pulse
minus the 18 setup clocks. The TSL14xx linear array is normally
configured with the SI and HOLD pins tied together. This
configuration will be assumed unless otherwise noted. Sending
a high pulse to SI (observing timing rules for setup and hold to
clock edge) starts a new cycle of pixel output and integration
setup. However, a minimum of (n+1) clocks, where n is the
number of pixels, must occur before the next high pulse is
applied to SI. It is not necessary to send SI immediately on/after
the (n+1) clocks. A wait time adding up to a maximum total of
100ms between SI pulses can be added to increase the
integration time creating a higher output voltage in low light
applications.
Each pixel of the linear array consists of a light-sensitive
photodiode. The photodiode converts light intensity to a
voltage. The voltage is sampled on the Sampling Capacitor by
closing switch S2 (position 1) (see Figure 2 on page 2). Logic
controls the resetting of the Integrating Capacitor to zero by
closing switch S1 (position 2).
At SI input, all of the pixel voltages are simultaneously scanned
and held by moving S2 to position 2 for all pixels. During this
event, S2 for pixel 1 is in position 3. This makes the voltage of
pixel 1 available on the analog output. On the next clock, S2 for
pixel 1 is put into position 2 and S2 for pixel 2 is put into
position 3 so that the voltage of pixel 2 is available on the
output.
Following the SI pulse and the next 17 clocks after the SI pulse
is applied, the S1 switch for all pixels remains in position 2 to
reset (zero out) the integrating capacitor so that it is ready to
begin the next integration cycle. On the rising edge of the 19 th
clock, the S1 switch for all the pixels is put into position 1 and
all of the pixels begin a new integration cycle.
The first 18 pixel voltages are output during the time the
integrating capacitor is being reset. On the 19th clock following
an SI pulse, pixels 1 through 18 have switch S2 in position 1 so
that the sampling capacitor can begin storing charge. For the
period from the 19 th clock through the nth clock, S2 is put into
position 3 to read the output voltage during the nth clock. On
the next clock the previous pixel S2 switch is put into position 1
to start sampling the integrating capacitor voltage. For
ams Datasheet
[v1-00] 2016-May-13
Page 17
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TSL1410R − Application Information
example, S2 for pixel 19 moves to position 1 on the 20 th clock.
On the n+1 clock, the S2 switch for the last (n th) pixel is put into
position 1 and the output goes to a high-impedance state.
If a SI was initiated on the n+1 clock, there would be no time
for the sampling capacitor of pixel n to charge to the voltage
level of the integrating capacitor. The minimum time needed
to guarantee the sampling capacitor for pixel n will charge to
the voltage level of the integrating capacitor is the charge
transfer time of 20μs. Therefore, after n+1 clocks, an extra 20μs
wait must occur before the next SI pulse to start a new
integration and output cycle.
The minimum integration time for any given array is determined
by time required to clock out all the pixels in the array and the
time to discharge the pixels. The time required to discharge the
pixels is a constant. Therefore, the minimum integration period
is simply a function of the clock frequency and the number of
pixels in the array. A slower clock speed increases the minimum
integration time and reduces the maximum light level for
saturation on the output. The minimum integration time shown
in this data sheet is based on the maximum clock frequency of
8MHz.
The minimum integration time can be calculated from the
equation:
1
T int ( min ) =  ------------------------------------------------------------------------- × ( n – 18 ) pixels + 20μs
 maximum clock frequency
where:
n is the number of pixels
In the case of the TSL1410R with the maximum clock frequency
of 8MHz, the minimum integration time would be:
Tint(min) = 0.125μs × (640 - 18) + 20μs = 97.75μs
It is good practice on initial power up to run the clock (n+1)
times after the first SI pulse to clock out indeterminate data
from power up. After that, the SI pulse is valid from the time
following (n+1) clocks. The output will go into a
high-impedance state after the n+1 high clock edge. It is good
practice to leave the clock in a low state when inactive because
the SI pulse required to start a new cycle is a low-to-high
transition.
The integration time chosen is valid as long as it falls in the
range between the minimum and maximum limits for
integration time. If the amount of light incident on the array
during a given integration period produces a saturated output
(Max Voltage output), then the data is not accurate. If this
occurs, the integration period should be reduced until the
analog output voltage for each pixel falls below the saturation
level. The goal of reducing the period of time the light sampling
window is active is to lower the output voltage level to prevent
saturation. However, the integration time must still be greater
than or equal to the minimum integration period.
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ams Datasheet
[v1-00] 2016-May-13
TSL1410R − Application Information
If the light intensity produces an output below desired signal
levels, the output voltage level can be increased by increasing
the integration period provided that the maximum integration
time is not exceeded. The maximum integration time is limited
by the length of time the integrating capacitors on the pixels
can hold their accumulated charge. The maximum integration
time should not exceed 100ms for accurate measurements.
It should be noted that the data from the light sampled during
one integration period is made available on the analog output
during the next integration period and is clocked out
sequentially at a rate of one pixel per clock period. In other
words, at any given time, two groups of data are being handled
by the linear array: the previous measured light data is clocked
out as the next light sample is being integrated.
Although the linear array is capable of running over a wide
range of operating frequencies up to a maximum of 8MHz, the
speed of the A/D converter used in the application is likely to
be the limiter for the maximum clock frequency. The voltage
output is available for the whole period of the clock, so the
setup and hold times required for the analog-to-digital
conversion must be less than the clock period.
ams Datasheet
[v1-00] 2016-May-13
Page 19
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TSL1410R − Mechanical Information
Mechanical Information
Figure 19:
TSL1410R Mechanical Specifications
TOP VIEW
0.100 (2,54) x 12 = 1.2 (30,48)
(Tolerance Noncumulative)
0.175 (4,24)
0.165 (4,19)
To Pixel 1
0.021 (0,533) DIA
13 Places
1.180 (29,97)
1.170 (29,72)
0.095 (2,21)
0.080 (2,03)
0.100 (2,54)
BSC
1
0.510 (12,95)
0.490 (12,45)
13
0.242 (6,15)
0.222 (5,64)
0.091 (2,31)
0.087 (2,21)
DIA (2 Places)
Centerline of Pixels is on the
Centerline of Mounting Holes
DETAIL A
0.228 (5,79)
0.208 (5,28)
3.548 (90,120)
3.528 (89,611)
0.086 (2,184)
0.076 (1,930)
3.705 (94,11)
3.695 (93,85)
0.130 (3,30)
0.120 (3,05)
Cover Glass
(Index of Refraction = 1.52)
0.015 (0,38) Typical Free Area
ÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈ
0.027 (0,690)
Linear Array
0.048 (1,22)
0.038 (0,97)
ÌÌÌÌÌÌ
ÌÌÌÌÌÌ
Cover Glass
Bonded Chip
Bypass Cap
DETAIL A
Note(s):
1. All linear dimensions are in inches (millimeters).
2. Pixel centers are in line with center line of mounting holes.
3. The gap between the individual sensor dies in the array is 57μm typical (51μm minimum and 75μm maximum).
4. This drawing is subject to change without notice.
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TSL1410R − Mechanical Information
Figure 20:
Edge Pixel Layout Dimensions
THEORETICAL PIXEL LAYOUT FOR IDEAL CONTINUOUS DIE
8.00
63.50
55.50
Nï2
Nï1
N
1
2
3
ACTUAL MULTI-DIE PIXEL LAYOUT FOR DIE-TO-DIE EDGE JOINING
Nï2
Nï1
95.50
76.50
64.00
Note 2
N
1
2
3
46.00
154.50
37.00
11.00
25.50
14.50
13.00
Note 3
Note(s):
1. All linear dimensions are in micrometers.
2. Spacing between outside pixels of adjacent die is typical.
3. Die-to-die spacing.
4. This drawing is subject to change without notice.
ams Datasheet
[v1-00] 2016-May-13
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TSL1410R − Ordering & Contact Information
Ordering & Contact Information
Figure 21:
Ordering Information
Ordering Code
Type
Delivery Form
Delivery Quantity
TSL1410R
1280 x 1 Array
Tray
20 pcs/tray
Buy our products or get free samples online at:
www.ams.com/ICdirect
Technical Support is available at:
www.ams.com/Technical-Support
Provide feedback about this document at:
www.ams.com/Document-Feedback
For further information and requests, e-mail us at:
[email protected]
For sales offices, distributors and representatives, please visit:
www.ams.com/contact
Headquarters
ams AG
Tobelbaderstrasse 30
8141 Premstaetten
Austria, Europe
Tel: +43 (0) 3136 500 0
Website: www.ams.com
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TSL1410R − RoHS Compliant & ams Green Statement
RoHS Compliant & ams Green
Statement
RoHS: The term RoHS compliant means that ams AG products
fully comply with current RoHS directives. Our semiconductor
products do not contain any chemicals for all 6 substance
categories, including the requirement that lead not exceed
0.1% by weight in homogeneous materials. Where designed to
be soldered at high temperatures, RoHS compliant products are
suitable for use in specified lead-free processes.
ams Green (RoHS compliant and no Sb/Br): ams Green
defines that in addition to RoHS compliance, our products are
free of Bromine (Br) and Antimony (Sb) based flame retardants
(Br or Sb do not exceed 0.1% by weight in homogeneous
material).
Important Information: The information provided in this
statement represents ams AG knowledge and belief as of the
date that it is provided. ams AG bases its knowledge and belief
on information provided by third parties, and makes no
representation or warranty as to the accuracy of such
information. Efforts are underway to better integrate
information from third parties. ams AG has taken and continues
to take reasonable steps to provide representative and accurate
information but may not have conducted destructive testing or
chemical analysis on incoming materials and chemicals. ams AG
and ams AG suppliers consider certain information to be
proprietary, and thus CAS numbers and other limited
information may not be available for release.
ams Datasheet
[v1-00] 2016-May-13
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TSL1410R − Copyrights & Disclaimer
Copyrights & Disclaimer
Copyright ams AG, Tobelbader Strasse 30, 8141 Premstaetten,
Austria-Europe. Trademarks Registered. All rights reserved. The
material herein may not be reproduced, adapted, merged,
translated, stored, or used without the prior written consent of
the copyright owner.
Devices sold by ams AG are covered by the warranty and patent
indemnification provisions appearing in its General Terms of
Trade. ams AG makes no warranty, express, statutory, implied,
or by description regarding the information set forth herein.
ams AG reserves the right to change specifications and prices
at any time and without notice. Therefore, prior to designing
this product into a system, it is necessary to check with ams AG
for current information. This product is intended for use in
commercial applications. Applications requiring extended
temperature range, unusual environmental requirements, or
high reliability applications, such as military, medical
life-support or life-sustaining equipment are specifically not
recommended without additional processing by ams AG for
each application. This product is provided by ams AG “AS IS”
and any express or implied warranties, including, but not
limited to the implied warranties of merchantability and fitness
for a particular purpose are disclaimed.
ams AG shall not be liable to recipient or any third party for any
damages, including but not limited to personal injury, property
damage, loss of profits, loss of use, interruption of business or
indirect, special, incidental or consequential damages, of any
kind, in connection with or arising out of the furnishing,
performance or use of the technical data herein. No obligation
or liability to recipient or any third party shall arise or flow out
of ams AG rendering of technical or other services.
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TSL1410R − Document Status
Document Status
Document Status
Product Preview
Preliminary Datasheet
Datasheet
Datasheet (discontinued)
ams Datasheet
[v1-00] 2016-May-13
Product Status
Definition
Pre-Development
Information in this datasheet is based on product ideas in
the planning phase of development. All specifications are
design goals without any warranty and are subject to
change without notice
Pre-Production
Information in this datasheet is based on products in the
design, validation or qualification phase of development.
The performance and parameters shown in this document
are preliminary without any warranty and are subject to
change without notice
Production
Information in this datasheet is based on products in
ramp-up to full production or full production which
conform to specifications in accordance with the terms of
ams AG standard warranty as given in the General Terms of
Trade
Discontinued
Information in this datasheet is based on products which
conform to specifications in accordance with the terms of
ams AG standard warranty as given in the General Terms of
Trade, but these products have been superseded and
should not be used for new designs
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TSL1410R − Revision Information
Revision Information
Changes from 043E (2007-Apr) to current revision 1-00 (2016-May-13)
Page
Content of TAOS datasheet was converted to the latest ams design
Updated Key Benefits & Features
1
Updated Ordering Information
22
Note(s):
1. Page and figure numbers for the previous version may differ from page and figure numbers in the current revision.
2. Correction of typographical errors is not explicitly mentioned.
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TSL1410R − Content Guide
Content Guide
ams Datasheet
[v1-00] 2016-May-13
1
1
2
General Description
Key Benefits & Features
Block Diagram
3
5
7
8
12
Detailed Description
Pin Assignments
Absolute Maximum Ratings
Electrical Characteristics
Typical Characteristics
16
17
Application Information
Integration Time
20
22
23
24
25
26
Mechanical Information
Ordering & Contact Information
RoHS Compliant & ams Green Statement
Copyrights & Disclaimer
Document Status
Revision Information
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