ETC TSL1401CS

TSL1401CS
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS036A - AUGUST 2003
128 × 1 Sensor-Element Organization
400 Dots-Per-Inch (DPI) Sensor Pitch
High Linearity and Uniformity
Wide Dynamic Range . . . 4000:1 (72 dB)
Output Referenced to Ground
Low Image Lag . . . 0.5% Typ
Operation to 8 MHz
Single 3-V to 5-V Supply
Rail-to-Rail Output Swing (AO)
No External Load Resistor Required
(TOP VIEW)
1 SI
HOLD 2
3 CLK
GND 4
5 GND
Description
AO 6
The TSL1401CS linear sensor array consists of a
128 × 1 array of photodiodes, associated charge
amplifier circuitry, and a pixel data-hold function
that provides simultaneous-integration start and
stop times for all pixels. The pixels measure 63.5
µm (H) by 55.5 µm (W) with 63.5-µm center-tocenter spacing and 8-µm spacing between pixels.
Operation is simplified by internal control logic that
requires only a serial-input (SI) signal and a clock.
7 SO
VDD 8
Functional Block Diagram
Pixel 1
Pixel
2
Integrator
Reset
Pixel
3
8
Pixel
128
VDD
Analog
Bus
Output
Buffer
_
6
AO
+
Sample/
Output
4, 5
GND
Switch Control Logic
Hold
2
Q1
Q2
Q3
Q128
Gain
Trim
7
CLK
SI
3
SO
128-Bit Shift Register
1
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Copyright 2003, TAOS Inc.
Texas Advanced Optoelectronic Solutions Inc.
800 Jupiter Road, Suite 205 Plano, TX 75074 (972)
673-0759
www.taosinc.com
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TSL1401CS
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS036A - AUGUST 2003
Terminal Functions
TERMINAL
NAME
AO
DESCRIPTION
NO.
6
Analog output
CLK
3
Clock. The clock controls charge transfer, pixel output, and reset.
GND
4, 5
Ground (substrate). All voltages are referenced to the substrate.
HOLD
2
Hold signal. HOLD freezes the result of a 128 pixel scan.
SI
1
Serial input. SI defines the start of the data-out sequence.
SO
7
Serial output. SO provides a signal to drive the SI input of another device
for cascading or as an end-of-data indication.
VDD
8
Supply voltage. Supply voltage for both analog and digital circuits.
Detailed Description
The sensor consists of 128 photodiodes arranged in a linear array. Light energy impinging on a photodiode
generates photocurrent, which is integrated by the active integration circuitry associated with that pixel.
During the integration period, a sampling capacitor connects to the output of the integrator through an analog
switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity and the
integration time.
The output and reset of the integrators is controlled by a 128-bit shift register and reset logic. An output cycle
is initiated by clocking in a logic 1 on SI. For proper operation, after meeting the minimum hold time condition,
SI must go low before the next rising edge of the clock. The signal called Hold is normally connected to SI. Then,
the rising edge of SI causes a HOLD condition. This causes all 128 sampling capacitors to be disconnected from
their respective integrators and starts an integrator reset period. As the SI pulse is clocked through the shift
register, the charge stored on the sampling capacitors is sequentially connected to a charge-coupled output
amplifier that generates a voltage on analog output AO. Simultaneously, during the first 18 clock cycles, all pixel
integrators are reset, and the next integration cycle begins on the 19th clock. On the 129th clock rising edge,
the SI pulse is clocked out of the shift register and the analog output AO assumes a high impedance state. Note
that this 129th clock pulse is required to terminate the output of the 128th pixel, and return the internal logic to
a known state. A subsequent SI pulse may be presented as early as the 130th clock pulse, thereby initiating
another pixel output cycle.
AO is an op amp-type output that does not require an external pull-down resistor. This design allows a rail-to-rail
output voltage swing. With VDD = 5 V, the output is nominally 0 V for no light input, 2 V for normal white level, and 4.8 V
for saturation light level. When the device is not in the output phase, AO is in a high-impedance state.
The voltage developed at analog output (AO) is given by:
Vout = Vdrk + (Re) (Ee)(tint)
where:
Vout
Vdrk
Re
Ee
tint
is the analog output voltage for white condition
is the analog output voltage for dark condition
is the device responsivity for a given wavelength of light given in V/(µJ/cm2)
is the incident irradiance in µW/cm2
is integration time in seconds
A 0.1 µF bypass capacitor should be connected between VDD and ground as close as possible to the device.
The TSL1401CS is intended for use in a wide variety of applications, including: image scanning, mark and code
reading, optical character recognition (OCR) and contact imaging, edge detection and positioning, and optical
linear and rotary encoding.
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TSL1401CS
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS036A - AUGUST 2003
Absolute Maximum Ratings†
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VDD + 0.3V
Input clamp current, IIK (VI < 0) or (VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 20 mA to 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 25 mA to 25 mA
Voltage range applied to any output in the high impedance or power-off state, VO . . . - 0.3 V to VDD + 0.3 V
Continuous output current, IO (VO = 0 to VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 25 mA to 25 mA
Continuous current through VDD or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40 mA to 40 mA
Analog output current range, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 25 mA to 25 mA
Maximum light exposure at 638 nm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mJ/cm2
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 °C to 100°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40°C to 100°C
Solder reflow temperature, case exposed for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions (see Figure 1 and Figure 2)
MIN
NOM
Supply voltage, VDD
3
5
5.5
V
Input voltage, VI
0
VDD
V
High-level input voltage, VIH
Low-level input voltage, VIL
2
VDD
V
Wavelength of light source, λ
Clock frequency, fclock
Sensor integration time, tint (see Note 1)
Setup time, serial input, tsu(SI)
Hold time, serial input, th(SI) (see Note 2)
MAX
0
0.8
400
1000
nm
5
8000
kHz
0.016
100
ms
20
-40
V
ns
0
Operating free-air temperature, TA
UNIT
ns
85
°C
NOTES: 1. This time does not include the 18 clock cycles for setup, which would consume an additional 0.002 mS of device integrate and read
time.
2. SI must go low before the rising edge of the next clock pulse.
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TSL1401CS
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS036A - AUGUST 2003
Electrical Characteristics at fclock = 1 MHz, VDD = 5 V, TA = 25°C, λp = 640 nm, tint = 5 ms,
RL = 330 Ω, Ee = 11 µW/cm2 (unless otherwise noted) (see Note 3 and Note 4)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.6
2
2.4
UNIT
V
0.1
0.2
V
±4%
±10%
Vout
Analog output voltage (white, average over 128 pixels)
Vdrk
Analog output voltage (dark, average over 128 pixels)
Ee = 0
PRNU
Pixel response nonuniformity
See Note 5
Nonlinearity of analog output voltage
See Note 6
±0.4%
Output noise voltage
See Note 7
1
Re
Responsivity
See Note 8
25
35
4.8
Analog output saturation voltage
VDD = 5 V, RL = 330 Ω
4.5
Vsat
VDD = 3 V, RL = 330 Ω
2.5
2.8
SE
Saturation exposure
DSNU
Dark signal nonuniformity
All pixels, Ee = 0
IL
Image lag
See Note 11
IDD
Supply current
VIH
High-level input voltage
VIL
Low-level input voltage
0.8
V
IIH
High-level input current
VI = VDD
1
µA
IIL
Low-level input current
VI = 0
1
µA
Ci
Input capacitance
0
VDD = 5 V, See Note 9
136
VDD = 3 V, See Note 9
78
See Note 10
0.02
FS
mVrms
44
V/
(µJ/cm 2)
V
nJ/cm 2
0.05
V
0.5%
VDD = 5 V, Ee = 0
2.8
4.5
VDD = 3 V, Ee = 0
2.6
4.5
2
mA
V
5
pF
NOTES: 3. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640 nm.
4. All measurements made with a 0.1 µF capacitor connected between VDD and ground.
5. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the
device under test when the array is uniformly illuminated at the white irradiance level. PRNU includes DSNU.
6. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent
of analog output voltage (white).
7. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period.
8. Re(min) = [Vout(min) - Vdrk(max)] ÷ (Ee × tint)
9. SE(min) = [Vsat(min) - Vdrk(min)] × 〈Ee × tint) ÷ [Vout(max) - Vdrk(min)]
10. DSNU is the difference between the maximum and minimum output voltage for all pixels in the absence of illumination.
11. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after
a pixel is exposed to a white condition followed by a dark condition:
IL V out (IL) V drk
100
V out (white) V drk
Timing Requirements (see Figure 1 and Figure 2)
MIN
tsu(SI)
Setup time, serial input (see Note 12)
th(SI)
Hold time, serial input (see Note 11 and Note 13)
tw
Pulse duration, clock high or low
tr, tf
Input transition (rise and fall) time
0
NOM
MAX
UNIT
20
ns
0
ns
50
ns
500
ns
NOTES: 12. Input pulses have the following characteristics: tr = 6 ns, tf = 6 ns.
13. SI must go low before the rising edge of the next clock pulse.
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TSL1401CS
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS036A - AUGUST 2003
Dynamic Characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figures 3 and 4)
PARAMETER
TEST CONDITIONS
Analog output settling time to ±1%
ts
RL = 330 Ω,
MIN
CL = 10 pF
TYP
120
MAX
UNIT
ns
TYPICAL CHARACTERISTICS
CLK
SI
Internal
Reset
18 Clock Cycles
Integration
Not Integrating
Integrating
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ
129 Clock Cycles
AO
Hi-Z
Hi-Z
Figure 1. Timing Waveforms
tw
1
2
128
129
5V
2.5 V
CLK
0V
tsu(SI)
SI
5V
50%
0V
th(SI)
ts
AO
ts
Pixel 1
Pixel 128
Figure 2. Operational Waveforms
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TSL1401CS
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS036A - AUGUST 2003
TYPICAL CHARACTERISTICS
SETTLING TIME
vs.
LOAD
SETTLING TIME
vs.
LOAD
600
600
VDD = 3 V
VDD = 5 V
Vout = 1 V
Vout = 1 V
500
470 pF
Settling Time to 1% — ns
Settling Time to 1% — ns
500
400
220 pF
300
200
100 pF
100
470 pF
400
220 pF
300
200
100 pF
100
10 pF
10 pF
0
0
200
400
600
800
RL — Load Resistance - 0
1000
0
200
400
600
800
RL — Load Resistance - Figure 3
1000
Figure 4
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
PHOTODIODE SPECTRAL RESPONSIVITY
1
4
TA = 25°C
VDD = 5 V
Ee = 0
RL = 330 IDD — Supply Current — mA
Relative Responsivity
0.8
0.6
0.4
0.2
0
300
3
2
1
0
400
500
600 700 800 900
λ - Wavelength - nm
1000 1100
0
10
20
30
40
60
50
TA - Free-Air Temperature - °C
Figure 5
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Figure 6
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TSL1401CS
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS036A - AUGUST 2003
TYPICAL CHARACTERISTICS
DARK OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
WHITE OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
2
0.100
tint = 0.5 ms
tint = 1 ms
VDD = 5 V
Vout — Output Voltage — V
Vout — Output Voltage — V
VDD = 5 V
tint = 0.5 ms to 15 ms
Ee = Varies
1.5
1
0.5
0
0.090
0.080
tint = 15 ms
tint = 5 ms
tint = 2.5 ms
0.070
0.060
0
10
20
30
40
60
50
TA - Free-Air Temperature - °C
70
0
10
20
30
40
60
50
TA - Free-Air Temperature - °C
Figure 7
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Figure 8
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TSL1401CS
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS036A - AUGUST 2003
APPLICATION INFORMATION
A 0.1 µF bypass capacitor should be connected between VDD and ground as close as possible to the device.
The HOLD pin on the device is normally connected to the SI pin in single-die operation. In multi-die operation
of n die, the HOLD pin is used to provide a continuous scan across the n die. See Figure 9 for an example of
this wiring configuration. Note that there is a single AO signal when used in this mode. Alternately, the individual
die may be scanned all at once by connecting the individual SI and HOLD lines and reading the AO signals in
parallel. See Figure 10 for an example of this wiring configuration.
VDD
C1
0.1 F
C2
0.1 F
C3
0.1 F
AO
8
1
8
VDD
SI
AO
1
6
VDD
SI
TSL1401CS
2
3
AO
VDD
SI
AO
SO
3
7
CLK
SO
3
7
HOLD
CLK
SO
GND
4
7
GND
4
5
6
TSL1401CS
2
HOLD
GND
5
1
6
TSL1401CS
2
HOLD
CLK
8
4
5
GND
CLK
SI
Figure 9. Multi-Die Continuous Scan
VDD
C1
0.1 F
C2
0.1 F
C3
0.1 F
AO1
AO2
8
1
8
VDD
SI
AO
1
6
VDD
SI
TSL1401CS
2
3
AO
2
SO
VDD
SI
AO
3
7
2
CLK
SO
5
AO3
3
7
HOLD
CLK
SO
GND
4
6
TSL1401CS
HOLD
GND
5
1
6
TSL1401CS
HOLD
CLK
8
7
GND
4
5
4
GND
CLK
SI
Figure 10. Multi-Die Individual Scan
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TSL1401CS
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS036A - AUGUST 2003
APPLICATION INFORMATION
TOP
BOTTOM
Figure 11. Device Pictorial
8 360
Diameter
Metal Pad
8 380
Diameter
Mask
170
1
2
3
4
5
6
7
8 110
Trace Width
8
7 1000
NOTES: A. All linear dimensions are in micrometers.
B. This drawing is subject to change without notice.
Figure 12. Suggested PCB Layout
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TSL1401CS
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS036A - AUGUST 2003
MECHANICAL INFORMATION
The TSL1401CS is available in a solder bump linear array package, ready for surface mount manufacturing
processes.
8870 25
TOP VIEW
8120
1000 25
A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Pixel 1
Pixel 128
Alignment Marker (Pin 8)
SIDE VIEW
B
655 30
BOTTOM
VIEW
4
8
145 30
170
935 30
7
4
415 30
1000
DETAIL A
DETAIL B
4
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
1
2
3
4
5
6
7
8
SI
HOLD
CLK
GND
GND
AO
SO
VDD
128
63.5
8
375 25
128
430.4 25
55.5
4
127
265 25
62
63.5
NOTES: A. All linear dimensions are in micrometers.
B. Unless otherwise noted, all dimensions are ± 10.
C. This drawing is subject to change without notice.
Figure 13. Packaging Configuration
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TSL1401CS
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS036A - AUGUST 2003
MECHANICAL INFORMATION
1.24 0.100
0.300 0.200
SIDE VIEW
1.5 0.100 Typ
1.75 0.100
4 0.100 Typ
2 0.100
Pin 1
4 0.100
TOP VIEW
A
7.50
0.100
16
CL
+ 0.300
- 0.100
A
R 0.58
B
DETAIL A
B
DETAIL B
Ko
9.17
0.82
Bo
8 Max
7.60
1.29
Ao
1.17
5 Max
NOTES: A.
B.
C.
D.
E.
F.
All linear dimensions are in millimeters.
The dimensions on this drawing are for illustrative purposes only. Dimensions of an actual carrier may vary slightly.
Symbols on drawing Ao, Bo, and Ko are defined in ANSI EIA Standard 481-B 2001.
Each reel is 178 millimeters in diameter and contains 2800 parts.
TAOS packaging tape and reel conform to the requirements of EIA Standard 481-B.
This drawing is subject to change without notice.
Figure 14. TSL1401CS Carrier Tape
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TSL1401CS
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS036A - AUGUST 2003
MANUFACTURING INFORMATION
This product has been tested and has demonstrated an ability to be reflow soldered to a PCB substrate. The
process, equipment, and materials used in these tests are detailed below.
Tooling Required
Solder stencil (round aperture size 0.36 mm, stencil thickness of 152.4 µm)
20 × 20 frame for solder stencil
Process
1. Apply solder paste using stencil
2. Dispense adhesive dots
3. Place component
4. Reflow solder/cure
5. X-Ray verify
Placement of the TSL1401CS device onto the gold immersion substrate is accomplished using a standard
surface mount manufacturing process. First, using the stencil with 0.36 mm square aperture, print solder paste
onto the substrate. Next, dispense two 0.25 mm to 0.4 mm diameter dots of adhesive in opposing corners of
the TSL1401CS mounting area. Machine place the TSL1401CS from the JEDEC waffle carrier onto the
substrate. A suggested pick-up tool is the Siemens Vacuum Pickup tool nozzle number 912. This nozzle has
a rubber tip with a diameter of approximately 0.75 mm. The part is picked up from the center of the body. Reflow
the solder and cure the adhesive using the solder profile shown in Figure 15.
250
Temperature — C
200
150
100
50
0
0
50
100
150
200
250
300
350
400
450
500
Time - s
Figure 15. TSL1401CS Solder Profile
It is important to use a substrate that has an immersion plating surface. This may be immersion gold, silver, or
white tin. Hot air solder leveled substrates (HASL) are not coplanar and should not be used.
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TSL1401CS
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS036A - AUGUST 2003
MANUFACTURING INFORMATION
Qualified Equipment
EKRA E5 — Stencil Printer
ASYMTEC Century — Dispensing system
SIEMENS F5 — Placement system
- SIEMENS 912 — Vacuum Pickup Tool Nozzle
VITRONICS 820 — Oven
PHOENIX — Inspector X-Ray system
Qualified Materials
OMG — Microbond solder paste
Loctite 3621 — Adhesive
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TSL1401CS
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
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PRODUCTION DATA — information in this document is current at publication date. Products conform to
specifications in accordance with the terms of Texas Advanced Optoelectronic Solutions, Inc. standard
warranty. Production processing does not necessarily include testing of all parameters.
NOTICE
Texas Advanced Optoelectronic Solutions, Inc. (TAOS) reserves the right to make changes to the products contained in this
document to improve performance or for any other purpose, or to discontinue them without notice. Customers are advised
to contact TAOS to obtain the latest product information before placing orders or designing TAOS products into systems.
TAOS assumes no responsibility for the use of any products or circuits described in this document or customer product
design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that
the circuits are free of patent infringement. TAOS further makes no claim as to the suitability of its products for any particular
purpose, nor does TAOS assume any liability arising out of the use of any product or circuit, and specifically disclaims any
and all liability, including without limitation consequential or incidental damages.
TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, INC. PRODUCTS ARE NOT DESIGNED OR INTENDED FOR
USE IN CRITICAL APPLICATIONS IN WHICH THE FAILURE OR MALFUNCTION OF THE TAOS PRODUCT MAY
RESULT IN PERSONAL INJURY OR DEATH. USE OF TAOS PRODUCTS IN LIFE SUPPORT SYSTEMS IS EXPRESSLY
UNAUTHORIZED AND ANY SUCH USE BY A CUSTOMER IS COMPLETELY AT THE CUSTOMER’S RISK.
LUMENOLOGY, TAOS, the TAOS logo, and Texas Advanced Optoelectronic Solutions are registered trademarks of Texas Advanced
Optoelectronic Solutions Incorporated.
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