TSL1402R 256 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS041 – AUGUST 2002 256 × 1 Sensor-Element Organization 400 Dots-Per-Inch (DPI) Sensor Pitch High Linearity and Uniformity Wide Dynamic Range . . . 4000:1 (72 dB) Output Referenced to Ground Low Image Lag . . . 0.5% Typ Operation to 8 MHz Single 3-V to 5-V Supply Rail-to-Rail Output Swing (AO) No External Load Resistor Required Replacement for TSL1402 ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÇÇ ÇÇ ÇÇ ÇÇ ÇÇ (TOP VIEW) VDD 1 SI1 2 CLK 3 AO1 4 GND 5 SO2 6 NC 7 14 NC 13 SO1 12 GND 11 NC 10 SI2 9 NC 8 AO2 NC – No internal connection Description The TSL1402R linear sensor array consists of two sections of 128 photodiodes each and associated charge amplifier circuitry, aligned to form a contiguous 256 × 1 pixel array. The device incorporates a pixel data-hold function that provides simultaneous integration start and stop times for all pixels. The pixels measure 63.5 µm by 55.5 µm, with 63.5-µm center-to-center spacing and 8-µm spacing between pixels. Operation is simplified by internal logic requiring only a serial-input pulse (SI) and a clock. The TSL1402R is intended for use in a wide variety of applications including mark and code reading, OCR and contact imaging, edge detection and positioning, and optical encoding. Functional Block Diagram (each section – pin numbers apply to section 1) 1 Pixel 2 Pixel 1 Integrator Reset Pixel 3 Pixel 128 VDD Analog Bus 4 Output Buffer _ AO + Sample/Hold/ Output 5 GND Gain Trim Switch Control Logic 13 Hold CLK SI Q1 3 Q2 Q3 SO Q128 128-Bit Shift Register 2 The LUMENOLOGY Company Copyright 2002, TAOS Inc. Texas Advanced Optoelectronic Solutions Inc. 800 Jupiter Road, Suite 205 Plano, TX 75074 (972) 673-0759 www.taosinc.com 1 TSL1402R 256 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS041 – AUGUST 2002 Terminal Functions TERMINAL NAME DESCRIPTION NO. AO1 4 Analog output of section 1. AO2 8 Analog output of section 2. CLK 3 Clock. Clk controls charge transfer, pixel output, and reset. GND 5,12 NC 7, 9, 11, 14 Ground (substrate). All voltages are referenced to GND. No internal connection. SI1 2 Serial input (section 1). SI1 defines the start of the data-out sequence for section 1. SI2 10 Serial input (section 2). SI2 defines the start of the data-out sequence for section 2. SO1 13 Serial output (section 1). SO1 provides a signal to drive the SI2 input (in serial connection). SO2 6 Serial output (section 2). SO2 provides a signal to drive the SI input of another device for cascading or as an end-of-data indication. VDD 1 Supply voltage. Supply voltage for both analog and digital circuitry. Detailed Description Device operation (assumes serial connection) The sensor consists of 256 photodiodes, called pixels, arranged in a linear array. Light energy impinging on a pixel generates photocurrent, which is then integrated by the active integration circuitry associated with that pixel. During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity on that pixel and the integration time. The output and reset of the integrators is controlled by a 256-bit shift register and reset logic. An output cycle is initiated by clocking in a logic 1 on SI1. An internal signal, called Hold, is generated from the rising edge of SI1 and simultaneously transmitted to sections 1 and 2. This causes all 256 sampling capacitors to be disconnected from their respective integrators and starts an integrator reset period. As the SI pulse is clocked through the shift register, the charge stored on the sampling capacitors is sequentially connected to a charge-coupled output amplifier that generates a voltage on analog output AO. Simultaneously, during the first 18 clock cycles, all pixel integrators are reset, and the next integration cycle begins on the 19th clock. On the 128th clock rising edge, the SI pulse is clocked out on the SO1 pin (section 1) and becomes the SI pulse for section 2 (SI2). The rising edge of the 129th clock cycle terminates the SO1 pulse, and returns the analog output AO1 of section 1 to high-impedance state. Analog output AO2 now becomes the active output. As in section 2, SO2 is clocked out on the 256th clock pulse. Note that a 257th clock pulse is needed to terminate the SO2 pulse and return AO2 to the high-impedance state. Copyright 2002, TAOS Inc. The LUMENOLOGY Company 2 www.taosinc.com TSL1402R 256 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS041 – AUGUST 2002 AO is an op amp-type output that does not require an external pull-down resistor. This design allows a rail-to-rail output voltage swing. With VDD = 5 V, the output is nominally 0 V for no light input, 2 V for normal white level, and 4.8 V for saturation light level. When the device is not in the output phase, AO is in a high-impedance state. The voltage developed at analog output (AO) is given by: Vout = Vdrk + (Re) (Ee)(tint) where: Vout Vdrk Re Ee tint is is is is is the analog output voltage for white condition the analog output voltage for dark condition the device responsivity for a given wavelength of light given in V/(µJ/cm2) the incident irradiance in µW/cm2 integration time in seconds The TSL1402R can be connected in the serial mode, where it takes 256 clocks to read out all pixels, or in the parallel mode where it takes 128 clocks to read out all pixels (see APPLICATION INFORMATION and FIgures 9 and 10). A 0.1 µF bypass capacitor should be connected between VDD and ground as close as possible to the device. The LUMENOLOGY Company Copyright 2002, TAOS Inc. www.taosinc.com 3 TSL1402R 256 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS041 – AUGUST 2002 Absolute Maximum Ratings† Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3V Input clamp current, IIK (VI < 0) or (VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA to 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25 mA to 25 mA Voltage range applied to any output in the high impedance or power-off state, VO . . . –0.3 V to VDD + 0.3 V Continuous output current, IO (VO = 0 to VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25 mA to 25 mA Continuous current through VDD or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40 mA to 40 mA Analog output current range, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25 mA to 25 mA Maximum light exposure at 638 nm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mJ/cm2 Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to 85°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Recommended Operating Conditions (see Figure 1 and Figure 2) MIN NOM Supply voltage, VDD 3 5 5.5 V Input voltage, VI 0 VDD V High-level input voltage, VIH Low-level input voltage, VIL 2 VDD V Wavelength of light source, λ Clock frequency, fclock MAX 0 0.8 400 1000 UNIT V nm 5 8000 kHz Sensor integration time, Parallel, tint 0.018 100 ms Sensor integration time, Serial, tint Setup time, serial input, tsu(SI) 0.034 100 ms 20 Hold time, serial input, th(SI) (see Note 1) 0 Operating free-air temperature, TA 0 ns ns 70 °C NOTE 1: SI must go low before the rising edge of the next clock pulse. Copyright 2002, TAOS Inc. The LUMENOLOGY Company 4 www.taosinc.com TSL1402R 256 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS041 – AUGUST 2002 Electrical Characteristics at fclock = 1 MHz, VDD = 5 V, TA = 25°C, λp = 640 nm, tint = 5 ms, RL = 330 Ω, Ee = 11 µW/cm2 (unless otherwise noted) (see Note 2) PARAMETER TEST CONDITIONS MIN TYP MAX 1.6 2 2.4 V 0 0.1 0.2 V Vout Analog output voltage (white, average over 256 pixels) See Note 3 Vdrk Analog output voltage (dark, average over 256 pixels) Ee = 0 PRNU Pixel response nonuniformity See Note 4 Nonlinearity of analog output voltage See Note 5 ±0.4% Output noise voltage See Note 6 1 Re Responsivity See Note 7 25 35 4.8 Analog output saturation voltage VDD = 5 V, RL = 330 Ω 4.5 Vsat VDD = 3 V, RL = 330 Ω 2.5 2.8 SE Saturation exposure DSNU Dark signal nonuniformity IL Image lag UNIT ±10% VDD = 5 V, See Note 8 136 VDD = 3 V, See Note 8 78 All pixels, Ee = 0, See Note 9 See Note 10 0.04 mVrms 45 V/ (µJ/cm 2) V nJ/cm 2 0.12 V 0.5% VDD = 5 V, Ee = 0 6 9 VDD = 3 V, Ee = 0 5 8 IDD Supply current mA IIH High-level input current VI = VDD 10 µA IIL Low-level input current VI = 0 10 µA Ci Input capacitance, SI Ci Input capacitance, CLK 5 pF 10 pF NOTES: 2. All measurements made with a 0.1 µF capacitor connected between VDD and ground. 3. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640 nm. 4. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the device under test when the array is uniformly illuminated at the white irradiance level. PRNU includes DSNU. 5. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent of analog output voltage (white). 6. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period. 7. Re(min) = [Vout(min) – Vdrk(max)] ÷ (Ee × tint) 8. SE(min) = [Vsat(min) – Vdrk(min)] × 〈Ee × tint) ÷ [Vout(max) – Vdrk(min)] 9. DSNU is the difference between the maximum and minimum output voltage for all pixels in the absence of illumination. 10. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after a pixel is exposed to a white condition followed by a dark condition: IL V out (IL) V drk V out (white) V drk 100 Timing Requirements (see Figure 1 and Figure 2) MIN tsu(SI) Setup time, serial input (see Note 11) th(SI) Hold time, serial input (see Note 11 and Note 12) tw Pulse duration, clock high or low 50 tr, tf Input transition (rise and fall) time 0 NOM MAX UNIT 20 ns 0 ns ns 500 ns NOTES: 11. Input pulses have the following characteristics: tr = 6 ns, tf = 6 ns. 12. SI must go low before the rising edge of the next clock pulse. The LUMENOLOGY Company Copyright 2002, TAOS Inc. www.taosinc.com 5 TSL1402R 256 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS041 – AUGUST 2002 Dynamic Characteristics over recommended ranges of supply voltage and operating free-air temperature (see Figures 7 and 8) PARAMETER ts Analog output settling time to ±1% tpd(SO) Propagation delay time, SO1, SO2 TEST CONDITIONS RL = 330 Ω, MIN CL = 10 pF TYP MAX UNIT 120 ns 50 ns TYPICAL CHARACTERISTICS CLK SI Internal Reset Integration 18 Clock Cycles tint Not Integrating Integrating ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ 257 Clock Cycles AO Hi-Z Hi-Z Figure 1. Timing Waveforms (Serial Connection) tw 1 (129) 2 128 129 (257) 5V CLK 0V tsu(SI) 5V SI 50% 0V th(SI) tpd(SO) tpd(SO) SO ts AO Pixel 1 (129) Pixel 128 (256) Figure 2. Operational Waveforms (each section) Copyright 2002, TAOS Inc. The LUMENOLOGY Company 6 www.taosinc.com TSL1402R 256 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS041 – AUGUST 2002 TYPICAL CHARACTERISTICS NORMALIZED IDLE SUPPLY CURRENT vs FREE-AIR TEMPERATURE PHOTODIODE SPECTRAL RESPONSIVITY 1 2 IDD — Normalized Idle Supply Current TA = 25°C Normalized Responsivity 0.8 0.6 0.4 0.2 0 300 1.5 1 0.5 0 400 500 600 700 800 900 1000 1100 0 10 λ – Wavelength – nm 30 40 50 60 70 TA – Free-Air Temperature – °C Figure 3 Figure 4 WHITE OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE DARK OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 2 0.10 VDD = 5 V tint = 0.5 ms to 15 ms tint = 0.5 ms tint = 1 ms VDD = 5 V 0.09 1.5 Vout — Output Voltage Vout — Output Voltage — V 20 1 0.08 tint = 15 ms tint = 5 ms tint = 2.5 ms 0.07 0.5 0 0.06 0 10 20 30 40 60 50 TA – Free-Air Temperature – °C 70 0 10 20 30 40 60 50 TA – Free-Air Temperature – °C Figure 5 The LUMENOLOGY Company 70 Figure 6 Copyright 2002, TAOS Inc. www.taosinc.com 7 TSL1402R 256 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS041 – AUGUST 2002 TYPICAL CHARACTERISTICS SETTLING TIME vs. LOAD SETTLING TIME vs. LOAD 600 600 VDD = 3 V Vout = 1 V VDD = 5 V Vout = 1 V 500 470 pF Settling Time to 1% — ns Settling Time to 1% — ns 500 400 220 pF 300 200 100 pF 100 470 pF 400 220 pF 300 200 100 pF 100 10 pF 10 pF 0 0 200 400 600 800 RL — Load Resistance – 1000 0 0 200 400 600 800 RL — Load Resistance – Figure 7 Copyright 2002, TAOS Inc. Figure 8 The LUMENOLOGY Company 8 1000 www.taosinc.com TSL1402R 256 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS041 – AUGUST 2002 APPLICATION INFORMATION Power Supply Considerations For optimum device performance, power-supply lines should be decoupled by a 0.01-µF to 0.1-µF capacitor with short leads mounted close to the device package (see Figure 9 and Figure 10). Connection Diagrams VDD 0.1 µF TSL1402R 1 2 3 4 5 6 7 SI CLK VDD SI1 CLK AO1 GND SO2 VDD NC SO1 GND NC SI2 NC AO2 14 13 12 11 10 9 8 AO Figure 9. Serial Connection VDD TSL1402R 0.1 µF 1 2 3 4 5 6 7 Si CLK AO1 (Pixels 1–128) VDD SI1 CLK AO1 GND SO2 VDD NC SO1 GND NC SI2 NC AO2 14 13 12 11 10 9 8 AO2 (Pixels 129–256) Figure 10. Parallel Connection The LUMENOLOGY Company Copyright 2002, TAOS Inc. www.taosinc.com 9 TSL1402R 256 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS041 – AUGUST 2002 MECHANICAL INFORMATION This assembly consists of 2 sensor chips mounted on a printed-circuit board in a clear molded plastic package. TOP VIEW 19.30 18.29 Sensors CL Sensors 3.62 to Pin 1 3.92 ÉÉÉÉÉÉÇÇÇÇÇ Pixel 1 0.53 to Pin 1 0.28 10.67 9.65 Pin 1 Indicator END VIEW SIDE VIEW 3.18 2.79 Top of Die to 0.89 Top of Package 1.29 ÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏ 14 4.60 MIN ÏÏÏÏÏÏ ÏÏÏÏÏÏ 14 14 0.50 0.00 0.508 0.406 BOTTOM VIEW 1.90 0.76 1 2 3 4 5 6 7 14 13 12 11 10 9 8 7.87 7.37 2 2.16 1.42 ÌÌÌÌÌ ÌÌÌÌÌ ÌÌÌÌÌ ÌÌÌÌÌ ÌÌÌÌÌ ÌÌÌÌÌ ÌÌÌÌÌ 12 2.54 Nonaccumulative See Note B NOTES: A. All linear dimensions are in millimeters. B. The true-position spacing is 2.54 mm between lead centerlines. Each pin centerline is located within 0.25 mm of its true longitudinal positions. C. Index of refraction of clear plastic is 1.52. D. This drawing is subject to change without notice. Figure 11. Packaging Configuration Copyright 2002, TAOS Inc. The LUMENOLOGY Company 10 www.taosinc.com TSL1402R 256 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS041 – AUGUST 2002 PRODUCTION DATA — information in this document is current at publication date. Products conform to specifications in accordance with the terms of Texas Advanced Optoelectronic Solutions, Inc. standard warranty. Production processing does not necessarily include testing of all parameters. NOTICE Texas Advanced Optoelectronic Solutions, Inc. (TAOS) reserves the right to make changes to the products contained in this document to improve performance or for any other purpose, or to discontinue them without notice. Customers are advised to contact TAOS to obtain the latest product information before placing orders or designing TAOS products into systems. TAOS assumes no responsibility for the use of any products or circuits described in this document or customer product design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that the circuits are free of patent infringement. TAOS further makes no claim as to the suitability of its products for any particular purpose, nor does TAOS assume any liability arising out of the use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, INC. PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN CRITICAL APPLICATIONS IN WHICH THE FAILURE OR MALFUNCTION OF THE TAOS PRODUCT MAY RESULT IN PERSONAL INJURY OR DEATH. USE OF TAOS PRODUCTS IN LIFE SUPPORT SYSTEMS IS EXPRESSLY UNAUTHORIZED AND ANY SUCH USE BY A CUSTOMER IS COMPLETELY AT THE CUSTOMER’S RISK. LUMENOLOGY is a registered trademark, and TAOS, the TAOS logo, and Texas Advanced Optoelectronic Solutions are trademarks of Texas Advanced Optoelectronic Solutions Incorporated. The LUMENOLOGY Company Copyright 2002, TAOS Inc. www.taosinc.com 11 TSL1402R 256 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS041 – AUGUST 2002 Copyright 2002, TAOS Inc. The LUMENOLOGY Company 12 www.taosinc.com