APL3540 High-Side Power Distribution Controller General Description Features • APL3540 is a high-side power distribution controller for an external N-channel MOSFET, allow for +12V and +19V High-Side Driver for an External N-Channel MOSFET • • • • • • • • power-supply rails. The wrong input voltage protection function protects a wrong input adapter insertion. When Under-Voltage Lockout (UVLO) Wrong VIN Input Voltage Protection input voltage is out of the target input voltage range, the IC is off. Output Under-Voltage Protection (UVP) Short-Circuit Protection During Power-Up (SCP) The built-in under-voltage protection monitors the output voltage for short-circuit conditions. When output voltage Over-Current Protection (OCP) Shutdown Function is less than 70% of VIN voltage, the IC will be shut down. The over-current protection monitors the output current Power-Ok (POK) Function by using the voltage drop across the external MOSFET’s RDS(ON). When output current reaches the trip point, the IC Lead Free and Green Devices Available (RoHS Compliant) will be shut down. The APL3540 also provides a shortcircuit protection during power-up. The device monitors Applications • DRV and VOUT voltages for a short-circuit detection. If a short-circuit condition is detected, the IC will be shut Desktop PCs down. Other features, including a POK output which indicates that the output voltage is ready and a logic-controlled shutdown mode. Pin Configuration 8 VINSEL VIN 1 VIN 1 8 VINSEL OCSET 2 7 POK OCSET 2 7 POK DRV 3 6 GND DRV 3 6 GND VOUT 4 5 EN VOUT 4 5 EN TDFN2x2-8 (Top View) SOP-8 (Top View) =Exposed Pad (Please connect to the ground) ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.9 - Oct., 2013 1 www.anpec.com.tw APL3540 Ordering and Marking Information Package Code K : SOP-8 QB : TDFN2x2-8 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel SCP Threshold Code 26 : 2.6V 28 : 2.8V 30 : 3.0V Blanking : 3.5V Assembly Material G : Halogen and Lead Free Device APL3540 Assembly Material Handling Code Temperature Range Package Code SCP Threshold Code APL3540 K : APL3540 XXXXX APL3540 QB : 3540 X APL3540 XXXXX SS 3540 X SS XXXXX - Date Code SS : SCP Threshold Code X - Date Code SS : SCP Threshold Code Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant)and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings (Note 1) Symbol VIN Parameter VIN Input Voltage (VIN to GND) VOUT, VDRV, VOCSET, VPOK, VOUT, DRV, POK, OCSET and VINSEL to GND Voltage VVINSEL VEN TJ EN to GND Voltage Rating Unit -0.3 to 35 V -0.3 to 40 V -0.3 to 7 Maximum Junction Temperature TSTG Storage Temperature TSDR Maximum Lead Soldering Temperature,10 Seconds V 150 o -65 to 150 o 260 o C C C Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics (Note 2) Symbol θJA Parameter Typical Value Unit Junction-to-Ambient Resistance in Free Air SOP-8 TDFN2x2-8 150 80 o C/W Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Copyright ANPEC Electronics Corp. Rev. A.9 - Oct., 2013 2 www.anpec.com.tw APL3540 Recommended Operating Conditions (Note 3) Symbol Parameter VIN VIN Input Voltage (VIN to GND) VEN EN to GND Voltage Range Unit 10 to 26 V 0 to 5 V TA Ambient Temperature -40 to 85 o TJ Junction Temperature -40 to 125 o C C Note 3: Refer to the typical application circuit Electrical Characteristics Unless otherwise specified, these specifications apply over VIN=19V, VEN =5V and TA= -40 to 85 oC. Typical values are at TA=25oC. Symbol Parameter APL3540 Test Conditions Unit Min. Typ. Max. 7.0 7.5 8.0 V 0.3 0.4 0.5 V VIN >VUVLO, VEN=5V, and VVINSEL(H)>VVINSEL> VVINSEL(L) 5 8.5 12 ms No load, VEN =5V - 750 1200 µA No load, VEN =0V - 400 600 µA UNDER-VOLTAGE LOCKOUT (UVLO) AND SUPPLY CURRENT VUVLO VIN UVLO Threshold Voltage VIN rising, TA= -40 to 85 oC VIN UVLO Hysteresis TD(ON) IVIN Power-On Delay Time VIN Supply Current WRONG VIN INPUT VOLTAGE PROTECTION VVINSEL(L) VVINSEL(H) VINSEL Low Detection Rising Threshold VIN rising, IC is on, VIN=10V to 21V 1.223 1.275 1.305 V VINSEL Low Detection Falling Threshold VIN falling, IC is off, VIN=10V to 21V 1.148 1.200 1.230 V VINSEL High Detection Rising Threshold VIN rising, IC is off, VIN=10V to 21V 1.748 1.800 1.830 V VINSEL High Detection Falling Threshold VIN falling, IC is on, VIN=10V to 21V 1.673 1.725 1.755 V VINSEL Input Current VVINSEL=40V - - 1 µA VINSEL Low Detection Debounce VVINSEL falling, VVINSEL < VVINSEL(L) - 10 - µs VINSEL High Detection Debounce VVINSEL rising, VVINSEL > VVINSEL(H) - 10 - µs GATE DRIVER VDRV-OUT DRV to VOUT Voltage VDRV-VOUT, VIN=19 4.3 4.6 4.9 V DRV Source Current VDRV=10V, VDRV-VOUT=2.5 155 185 215 µA DRV Discharge Resistance Any fault condition and shutdown (connected from DRV to VOUT), VDRV=5V, VOUT=GND 1.8 2.0 2.2 kΩ 65 70 75 % - 5 - µs 45 50 55 µA -10 0 10 mV - 10 - µs PROTECTIONS Under-Voltage Protection Threshold VOUT falling, VOUT/VIN Under-Voltage Protection Debounce IOCSET OCSET Source Current No load, VVINSEL=1.5V, VEN=5V, VOCSET=18.9V OCSET Offset Voltage Over-Current Debounce Copyright ANPEC Electronics Corp. Rev. A.9 - Oct., 2013 3 www.anpec.com.tw APL3540 Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VIN=19V, VEN =5V and TA= -40 to 85 oC. Typical values are at TA=25oC. Symbol Parameter APL3540 Test Conditions Unit Min. Typ. Max. -100 - +100 mV PROTECTIONS (CONT.) VDRV(SC) Short Circuit Protection Threshold Accuracy VDRV -VOUT SCP threshold tunable range: 2.5~3.5V, 0.1V/step VOUT Input Current VOUT=19V - 60 80 µA VOUT Discharge Resistance Any fault condition and shutdown, VOUT=1V 1.5 1.75 2.0 kΩ EN Logic High Threshold Voltage VIN=10V to 21V EN INPUT 0.8 - 1.5 V EN Hyteresis - 0.2 - V EN Pull-up Current - 5 - µA POK OUTPUT VPOK(TH) TD(POK) POK Threshold VOUT rising, VOUT/VIN, VPOK=High 85 90 95 % POK Hysteresis VOUT falling, VPOK=Low - 5 - % POK Low Voltage IPOK=10mA - 0.2 0.5 V POK Leakage Current VPOK=40V - - 1 µA POK Rising Delay Time VOUT rising, POK assertion 8 11.5 15 ms Copyright ANPEC Electronics Corp. Rev. A.9 - Oct., 2013 4 www.anpec.com.tw APL3540 Typical Operating Characteristics VINSEL Detection Threshold Voltage vs. Input Voltage Supply Current vs. Input Voltage EN=High 600 500 EN=Low 400 300 VIN =19V, RLOAD =100Ω, CIN =0.1µF/X7R, COUT =1500µF/Electrolytic, 200 8 VIN UVLO Threshold Voltage, VUVLO (V) VINSEL Detection Threshold, VVINSEL (V) 700 12 16 20 24 28 32 TA=25oC 2.5 2.0 VVINSEL (H) 1.5 VVINSEL (L) 1.0 0.5 0.0 10 15 20 25 30 35 Input Voltage (V) Input Voltage (V) VIN UVLO Threshold Voltage vs. Junction Temperature VINSEL Detection Threshold Voltage vs. Junction Temperature 8.5 8.0 VIN Rising 7.5 7.0 VIN Falling 6.5 6.0 -50 3.0 36 VINSEL Detection Threshold, VVINSEL (V) Supply Current , IVIN (µA) 800 0 50 100 150 Junction Temperature ( oC) Copyright ANPEC Electronics Corp. Rev. A.9 - Oct., 2013 2.0 1.9 VVINSEL (H) 1.8 1.7 1.6 1.5 1.4 1.3 1.2 VVINSEL (L) 1.1 1.0 -50 0 50 100 150 Junction Temperature ( oC) 5 www.anpec.com.tw APL3540 Operating Waveforms The test condition is VIN=19V, TA=25oC unless otherwise specified. Power On Power Off VIN VIN 1 1 VDRV VOUT VOUT 3 3 4 VDRV 2 2 VPOK VPOK 4 VIN =19V, RLOAD =100Ω, R3 =51kΩ, CIN =0.1µF/X7R, C OUT =1500µF/Electrolytic, CH1: VIN, 5V/Div, DC CH2: VDRV, 5V/Div, DC CH3: VOUT, 5V/Div, DC CH4: VPOK, 10V/Div, DC TIME: 10ms/Div VIN =19V, RLOAD =100Ω, R3 =51kΩ, CIN =0.1µF/X7R, C OUT =1500µF/Electrolytic, CH1: VIN, 5V/Div, DC CH2: VDRV, 5V/Div, DC CH3: VOUT, 5V/Div, DC CH4: VPOK, 10V/Div, DC TIME: 0.5s/Div Enable Disable VEN VE N 1 1 VDRV VOUT VIN V POK VDRV 2 2 VOUT VOUT 3 3 4 VPOK 4 VIN =19V, RLOAD =100Ω, R3 =51kΩ, CIN =0.1µF/X7R, C OUT =1500µF/Electrolytic, CH1: VEN, 5V/Div, DC CH2: VDRV, 5V/Div, DC CH3: VOUT, 5V/Div, DC CH4: VPOK, 10V/Div, DC TIME: 5ms/Div Copyright ANPEC Electronics Corp. Rev. A.9 - Oct., 2013 VIN =19V, RLOAD =100Ω, R3 =51kΩ, CIN =0.1µF/X7R, C OUT =1500µF/Electrolytic, CH1: VEN, 5V/Div, DC CH2: VDRV, 5V/Div, DC CH3: VOUT, 5V/Div, DC CH4: VPOK, 10V/Div, DC TIME: 50ms/Div 6 www.anpec.com.tw APL3540 Operating Waveforms (Cont.) The test condition is VIN=19V, TA=25oC unless otherwise specified. Soft-Start Over-Current Protection VB A T VIN VDRV VDRV VOUT 1 1 VIN V OUT V CHRIN 2 3 2 IOUT 3 4 IOUT 4 VIN =19V, R LOAD =100Ω, C1=100nF, CIN =0.1µF/X7R, C OUT =1500µF/Electrolytic, CH1: VIN, 5V/Div, DC CH2: VDRV, 5V/Div, DC CH3: VOUT, 5V/Div, DC CH4: IOUT, 1A/Div, DC TIME: 10ms/Div IOUT VIN =19V, R LOAD =1Ω, ROCSET =1.5kΩ, CIN =0.1µF/X7R, COUT =470µF/Electrolytic, CH1: VIN, 10V/Div, DC CH2: VDRV, 10V/Div, DC CH3: VOUT, 10V/Div, DC CH4: IOUT, 10A/Div, DC TIME: 0.5ms/Div Wrong VIN Input Voltage Protection, Short-Circuit Protection VVINSEL > VVINSEL(H) 1 V IN VDRV 2 VOUT 3 VIN 1 VDRV and V OUT 2,3 IOUT 4 VIN =19V, RLOAD =Short to GND before power-up, CIN =0.1µF/X7R, C OUT =470µF/Electrolytic CH1: VIN, 10V/Div, DC CH2: VDRV, 5V/Div, DC CH3: VOUT, 5V/Div, DC CH4: IOUT, 10A/Div, DC TIME: 2ms/Div Copyright ANPEC Electronics Corp. Rev. A.9 - Oct., 2013 VIN =25V, R1=24kΩ, R2 =2kΩ CH1: VIN, 5V/Div, DC CH2: VDRV, 5V/Div, DC CH3: VOUT, 5V/Div, DC TIME: 50ms/Div 7 www.anpec.com.tw APL3540 Operating Waveforms (Cont.) The test condition is VIN=19V, TA=25oC unless otherwise specified. Wrong VIN Input Voltage Protection, VVINSEL < VVINSEL(L) VDRV VIN V OUT VIN V POK 1 VDRV and V OUT 2,3 VIN =12V, R1=24kΩ, R2 =2kΩ CH1: VIN, 5V/Div, DC CH2: VDRV, 5V/Div, DC CH3: VOUT, 5V/Div, DC TIME: 20ms/Div Pin Description PIN FUNCTION NO. NAME 1 VIN Input Supply Pin. Provides power to the IC, VIN can range from 10V to 21V and should be bypassed with at least a 0.1µF capacitor. 2 OCSET Over-Current Trip Point Adjustment Pin. Connect a resistor (ROCSET) from this pin to the drain of the external MOSFET to set the OCP trip point. 3 DRV 4 VOUT 5 EN 6 GND Ground. 7 POK Power-Okay Indicator Output. The POK is an open-drain pull-down device. When VOUT voltage is below the POK threshold, the POK output is pulled low; when VOUT voltage is above the POK threshold, the POK output is high impedance. 8 VINSEL Input Voltage Sense Pin. Connect a resistive divider from VIN to VINSEL to GND to monitor the input voltage. This pin cannot be left floating. Gate Driver Output. The gate driver for the external N-channel MOSFET. Output Voltage Sense Pin. Connect this pin to the source of external N-channel MOSFET to monitor the output voltage. Enable Input. Pulling the VEN above 2V will enable the IC; pulling VEN below 0.6V will disable the IC. This pin is pulled high by an internal current source. Copyright ANPEC Electronics Corp. Rev. A.9 - Oct., 2013 8 www.anpec.com.tw APL3540 Block Diagram 5V LDO GND Bias+Band-Gap UVLO VIN POK TD(ON) EN 5V OCSET OCP POK_WD Logic Control 1.275V VOUT VOUT VDRV VINSEL SCP 2.5~3.5V, 0.1V/step Clock Generator 1.8V Charge Pump and Gate Driver DRV 5V POK_WD POK POK VOUT VOUT TD(POK) VINx0.7 UVP VINx0.9 Typical Application Circuit Adapter 19V C2 1nF 2 ROCSET 4kΩ R5 4.7Ω (option) Q1 IPD09N03L 1 VINSEL R2 2kΩ 1% VIN CIN 0.1µF 3 RG 47Ω OCSET DRV EN COUT 470µF Copyright ANPEC Electronics Corp. Rev. A.9 - Oct., 2013 5 OFF C1 68nF 4 R3 50kΩ ON APL3540 POK VOUT R1 23.2kΩ 1% 8 VOUT 7 GND 6 9 www.anpec.com.tw APL3540 Function Description Wrong VIN Input Voltage Protection The APL3540 provides an input voltage detection func- When the voltage across the MOSFET exceeds the voltage drop across the R OCSET, an over-current will be tion to protect a wrong input adapter insertion. Connect a resistive divider from VIN to VINSEL to GND to set the detected. The threshold of the over current is therefore given by: target input voltage. The target input voltage is set at: IOCP= IOCSET x ROCSET / RDS(ON) VIN(target)=1.5V x (1+R1/R2) For the over-current is never occurred in the normal oper- The IC is enabled when input voltage is within the VIN(target) ating load range, the variation of all parameters in the above equation should be determined. ±15% (V IN also must above VUVLO and EN is high); the device shuts down when input voltage is outside the VIN - The MOSFET’s RDS(ON) is varied by temperature, the user should determine the maximum RDS(ON) in manufacturer’s datasheet. - The minimum IOCSET (45µA) and minimum ROCSET should be used in the above equation. An over-current condition will shut down the device and pull the VDRV-OUT to low, the VOUT voltage is also discharged ±20%. (target) Power-Up The APL3540 has a built-in under-voltage lockout circuitry to keep the DRV output shutting off until internal circuitry operates properly. The UVLO circuit has a hysteresis and a de-glitch feature so that it will typically ignore under- to the GND by an internal resistor, requiring a VIN UVLO or EN re-enable again to restart IC. Note that the OCP is shoot transients on the input. When input voltage exceeds the UVLO threshold (VIN also must within the V IN(target)±10% active after the power-up and POK are asserted. and EN is high) and after 7ms delay time, the DRV output starts to charge the C1. POK Output The power okay function monitors the output voltage and The voltage at DRV rises with a slope equals to 185µA/ C1 and the VOUT output voltage rise time is set at: drives the POK low to indicate a fault. When a fault condition such as over-current or under-voltage is occurred, TSS=C1 x VIN / 185µA the VOUT output voltage falls to 85% of VIN input voltage and the POK is pulled low. When the VOUT output volt- where TSS is the rise time of VOUT output voltage age reaches to 90% of VIN input voltage and after 10ms delay time, the POK is pulled high. Since the POK is an Under-Voltage Protection (UVP) open-drain device, connecting a resistor to a pull high voltage is necessary. The VOUT pin monitors the output voltage. If the VOUT is under 70% of VIN input voltage because of the short cir- Short-Circuit Protection cuit or other influences, it will cause the under-voltage protection and turn off IC, the VOUT voltage is also dis- The APL3540 monitors DRV and VOUT voltages for the short circuit detection during power-up. When the differ- charged to the GND by an internal resistor, requiring a VIN UVLO or EN re-enable again to restart IC. Note that ence in voltage between DRV pin and VOUT pin is above short circuit protection threshold, a short-circuit condition the UVP is active after the power-up and POK are asserted. Over-Current Protection (OCP) is detected and the device will be shut down. Requiring a VIN UVLO or EN re-enable again to restart IC. The APL3540 monitors the voltage across the external MOSFET and uses the OCSET pin to set the over-current trip point. Caution must be taken when selecting a power MOSFET. If an unsuitable MOSFET is used, the SCP will be falsely A resistor (ROCSET) connected between OCSET pin and the drain of the MOSFET will determine the over current activated during power-up. A complete power-up partly relies on the current driving capacity of the MOSFET. In trip point. An internal 50µA current source will flow through this resistor, creating a voltage drop, which will be com- the startup of VDRV while gate voltage starts to rise, the MOSFET starts to conduct. If the current via the MOSFET pared with the voltage across the MOSFET. is insufficient to supply for the needs of COUT and RLOAD, Copyright ANPEC Electronics Corp. Rev. A.9 - Oct., 2013 10 www.anpec.com.tw APL3540 Function Description (Cont.) Short-Circuit Protection (Cont.) the VOUT voltage will not follow the VDRV to rise, eventually, when VDRV - VOUT > short circuit protection threshold, the SCP happens. Since the COUT demands the most current during power-up, the supplying current via the MOSFET should satisfy the following equation for a completion of power-up. ISUPPLY(max) > ICHARGING where: ICHARGING = COUT x (185µA/C1) • I SUPPLY(max) is the maximum supply current via the MOSFET in the conditions of VGS = short circuit protection threshold and VDS = VIN -VOUT . • ICHARGING is the charging current of COUT during soft-start. • COUT is output capacitor. • C1, placed on the gate of MOSFET is the capacitor that controls the ramp-up rate of output voltage during softstart. • 185µA is the soft-start current driving from the DRV pin during the power-up process. For example, If COUT=1500µF, C1=100nF, short circuit protection threshold=3.0V and VIN=19V, the ICHARGING demanded by the output capacitor is 2.78A. The ISUPPLY(max) in the conditions of VGS = 3.0V and VDS = 19V (while VIN -VOUT ≒ VIN) should be greater than the ICHARGING. We set the safety margin that is 1.5 times greater than the demanded 2.78A, therefore, we can choose a MOSFET that can deliver at least 4.17A in such conditions. Shutdown Control The APL3540 has an active-low shutdown function. Pulling the VEN above 2V will enable the IC; pulling VEN below 0.6V will disable the IC and the POK is pulled low immediately (ignore the VPOK(TH) and TD(POK)), the VOUT voltage is also discharged to the GND by an internal resistor. EN pin is pulled high by an internal current source and can be left floating. Copyright ANPEC Electronics Corp. Rev. A.9 - Oct., 2013 11 www.anpec.com.tw APL3540 Application Information avoid oscillation. The RG can be in the range of 10~100Ω. Input Capacitor The recommended value is 47Ω. While hot plug-in an AC adapter, the inductive peak voltage seen in the VIN pin could be very high if there is no Power MOSFETs any filtering measure taken. It is recommended to place a 0.1 to 1µF ceramic bypass capacitor as close as possible APL3540 requires an N-channel MOSFET that is utilized as an on/off switch. When a MOSEFT is selected, please make sure that the RDS(ON) of this MOSFET can meet your to the VIN pin. An RC-filter, depicted in the application circuit, is preferable because better performance in filter- maximum voltage droop requirement in full load conditions. And also make sure that the MOSFET you ing the peak voltage and noise. Note that the voltage rating of the input capacitor must be greater than the maxi- select can satisfy the current delivering requirement, described in the paragraph of Short-Circuit Protection in mum VIN voltage. Function Description. Another important criterion for selection of MOSFET is the MOSFET must be operated within Gate and Output Capacitor It is recommended to place a capacitor in the gate of ex- its safe operation area in your application. The package type of the MOSFET must be chosen for efficient heat ternal power MOSFET to control the soft-start rate of output voltage, especially when a high-value output capaci- removal. Note that the VDS rating of the MOSFET you selected must be greater than the VIN voltage and the VGS tor is used. The gate capacitor can reduce the inrush current to the output capacitor during soft-start. If the power rating must be greater than VIN+5V. The power dissipated in the MOSFET while on is shown in the following supply cannot support the inrush current, the COUT voltage will be clamped during soft-start and SCP will be falsely equation: activated. The inrush current must be controlled within power supply current capability by using this gate capacitor. PD = IO2 x RDS(on) Note that the voltage rating of the gate capacitor must be greater than the maximum VDRV voltage, where the VDRV Select a package type and heatsink that maintains the junction temperature below the rating. approximately equals VIN+5V. Layout Consideration A bulk output capacitor, placed close to the load, is recommended to support load transient current. Precautions Figure 1 illustrates the layout, with bold lines indicating should be taken when a high-value output capacitor is used the gate capacitor C1 (shown in the application high current paths; and these traces must be short and wide. The layout guidelines are listed as below. circuit) must be matched. A high-value output capacitor with a small-value C1 would probably lead to inrush cur- 1. Place the input capacitors CIN for VIN near pin as close as possible. rent and end up SCP latched-off in the soft-start period. Please make sure that the gate capacitor C1 is matched 2. The trace from DRV to the gate of power MOSFETs should be wide and short. with a high-value output capacitor. Note that the voltage rating of the output capacitor must be greater than the 3. Place output capacitor COUT near the load as close as possible. maximum VIN voltage. 4. Large current paths must have wide and thick traces, depicted as the bold lines. Gate Resistor 5. The drain of the power MOSFETs should be a large plane for heatsinking. It is recommended to place a resistor RG, as shown in the Typical Application Circuit, in the gate of external power MOSFET to prevent occurrence of oscillation during powering on. If the oscillation occurs, the SCP or VINSEL wrong voltage detection might be activated unexpectedly. The RG literally could stabilize the external MOSFET to Copyright ANPEC Electronics Corp. Rev. A.9 - Oct., 2013 12 www.anpec.com.tw APL3540 Application Information (Cont.) Layout Consideration (Cont.) VIN CIN ROCSET VIN OCSET DRV C1 APL3540 VOUT GND COUT Load Figure 1. Layout Guidelines Copyright ANPEC Electronics Corp. Rev. A.9 - Oct., 2013 13 www.anpec.com.tw APL3540 Package Information SOP-8 D E E1 SEE VIEW A h X 45 ° 0.25 A2 c A b e NX GAUGE PLANE SEATING PLANE aaa C L VIEW A S Y M B O L SOP-8 INCHES MILLIMETERS MIN. MAX. A MIN. MAX. 1.75 0.069 0.010 0.004 0.25 A1 0.10 A2 1.25 b 0.31 0.51 0.012 0.020 c 0.17 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 5.80 6.20 0.228 0.244 E1 3.80 4.00 0.150 0.157 e 0.049 1.27 BSC 0.050 BSC h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 0 0° 8° 0° aaa 0.10 8° 0.004 Note: 1. Follow JEDEC MS-012 AA. 2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension “E” does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.9 - Oct., 2013 14 www.anpec.com.tw APL3540 Package Information TDFN2x2-8 D b E A A1 D2 A3 NX aaa c E2 SEATING PLANE L K Pin 1 Corner e S Y M B O L TDFN2x2-8 INCHES MILLIMETERS MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 A3 0.008 REF 0.20 REF b 0.18 0.30 0.007 0.012 D 1.90 2.10 0.075 0.083 0.063 D2 1.00 1.60 0.039 E 1.90 2.10 0.075 0.083 E2 0.60 1.00 0.024 0.039 0.45 0.012 e 0.50 BSC L 0.30 K 0.20 aaa 0.020 BSC 0.018 0.008 0.08 0.003 Note : 1. Followed from JEDEC MO-229 WCCD-3. Copyright ANPEC Electronics Corp. Rev. A.9 - Oct., 2013 15 www.anpec.com.tw APL3540 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application A H 330.0±2.00 50 MIN. T1 C d D W E1 12.4+2.00 13.0+0.50 -0.00 -0.20 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 P0 P1 P2 4.0±0.10 8.0±0.10 2.0±0.05 A H SOP-8 Application 178.0±2.00 50 MIN. D1 1.5 MIN. 5.5±0.05 T A0 B0 K0 0.6+0.00 -0.40 6.40±0.20 5.20±0.20 2.10±0.20 T1 C d D W E1 F 8.4+2.00 13.0+0.50 -0.00 -0.20 1.5 MIN. 20.2 MIN. 8.0±0.20 1.75±0.10 3.50±0.05 P0 P1 P2 4.0±0.10 4.0±0.10 2.0±0.05 TDFN2x2-8 D0 1.5+0.10 -0.00 F D0 1.5+0.10 -0.00 D1 T 0.6+0.00 1.5 MIN. -0.4 A0 B0 K0 3.35 MIN 3.35 MIN 1.30±0.20 (mm) Devices Per Unit Package Type Unit Quantity SOP-8 Tape & Reel 2500 TDFN2x2-8 Tape & Reel 3000 Copyright ANPEC Electronics Corp. Rev. A.9 - Oct., 2013 16 www.anpec.com.tw APL3540 Taping Direction Information SOP-8 USER DIRECTION OF FEED TDFN2x2-8 USER DIRECTION OF FEED Copyright ANPEC Electronics Corp. Rev. A.9 - Oct., 2013 17 www.anpec.com.tw APL3540 Classification Profile Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Copyright ANPEC Electronics Corp. Rev. A.9 - Oct., 2013 18 www.anpec.com.tw APL3540 Classification Reflow Profiles (Cont.) Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.9 - Oct., 2013 19 www.anpec.com.tw