APL3542A High-Side Power Distribution Controller General Description Features • APL3542A is a high-side power distribution controller for an external N-channel MOSFET, allow for +12V, +19V or High-Side Driver for an External N-Channel MOSFET • • • • • • • • • +5V power-supply rail. The wrong input voltage protection function protects a wrong input adapter insertion, when Under-Voltage Lockout (UVLO) Wrong VIN Input Voltage Protection input voltage is out of the target input voltage range the IC is off. Output Under-Voltage Protection (UVP) Short-Circuit Protection During Power-up (SCP) The over-current protection monitors the output current by using the voltage drop across the external sensing Over-Current Protection (OCP) Selectable VIN Monitor Voltage resistor, when output current reaches the trip point the IC will be shut down. The APL3542A also provides a short- Shutdown Function circuit protection during power-up. The device monitors VOUT voltages for a short-circuit detection, if a short-cir- Power Okay (POK) Function Lead Free and Green Devices Available cuit condition is detected the IC will be shut down. Other features include a POK output to indicate the out- (RoHS Compliant) put voltage is ready, and a logic-controlled shutdown mode. Pin Configuration Applications • • AIO Computers Notebooks VCNTL 1 10 VINSEL VIN 2 ISENSE 3 9 EN EP (GND) 8 POK DRV 4 7 OCSET OUT 5 6 DELAY TDFN3x3-10 (Top View) =Exposed Pad. Power’s and signal’s return path. Connect this pad to large copper area for better heat dissipation. ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2014 1 www.anpec.com.tw APL3542A Ordering and Marking Information APL3542A Assembly Material Handling Code Temperature Range Package Code APL3542A QB : APL 3542A XXXXX Package Code QB : TDFN 3x3-10 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device XXXXX - Date Code Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant)and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings (Note 1) Symbol Parameter Rating Unit VIN VVCNTL VIN, VCNTL Input Voltage (VIN to GND) -0.3 to 40 V VOUT, VDRV, VVINSEL VOUT, DRV, and VINSEL to GND Voltage -0.3 to 40 V -0.3 to 7 V VEN, VPOK, ,VOCSET, EN, POK, OCSET, DELAY to GND Voltage VDELAY TJ Maximum Junction Temperature TSTG Storage Temperature TSDR Maximum Lead Soldering Temperature (10 Seconds) 150 o -65 to 150 o 260 o C C C Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics (Note 2) Symbol θJA Parameter Typical Value Junction-to-Ambient Resistance in free air 60 Unit o C/W Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2014 2 www.anpec.com.tw APL3542A Recommended Operating Conditions (Note 3) Symbol VIN VVCNTL VOUT, VVINSEL Parameter Range Unit VIN, VCNTL Input Voltage (VIN to GND) 5 to 26 V VOUT, and VINSEL to GND Voltage 0 to 26 V 0 to 5 V VEN, VPOK, ,VOCSET, EN, POK, OCSET, DELAY to GND Voltage VDELAY TA TJ Ambient Temperature Junction Temperature -40 to 85 o -40 to 125 o C C Note 3: Refer to the typical application circuit Electrical Characteristics Unless otherwise specified, these specifications apply over VIN=19V, VEN =5V and TA= -40 to 85 oC. Typical values are at TA=25oC. Symbol Parameter APL3542A Test Conditions Unit Min Typ Max - 4.3 - V - 0.3 - V VCNTL >VUVLO, VEN=5V, and VVINSEL(H)>VVINSEL> VVINSEL(L) - 30 - ms No load, VEN =5V, - 500 750 µA No load, VEN =0V - 20 40 µA UNDER-VOLTAGE LOCKOUT (UVLO) AND SUPPLY CURRENT VUVLO VCNTL UVLO Threshold Voltage VCNTL rising, TA= -40 to 85 oC VCNTL UVLO Hysteresis TD(ON) Power-On Delay Time IVICNTL VCNTL Supply Current WRONG VIN INPUT VOLTAGE PROTECTION VVINSEL(L) VVINSEL(H) VINSEL Low Detection Rising Threshold VINSEL rising, IC is on, VIN=5V to 21V 0.625 0.650 0.665 V VINSEL Low Detection Falling Threshold VINSEL falling, IC is off, VIN=5V to 21V 0.575 0.600 0.615 V VINSEL High Detection Rsing Threshold VINSEL rising, IC is off, VIN=5V to 21V 2.145 2.200 2.232 V VINSEL High Detection Falling Threshold VINSEL falling, IC is on, VIN=5V to 21V 2.048 2.100 2.132 mV VINSEL Input Current VVINSEL=40V - - 1 µA VINSEL Voltage Detection Disable Threshold By pulling VINSEL low to disable VINSEL voltage detection, VIN=5V to 21V - - 0.3 V VDRV-VOUT - 5 - V DRV Source Current VDRV=10V, VDRV-VOUT=2.5V - 450 - µA DRV Discharge Resistance Any fault condition and shutdown (connected from DRV to VOUT) - 50 - Ω 80 85 90 % ms GATE DRIVER VDRV-OUT DRV to VOUT Voltage PROTECTIONS Under-Voltage Protection Threshold VOUT falling, VOUT/VIN (UVP is enabled after POK asserted high) - 1 - - - - OCP Debounce Time - 10 - OCP No Debounce Threshold - 1.5*IOCP - Under-Voltage Protection Debounce IOCP OCP Threshold TOCP Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2014 IOCP=(VVIN-VISENSE)*GM 3 ms www.anpec.com.tw APL3542A Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VIN=19V, VEN =5V and TA= -40 to 85 oC. Typical values are at TA=25oC. Symbol Parameter APL3542A Test Conditions Unit Min Typ Max PROTECTIONS VOUT Input Current VOUT=19V - 60 80 µA VOUT Discharge Resistance Discharge during any fault condition or shutdown - 50 - Ω Over Temperature Protection - 135 - o Over Temperature Protection Hysteresis - 50 - o EN Logic Input Threshold 0.9 1.25 1.6 EN Input Logic Hyteresis - 0.2 - V EN Pull-up Current - 4 - µA C C EN Input V POK Output VPOK(L) TD(POK) - 0.3 - V 80 85 90 % - - 0.5 V POK In From Lower VOUT rising, VIN-VOUT, VPOK=High POK Low threshold VOUT falling from normal, VPOK=Low POK Low Voltage IPOK=10mA POK Leakage Current VPOK=40V - - 1 µA VOUT rising, POK assertion 7 10 13 ms Pre-charge Current VIN-VOUT>1V - 100 - mA Pre-charge Reset Time From the occurrence of SCP to the next pre-charge start - 30 - ms Pre-charge Re-try Times during Short-Circuit - 4 - time DELAY Source Current - 2.4 - µA DELAY pin Pre-SCP Threshold - 1.8 - V POK Rising Delay Time Pre-Charge Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2014 4 www.anpec.com.tw APL3542A Typical Operating Characteristics VINSEL Detection Threshold Voltage vs. VCNTL Supply Voltage VCNTL Supply current vs. VCNTL Supply Voltage 800 VINSEL Detection Threshold, VVINSEL (V) VCNTL Supply Current , IVCNTL (µA) 900 EN=High 700 600 500 400 300 TA=25oC 200 100 0 EN=Low 5 10 15 20 3.0 TA=25oC 2.5 2.0 VVINSEL(H) 1.5 VVINSEL(L) 1.0 0.5 0.0 25 5 VCNTL Supply Voltage (V) VINSEL Detection Threshold, VVINSEL (V) EN Input Logic Threshold Voltage (V) EN Input Logic High Threshold 1.2 1.0 EN Input Logic Low Threshold 0.8 0.6 0.4 TA=25oC 5 10 15 20 25 1.9 VINSEL High Detection Threshold 1.7 1.6 1.5 1.4 1.3 VINSEL Low Detection Threshold 1.2 1.1 1.0 -50 VINSEL Detection Threshold, VVINSEL (V) EN Input Logic Threshold Voltage (V) 1.0 EN Input Logic Low Threshold 0.6 0.4 VCNTL=19V 0 50 100 150 o Junction Temperature ( C) Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2014 100 150 Junction Temperature C) EN Input Logic High Threshold -50 50 POK Rising Delay Time vs. VCNTL Supply Voltage 1.2 0 0 (o 1.6 0.2 35 1.8 EN Input Logic Threshold Voltage vs. Junction Temperature 0.8 30 2.0 VCNTL Supply Voltage (V) 1.4 2 VINSEL Detection Threshold Voltage vs. Junction Temperature 1.4 0 15 VCNTL Supply Voltage (V) EN Logic Threshold Voltage vs. VCNTL Supply Voltage 0.2 10 12 11 10 9 8 7 6 5 5 10 15 20 25 VCNTL Supply Voltage (V) 5 www.anpec.com.tw APL3542A Typical Operating Characteristics OUT Pin Input Current vs. OUT Input Voltage 450 TA=25oC 400 60 DRV Output Current (µA) OUT Pin Input Current , IOUT (µA) 70 DRV Output Current vs. DRV Output Voltage 50 40 30 20 10 350 300 250 200 150 TA=25℃, VVCNTL=VVIN=19V, VOUT=14.5V 100 50 0 0 5 10 15 20 0 25 OUT Pin Input Voltage (V) 2 4 6 8 10 12 14 16 18 20 22 24 DRV Ouput Voltage (V) DRV Over-Drive Voltage, VDRV-VOUT (V) DRV Over-Drive Voltage vs. VCNTL Supply Voltage 6 5 4 3 2 TA=25℃, DRV Over-Drive Voltage=VDRV-VOUT 1 0 5 7 9 11 13 15 17 19 21 23 25 VCNTL Supply Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2014 6 www.anpec.com.tw APL3542A Operating Waveforms The test condition is TA= 25oC unless otherwise specified. Power On with POK Pulled High Power Off with POK Pulled High VIN VIN VDRV VDRV 1 1 VOUT V OUT 2,3 2,3 VPOK 4 VPOK 4 VIN =19V, CDRV =470nF, COUT =470µF, no load, EN open, POK tied to VIN via 100kΩ/36kΩ, VINSEL tied to VIN via 24kΩ/2kΩ. CH1: VIN, 10V/Div, DC CH2: VOUT , 10V/Div, DC CH3: VDRV, 10V/Div, DC CH4: VPOK, 5V/Div, DC TIME: 20ms/Div VIN =19V, CDRV =470nF, COUT =470µF, no load, EN open, POK tied to VIN via 100kΩ/36kΩ, VINSEL tied to VIN via 24kΩ/2kΩ. CH1: VIN, 10V/Div, DC CH2: VOUT , 10V/Div, DC CH3: VDRV, 10V/Div, DC CH4: VPOK, 5V/Div, DC TIME: 100ms/Div Power On with POK Open Power Off with POK Open VIN VIN VDRV V DRV 1 1 VOUT VOUT 2,3 2,3 I IN I IN 4 4 VIN =19V, CDRV =470nF, COUT =470µF, no load, EN open, POK open, VINSEL tied to VIN via 24kΩ/2kΩ. CH1: VIN, 10V/Div, DC VIN =19V, CDRV =470nF, COUT =470µF, no load, EN open, POK open, VINSEL tied to VIN via 24kΩ/2kΩ. CH1: VEN, 5V/Div, DC CH2: VOUT, 10V/Div, DC CH3: VDRV, 10V/Div, DC CH4: IIN, 0.5A/Div, DC TIME: 20ms/Div CH2: VDRV, 5V/Div, DC CH3: VOUT, 5V/Div, DC CH4: IIN, 0.5A/Div, DC TIME: 100ms/Div Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2014 7 www.anpec.com.tw APL3542A Operating Waveforms The test condition is TA= 25oC unless otherwise specified. Disable Enable VEN VEN VDRV 1 1 V DRV V OUT VOUT 2,3 2,3 I IN IIN 4 4 VIN =19V, CDRV =470nF, COUT =470µF, RLOAD=47Ω, POK pin open, VIN =19V, CDRV =470nF, COUT =470µF, RLOAD=47Ω, POK pin open, CH1: V EN, 5V/Div, DC CH2: V OUT, 10V/Div, DC CH3: VDRV, 10V/Div, DC CH4: IIN, 0.5A/Div, DC TIME: 20mA/Div CH1: V EN, 5V/Div, DC CH2: V OUT, 10V/Div, DC CH3: VDRV, 10V/Div, DC CH4: IIN, 0.5A/Div, DC TIME: 10mA/Div Short Circuit After Power On Short-Circuit Before Power On VIN VIN V DRV 1 1 VOUT VDRV 2 2,3 V DELAY 3 IIN I IN 4 4 VIN =19V, CDRV =470nF, COUT =470µF, EN pin open, POK pin open, RS=25mΩ, ROCSET=5kΩ, Output shorted to ground CH1: V IN, 10V/Div, DC CH2: V OUT, 10V/Div, DC CH3: VDRV, 10V/Div, DC CH4: IIN, 10A/Div, DC TIME: 50µA/Div VIN =19V, CDRV =470nF, COUT =470µF, CDELAY =0.1µF, EN pin open, POK pin open, Output shorted to ground then VIN power on CH1: VIN, 10V/Div, DC CH2: VDRV , 2V/Div, DC CH3: VDELAY, 5V/Div, DC CH4: IIN, 200mA/Div, DC TIME: 100ms/Div Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2014 8 www.anpec.com.tw APL3542A Operating Waveforms (Cont.) The test condition is TA= 25oC unless otherwise specified. OCP and Its Debounce Time VIN VDRV 1 VOUT 2,3 IIN 4 V IN =19V, CDRV =470nF, COUT =470µF, EN pin open, POK pin open, RS =25mΩ, ROCSET=5kΩ, ILOAD=8A CH1: VIN, 10V/Div, DC CH2: VOUT , 10V/Div, DC CH3: VDRV, 10V/Div, DC CH4: IIN, 5A/Div, DC TIME: 2ms/Div Pin Description PIN FUNCTION NO. NAME 1 VCNTL 2 VIN 3 Supply Voltage for internal circuits. Provide power to the internal 100mA current source and gate driver. ISENSE This pin is used to sample the voltage drop between VIN and ISENSE for sensing load current. 4 DRV Gate Driver Output. The gate driver for the external N-channel MOSFET. 5 VOUT Output Voltage Sense Pin. Connect this pin to the source of external N-channel MOSFET to monitor the output voltage. 6 DELAY Connecting a capacitor from this pin to ground sets the delay time which determines when SCP protection is activated. 7 OCSET Over-Current Trip Point Adjustment Pin. A resistor (ROCSET) from this pin to ground sets the OCP threshold. 8 POK Power Okay Indicator Output. The POK is an open-drain pull-down device. When VOUT voltage is below the POK threshold, the POK output is pulled low; when VOUT voltage is above the POK threshold, the POK output is in high impedance. 9 EN Enable Input. Pulling the VEN above 2V will enable the IC; pulling VEN below 0.6V will disable the IC. This pin is pulled high by an internal current source. 10 VINSEL Input Voltage Sense Pin. Connect a resistive divider from VIN to VINSEL to GND to monitor the input voltage. Pulling VVINSEL below 0.3V will disable this function. Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2014 9 www.anpec.com.tw APL3542A Block Diagram 5V LDO Bias+Band-Gap VIN UVLO VIN TD(ON) Gm POK ISENSE EN 5V OCSET OCP 0.3V 1.8V 5V VINSEL 2.4uA Logic Control 0.65V DELAY VINSEL SCP Clock Generator 2.2V DRV 1.8V Charge Pump and Gate Driver Open Detectio n 5V VOUT POK POK VOUT VOUT TD(POK) VIN x0.85 UVP VIN x0.9 GND 100mA precharge current source Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2014 10 www.anpec.com.tw APL3542A Typical Application Circuit 19V 5V R4 10Ω R3 10kΩ C CNTL 0.47µF VCNTL R1 24 kΩ 1% POK VIN VINSEL RS 5mΩ R2 2.4kΩ 1% ISENSE R G 47 Ω Q1 APL3542A DRV ON EN CG OFF 0.47 µF DELAY VOUT C DELAY VOUT 0.1µF OCSET GND C OUT 470 µF R OCSET 1 kΩ Use R resistor to sense output current S 19V 5V R4 10 Ω R3 10 kΩ C CNTL 0.47µF VCNTL VIN Q 1 RG 47 Ω CG R1 24kΩ 1% VINSEL R2 2.4 kΩ 1% DRV APL3542A 0.47µ F V OUT POK ON EN OFF DELAY VOUT C OUT 470µF ISENSE R5 100kΩ GND C DELAY 0.1µF OCSET R OCSET 1kΩ Use MOSFET’s on-resistance to sense output current Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2014 11 www.anpec.com.tw APL3542A Function Description The OCP latch-off occurs when the load current exceeds IOCP and period persists over OCP debounce time. This Wrong VIN Input Voltage Protection The APL3542A provides an input voltage detection function to protect a wrong input adapter insertion. Connect a feature of debounce ignores transient current. When the load current exceeds 1.5 x IOCP, the APL3542 latches off resistive divider from VIN to VINSEL to GND to set the target input voltage. The target input voltage is set at: immediately. VIN(target)=1.4V x (1+R1/R2) The IC is enabled When input voltage is within the VIN(target) Pre-SCP Protection The APL3542A implements Pre-SCP function during power-on period by monitoring the voltage on both DE- +15% (VIN also must be above VUVLO and EN is high); the device is shut down when input voltage is outside the VIN (target)+20%. LAY and OUT pins. If a short circuit is present before power on, the VOUT’s voltage will be kept low and never Power-Up reach 1.8V threshold while the DELAY’s voltage will rise beyond 1.8V, the SCP will be engaged. The chip will latch The APL3542A has a built-in under-voltage lockout circuitry to keep the DRV output shut off until internal cir- off after 4 times of short circuit condition is detected, needing to toggle EN or VCC to release the latch off condition. cuitry is operating properly. The UVLO circuit has a hysteresis and a de-glitch feature so that it will typically ig- Connecting a capacitor on DELAY pin can adjust the SCP timing, meaning that larger CDELAY capacitor postpones nore undershoot transients on the input. When input voltage exceeds the UVLO threshold and after 10ms delay the timing of SCP. If output soft start time is very long, the C DELAY capacitor should be adjusted, accordingly. time. Under-Voltage Protection (UVP) The OUT pin monitors the output voltage. If the VOUT is Approximately, the selection of CDELAY should meet the following criterion to avoid wrongly SCP trigger: 42000 x CDELAY>COUT under 85% of VIN input voltage, because of the short circuit or other influences, it will cause the under voltage Shutdown Control protection, and turn off IC, the VOUT voltage is also discharged to GND by an internal resistor, requiring a VIN The APL3542A has an active-low shutdown function. Pull- UVLO or EN re-enable again to restart IC. Note that the UVP is active after the power-up and POK is asserted. ing the VEN above 2V will enable the IC; pulling VEN below 0.6V will disable the IC and the POK is pulled low imme- Over-Current Protection (OCP) diately (ignore the VPOK(TH) and TD(POK)), the VOUT voltage is also discharged to GND by an internal resistor . EN pin is The APL3542A provides OCP protection against over load or short circuit conditions after POK is asserted. pulled high by an internal current source and can be left floating. The OCP threshold can be adjusted by the resistor on OCSET pin, ROCSET. When the load current flowing through POK Output and POK Open Detection The power okay function monitors the output voltage and the RS (the sense resistor between VIN and ISENSE) or RDS(ON) (the on-resistance of extermal power MOSFET) drives the POK low to indicate a fault. When a fault condition such as over-current, or under-voltage is occurred, exceeds the OCP threshold, IOCP, the APL3542 will turn off its DRV by internal discharge circuit and latch whole chip and the V output voltage falls to 85% of VIN input voltage, OUT the POK is pulled low. When the V output voltage in off state until EN or VCC is cycled. The IOCP can be calculated according to RSENSE and ROCSET by the follow- OUT reaches to 90% of VVIN, and after 10ms delay time the POK is pulled high. Since the POK is an open-drain ing equation: IOCP(A)= 1000/ (RS (mΩ)x ROCSET(kΩ)) device, connecting a resistor to a pull high voltage is necessary. -using RS as current sensing IOCP(A)= 1000/ (RDS(ON) (mΩ)x ROCSET(kΩ)) -using RDS(ON) as current sensing Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2014 12 www.anpec.com.tw APL3542A Function Description (Cont.) POK Output and POK Open Detection(cont.) If the POK is not used, it can be left open. We presume that the POK is a declaration of “power is ready” and used to allow system draws large current from V . Since OUT the POK is opened, meaning that POK indication is not implemented by system designer, the larger power request shall come at any time. In POK open case, we advance the DRV timing to drive Q1 in case power request is around the corner. Please refer to the following timing diagram for both POK open and POK used conditions. If the POK is used, the range of POK externally pulled high resistor must be 2kΩ~200kΩ. POK Used POK Open VOUT=90% of VVIN VOUT 100mA precharge DRV 1.8V VOUT 100mA precharge DRV Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2014 13 www.anpec.com.tw APL3542A Application Information avoid oscillation. The RG can be in the range of 10~100Ω. Input Capacitor The recommended value is 47Ω. While hot plug-in an AC adapter, the inductive peak voltage seen in the VIN pin could be very high if there is no Power MOSFETs any filtering measure taken. It is recommended to place a 0.1 to 1µF ceramic bypass capacitor as close as possible APL3542A requires an N-channel MOSFET that is utilized as an on/off switch. When a MOSEFT is selected, please make sure that the RDS(ON) of this MOSFET can meet your to the VIN pin. An RC-filter, depicted in the application circuit, is preferable because better performance in filter- maximum voltage droop requirement in full load conditions. And also make sure that the MOSFET you ing the peak voltage and noise. Note that the voltage rating of the input capacitor must be greater than the maxi- select can satisfy the current delivering requirement, described in the paragraph of Short-Circuit Protection in mum VIN voltage. Function Description. Another important criterion for selection of MOSFET is the MOSFET must be operated within Gate and Output Capacitor It is recommended to place a capacitor in the gate of ex- its safe operation area in your application. The package type of the MOSFET must be chosen for efficient heat ternal power MOSFET to control the soft-start rate of output voltage, especially when a high-value output capaci- removal. Note that the VDS rating of the MOSFET you selected must be greater than the VIN voltage and the VGS tor is used. The gate capacitor can reduce the inrush current to the output capacitor during soft-start. If the power rating must be greater than 5V. The power dissipated in the MOSFET while on is shown in the following equation: supply cannot support the inrush current, the COUT voltage will be clamped during soft-start and SCP will be falsely PD = IO2 x RDS(on) activated. The inrush current must be controlled within power supply current capability by using this gate capacitor. Select a package type and heatsink that maintains the junction temperature below the rating. Note that the voltage rating of the gate capacitor must be greater than the maximum VDRV voltage, where the VDRV approximately equals VIN+5V. A bulk output capacitor, placed close to the load, is recommended to support load transient current. Precautions Layout Consideration should be taken when a high-value output capacitor is used the gate capacitor C1 (shown in the application high current paths; and these traces must be short and wide. The layout guidelines are listed as below. circuit) must be matched. A high-value output capacitor with a small-value C1 would probably lead to inrush cur- 1. Place the input capacitors CIN for VIN near pin as close as possible. rent and end up SCP latched-off in the soft-start period. Please make sure that the gate capacitor C1 is matched 2. The trace from DRV to the gate of power MOSFETs should be wide and short. with a high-value output capacitor. Note that the voltage rating of the output capacitor must be greater than the 3. Place output capacitor COUT near the load as close as possible. maximum VIN voltage. 4. Large current paths must have wide and thick traces, depicted as the bold lines. Figure 1 illustrates the layout, with bold lines indicating Gate Resistor 5. The drain of the power MOSFETs should be a large plane for heatsinking. It is recommended to place a resistor RG, as shown in the Typical Application Circuit, in the gate of external power MOSFET to prevent occurrence of oscillation during powering on. If the oscillation occurs, the SCP or VINSEL wrong voltage detection might be activated unexpectedly. The RG literally could stabilize the external MOSFET to Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2014 14 www.anpec.com.tw APL3542A Application Information (Cont.) Layout Consideration (Cont.) VIN CIN VIN DRV C1 APL3542A VOUT GND COUT Load Figure 1. Layout Guidelines Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2014 15 www.anpec.com.tw APL3542A Package Information TDFN3x3-10 D E A b Pin 1 A1 D2 A3 L K E2 Pin 1 Corner e TDFN3x3-10 S Y M B O L A MIN. MAX. MIN. MAX. 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 0.30 0.007 0.012 3.10 0.114 0.122 A3 b INCHES MILLIMETERS 0.20 REF 0.18 0.008 REF D 2.90 D2 2.20 2.70 0.087 0.106 E 2.90 3.10 0.114 0.122 1.75 0.055 0.069 0.50 0.012 E2 1.40 e L K 0.50 BSC 0.30 0.020 BSC 0.020 0.008 0.20 Note : 1. Followed from JEDEC MO-229 VEED-5. Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2014 16 www.anpec.com.tw APL3542A Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TDFN3x3-10 A H T1 C d D 330.0±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 3.30±0.20 3.30±0.20 1.30±0.20 4.0±0.10 8.0±0.10 W E1 12.0±0.30 1.75±0.10 F 5.5±0.05 (mm) Devices Per Unit Package Type TDFN3x3-10 Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2014 Unit Tape & Reel Quantity 3000 17 www.anpec.com.tw APL3542A Taping Direction Information TDFN3x3-10 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2014 18 www.anpec.com.tw APL3542A Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2014 Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 19 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APL3542A Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2014 20 www.anpec.com.tw