APL3206/A Li+ Charger Protection IC with Integrated P-MOSFET Features General Description • Input Over-Voltage Protection • Input Over-Current Protection The APL3206/A provides complete Li+ charger protection against input over-voltage, input over-current, and battery • Battery Over-Voltage Protection • High Immunity of False Triggering • High Accuracy Protection Threshold • A Built-In P-MOSFET • Thermal Shutdown Protection • Compliance to IEC61000-4-2 (Level 4) • over-voltage. When any of the monitored parameters are over the threshold, the IC removes the power from the charging system by turning off an internal switch. All protections also have deglitch time against false triggering due to voltage spikes or current transients. The APL3206/A integrates a P-MOSFET with the body diode reverse protection to replace the external P-MOSFET and Schottky diode for charger function of cell phone’s ± 8kV (Contact Discharge) PMIC. When the CHRIN voltage drops below VBAT+20mV, the internal power select circuit will reverse the body ± 15kV (Air Discharge) diode’s terminal to prevent a reverse current flowing from the battery back to CHRIN pin. Available in a TDFN2x2-8 and TSOT-23-6A The APL3206/A provides complete Li+ charger protections and saves the external MOSFET and Schottky diode Packages • for the charger of cell phone’s PMIC. The above features and small package make the APL3206/A an ideal part for Lead Free and Green Devices Available (RoHS Compliant) cell phones applications. Applications • Pin Configuration Cell Phones ACIN 1 8 OUT ACIN 2 Simplified Application Circuit GND 3 7 OUT EP VBAT 4 TDFN2x2-8 (Top View) 5V Adapter or USB ACIN CHRIN CHRIN EP APL3206/A PMIC GATDRV = Exposed Pad (connected to ground plane for better heat dissipation) GATDRV ISENS OUT 6 VIN OUT 1 GND 6 CHRIN 5 GATDRV VBAT CHRIN 2 VBAT 5 GND GATDRV 3 Li+ Battery 4 VBAT TSOT-23-6A (Top View) ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 1 www.anpec.com.tw APL3206/A Ordering and Marking Information Package Code QB : TDFN2x2-8 CT : TSOT-23-6A Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APL3206 APL3206A Assembly Material Handling Code Temperature Range Package Code APL3206 QB: L06 X X - Date Code APL3206A QB: L6A X X - Date Code APL3206 CT: L06X X - Date Code APL3206A CT: L6AX X - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings (Note 1) Symbol VACIN Parameter ACIN Input Voltage (ACIN to GND) VCHRIN CHRIN to GND Voltage VGATDRV GATDRV to GND Voltage Rating Unit -0.3 ~ 30 V -0.3 ~ 7 V -0.3 ~ VCHRIN V VBAT VBAT to GND Voltage -0.3 ~ 7 V VOUT OUT to GND Voltage -0.3 ~ 7 V IOUT OUT Output Current 1.5 Maximum Junction Temperature 150 o -65 ~ 150 o 260 o TJ TSTG TSDR Storage Temperature Maximum Lead Soldering Temperature, 10 Seconds A C C C Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristic Symbol Parameter Typical Value Unit Junction-to-Ambient Resistance in Free Air (Note 2) θJA TDFN2x2-8 80 TSOT-23-6A 235 o C/W Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of TDFN2x2-8 is soldered directly on the PCB. Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 2 www.anpec.com.tw APL3206/A Recommended Operating Conditions (Note 3) Symbol Parameter Range Unit VACIN ACIN Input Voltage 4.5 ~ 5.5 V IOUT Output Current 0 ~ 700 mA TA Ambient Temperature -40 ~ 85 o -40 ~ 125 o TJ Junction Temperature C C Note 3: Refer to the typical application circuit Electrical Characteristics Unless otherwise specified, these specifications apply over VACIN=5V, VBAT=3.8V and TA= -40 ~ 85 oC. Typical values are at TA=25oC. Symbol Parameter APL3206/A Test Conditions Unit Min. Typ. Max. - 250 350 ACIN INPUT CURRENT AND POWER-ON-RESET (POR) IACIN VACIN ACIN Supply Current IOUT=0A, ICHRIN=0A ACIN POR Threshold VACIN rising ACIN POR Hysteresis TB(ACIN) ACIN Power-On Blanking Time µA 2.4 - 2.8 V 200 250 300 mV - 8 - ms - 0.5 - Ω - 500 - Ω INTERNAL SWITCH ON RESISTANCE ACIN to OUT On Resistance IOUT=0.7A CHRIN Discharge On Resistance INPUT OVER-VOLTAGE PROTECTION (OVP) VOVP Input OVP Threshold APL3206 VACIN rising APL3206A Input OVP Hysteresis Input OVP Propagation Delay TON(OVP) Input OVP Recovery Time 6 6.17 6.35 6.6 6.8 7 200 300 400 mV - - 1 µs - 8 - ms V OVER-CURRENT PROTECTION (OCP) IOCP TB(OCP) OCP Threshold 1 - 1.5 A OCP Blanking Time - 176 - µs - 64 - ms 4.32 4.35 4.38 V 220 270 320 mV - - 20 nA - 176 - µs VCHRIN from low to high, P-MOSFET is controlled by GATDRV - 150 - VCHRIN from high to low, P-MOSFET is off - 20 - TON(OCP) OCP Recovery Time BATTERY OVER-VOLTAGE PROTECTION VBOVP Battery OVP Threshold VBAT rising Battery OVP Hysteresis IVBAT VBAT Pin Leakage Current VBAT = 4.4V TB(BOVP) Battery OVP Blanking Time INTERNAL P-MOSFET (CHRIN, OUT, AND GATDRV PINS) VCHRIN-VBAT Lockout Threshold mV OUT Input Current VCHRIN=0V, VOUT=4.2V, GATDRV=GND - - 1 µA GATDRV Leakage Current VACIN=VCHRIN= VOUT=5V, VGATDRV=0V - - 1 µA OUT Leakage Current VACIN=VCHRIN= VGATDRV =5V, VOUT=0V - - 1 µA Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 3 www.anpec.com.tw APL3206/A Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VACIN=5V, VBAT=3.8V and TA= -40 ~ 85 oC. Typical values are at TA=25oC. Symbol Parameter APL3206/A Test Conditions Unit Min. Typ. Max. P-MOSFET Input Capacitance - 200 - pF GATDRV Input Resistance - 15 - Ω - 160 - °C - 40 - °C INTERNAL P-MOSFET (CHRIN, OUT, AND GATDRV PINS) (CONT.) OVER-TEMPERATURE PROTECTION (OTP) TOTP Over-Temperature Threshold TJ rising Over-Temperature Hysteresis Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 4 www.anpec.com.tw APL3206/A Typical Operating Characteristics OCP Threshold vs. Junction Temperature 6.25 1.30 6.15 1.25 OCP Threshold, IOCP (A) Input OVP Threshold, VOVP (V) Input OVP Threshold vs. Junction Temperature VACIN Increasing 6.05 5.95 5.85 5.75 1.20 1.15 1.10 1.05 VACIN Decreasing 1.00 5.65 -50 -25 0 25 50 75 Junction Temperature 100 -50 125 ACIN to OUT On Resistance, RDS,ON (mΩ) Battery OVP Threshold, VBOVP (V) 4.35 VBAT Increasing 4.25 4.20 4.15 4.10 VBAT Decreasing 4.00 -50 -25 0 25 50 75 100 50 75 100 125 1000 900 800 ACIN to OUT On Resistance 700 600 500 400 300 -50 125 -25 0 25 50 75 100 Junction Temperature (oC) Junction Temperature ( oC) ACIN Supply Current vs. Junction Temperature POR Threshold vs. Junction Temperature 350 125 2.8 VACIN Increasing POR Threshold, VPOR (V) ACIN Supply Current, IACIN (µA) 25 ACIN to OUT On Resistance vs. Junction Temperature 4.40 4.05 0 Junction Temperature (oC) Battery OVP Threshold vs. Junction Temperature 4.30 -25 ( oC) 300 250 200 2.7 2.6 2.5 2.4 VACIN Decreasing 2.3 150 2.2 -50 -25 0 25 50 75 Junction Temperature Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 100 -50 125 -25 0 25 50 75 Junction Temperature (oC) 5 100 125 (oC) www.anpec.com.tw APL3206/A Operating Waveforms The test condition is VACIN=5V, VBAT=3.8V, CACIN=1µF, CCHRIN=1µF, TA= 25oC unless otherwise specified. OVP at Power On Normal Power On VACIN 1 VACIN VOUT 1 VCHRIN 2 VCHRIN VOUT 2,3 IOUT 3 4 VACIN = 0 to 12V, VGATDRV = VCHRIN CH1: VACIN, 10V/Div, DC CH2: VCHRIN, 2V/Div, DC CH3: VOUT, 2V/Div, DC TIME: 2ms/Div VGATDRV = VCHRIN CH1: VACIN, 5V/Div, DC CH2: VOUT, 2V/Div, DC CH3: VCHRIN, 2V/Div, DC CH4: IOUT, 0.2A/Div, DC TIME: 2ms/Div Input Over-Voltage Protection Recovery from Input OVP VACIN VACIN 1 1 VCHRIN VCHRIN 2 2 VACIN =5V to 12V VACIN= 12V to 5V CH1: VACIN, 5V/Div, AC CH2: VCHRIN, 2V/Div, DC TIME:20µs/Div CH1: VACIN, 5V/Div, AC CH2: VCHRIN, 2V/Div, DC TIME: 2ms/Div Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 6 www.anpec.com.tw APL3206/A Operating Waveforms (Cont.) The test condition is VACIN=5V, VBAT=3.8V, CACIN=1µF, CCHRIN=1µF, TA= 25oC unless otherwise specified. Battery Over-Voltage Protection Battery Over-Voltage Protection VBAT VBAT 1 1 VCHRIN VCHRIN 2 2 VBAT = 3.6V to 4.4V VBAT = 3.6V to 4.4V to 3.6V CH1: VBAT, 2V/Div, DC CH2: VCHRIN, 2V/Div, DC TIME: 200µs/Div CH1: VBAT, 2V/Div, AC CH2: VCHRIN, 2V/Div, DC TIME: 50ms/Div Over-Current Protection Over-Current Protection VCHRIN VACIN VOUT 1 VCHRIN 1 2 2 VOUT IOUT IOUT 3 3 ROUT=2.5Ω, VBAT = 0V, VGATDRV=0V ROUT=10Ω to 2.4Ω, VBAT = 0V, VGATDRV=0V CH1: VACIN, 5V/Div, DC CH2: VCHRIN, 5V/Div, DC CH3: VOUT, 5V/Div, DC CH4: IOUT, 1A/Div, DC TIME: 200ms/Div Note: OUT pin connected with a resistor to ground. CH1: VCHRIN, 2V/Div, DC CH2: VOUT, 2V/Div, DC CH3: IOUT, 0.5A/Div, DC TIME: 100µs/Div Note: OUT pin connected with a resistor to ground. Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 7 www.anpec.com.tw APL3206/A Pin Description PIN FUNCTION NO. NAME 1 ACIN 2 ACIN Power Supply Input. Connect this pin to external DC supply. Bypass to GND with a 1µF (minimum) ceramic capacitor. 3 GND Ground Terminal. 4 VBAT Battery Voltage Sense Input. Connect this pin to pack positive terminal through a resistor. 5 GATDRV 6 CHRIN 7 OUT 8 OUT - EP Internal P-MOSFET Gate Input. Output Pin. This pin provides supply voltage to the PMIC input. Bypass to GND with a 1µF (minimum) ceramic capacitor. Output Pins. These pins provide supply source current in series with a resistor to battery. Exposed Thermal Pad. Must be electrically connected to the GND pin. Block Diagram ACIN CHRIN POR OUT Charge Pump ACIN OVP OCP Gate Driver and Control Logic VBAT OVP 0.5V 1V GATDRV GND VBAT Thermal Shutdown Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 8 www.anpec.com.tw APL3206/A Typical Application Circuit 5V Adapter/USB 1, 2 ACIN CACIN 1µF CHRIN 6 CHRIN CCHRIN 1µF APL3206/A GATDRV PMIC 5 GATDRV 7, 8 ISENS OUT 0.2Ω 3 GND VBAT 4 VBAT RBAT 200kΩ Li+ Battery Description Designation CACIN 1µF, 25V, X5R, 0603 Murata GRM188R61E105K CCHRIN 1µF, 10V, X5R, 0603 Murata GRM188R61A105K Murata website: www.murata.com Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 9 www.anpec.com.tw APL3206/A Function Description ACIN Power-On-Reset (POR) Over-Temperature Protection The APL3206/A has a built-in power-on-reset circuit to When the junction temperature exceeds 160oC, the internal thermal sense circuit turns off the power FET and keep the output shutting off until internal circuitry is operating properly. The POR circuit has hysteresis and a de- allows the device to cool down. When the device’s junction temperature cools by 40 oC, the internal thermal glitch feature so that it will typically ignore undershoot transients on the input. When input voltage exceeds the sense circuit will enable the device, resulting in a pulsed output during continuous thermal protection. Thermal pro- POR threshold and after 8ms blanking time, the output voltage starts a soft-start to reduce the inrush current. tection is designed to protect the IC in the event of over temperature conditions. For normal operation, the junc- ACIN Over-Voltage Protection (OVP) tion temperature cannot exceed TJ=+125oC. The input voltage is monitored by the internal OVP circuit. When the input voltage rises above the input OVP Internal P-MOSFET threshold, the internal FET will be turned off within 1ms to protect connected system on OUT pin. When the input The APL3206/A integrates a P-channel MOSFET with the body diode reverse protection to replace the external PMOSFET and Schottky diode for cell phone’s PMIC. The voltage returns below the input OVP threshold minus the hysteresis, the FET is turned on again after 8ms recovery body diode reverse protection prevents a reverse current flowing from the battery back to CHRIN pin. During power- time. The input OVP circuit has a 300mV hysteresis and a recovery time of TON(OVP) to provide noise immunity against transient conditions. on, when CHRIN voltage rises above the VBAT voltage by more than 150mV, the body diode of the P-channel Over-Current Protection (OCP) MOSFET is forward biased from OUT to CHRIN, and PMOSFET is controlled by the external GATDRV voltage. The output current is monitored by the internal OCP circuit. When the CHRIN voltage drops below VBAT+20mV, the body diode of the P-channel MOSFET is forward biased When the output current reaches the OCP threshold, the device limits the output current at OCP threshold level. If from CHRIN to OUT and P-channel MOSFET is turned off. When any of input OVP, OCP, battery OVP, is detected, the OCP condition continues for a blanking time of TB(OCP), the internal power FET is turned off. After the recovery the internal P-channel MOSFET is also turned off. time of TON(OCP), the FET will be turned on again. The APL3206/A has a built-in counter. When the total count of ESD Tests OCP fault reaches 16, the FET is turned off permanently, requiring a VACIN POR again to restart. The APL3206/A VIN input pin fully supports the IEC610004-2. That means the VIN pin has immunity of ±15kV ESD Battery Over-Voltage Protection discharge in Air condition, and immunity of ±8kV ESD discharge in Contact condition. The APL3206/A monitors the VBAT pin voltage for battery over-voltage protection. The battery OVP threshold is internally set to 4.35V. When the VBAT pin voltage exceeds the battery OVP threshold for a blanking time of TB(BOVP), the internal power FET is turned off. When the VBAT voltage returns below the battery OVP threshold minus the hysteresis, the FET is turned on again. The APL3206/A has a built-in counter. When the total count of battery OVP fault reaches 16, the FET is turned off permanently, requiring a VACIN POR again to restart. Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 10 www.anpec.com.tw APL3206/A Function Description (Cont.) VOVP VPOR VACIN VCHRIN -VBAT = 150mV VCHRIN -VBAT = 150mV VCHRIN VOUT GATDRV is pulled low P-MOS Gate Control Controlled by GATDRV Turn Off Internal P-MOSFET Controlled by GATDRV Turn Off Internal P-MOSFET TB(ACIN) ACIN OVP TON(OVP) Figure 1. OVP Timing Diagram IOCP IOUT GATDRV is pulled low VCHRIN P-MOS Gate Control Count 13 times Controlled by GATDRV TB(OCP) Turn Off Internal P-MOSFET Controlled by GATDRV TON(OCP) Turn Off Internal PMOSFET TB(OCP) Controlled by GATDRV Turn Off Internal PMOSFET Total count 16 times, IC is latched off TB(OCP) Figure 2. OCP Timing Diagram Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 11 www.anpec.com.tw APL3206/A Function Description (Cont.) VBAT VBOVP VBOVP VCHRIN -VOUT = 150mV VCHRIN Count 13 times P-MOS Gate Controlled Control by GATDRV Turn Off Internal P-MOSFET TB(BOVP) Controlled by GATDRV Turn Off Internal PMOSFET TB(BOVP) Controlled by GATDRV Turn Off Internal P-MOSFET TB(BOVP) Total count 16 times, IC is latched off Figure 3. Battery OVP Timing Diagram Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 12 www.anpec.com.tw APL3206/A Application Information tion at TA = 25oC can be calculated by following formula : RBAT Selection Connect the VBAT pin to the positive terminal of battery through a resistor RBAT for battery OVP function. The RBAT PD(MAX) = (125oC-25oC) / (165oC/W) = 0.606W limits the current flowing from VBAT to battery in case of VBAT pin is shortened to ACIN pin under a failure mode. PD(MAX) = (125oC-25oC) / (220oC/W)= 0.455W for TDFN2x2-8 packages for TSOT-23-6A packages The recommended value of RBAT is 200kΩ. In the worse case of an IC failure, the current flowing from the VBAT The maximum power dissipation depends on operating ambient temperature for fixed TJ(MAX) and thermal resistance θJA. For APL3206/A packages, the Figure 4 of derat- pin to the battery is: (30V-3V) / 200kΩ =135µA ing curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. where the 30V is the maximum ACIN voltage and the 3V is the minimum battery voltage. The current is so small and can be absorbed by the charger system. 0.8 Signal Layer PCB 0.7 Power Dissipation (W) Capacitor Selection The input capacitor is for decoupling and prevents the input voltage from overshooting to dangerous levels. In the AC adapter hot plug-in applications or load current step-down transient, the input voltage has a transient spike due to the parasitic inductance of the input cable. A 25V, X5R, dielectric ceramic capacitor with a value between 1µF and 4.7µF placed close to the ACIN pin is TDFN2x2-8 0.6 0.5 TSOT-23-6A 0.4 0.3 0.2 0.1 0.0 recommended. The output capacitor of CHRIN is for CHRIN voltage 0 25 50 75 Ambient Temperature ( decoupling. And also can be as the input capacitor of the charging circuit. At least, a 1µF, 10V, X5R capacitor is 100 125 oC) Figure 4. Derating Curves for APL3206/A Packages recommended. Layout Consideration Thermal Considerations In some failure modes, a high voltage may be applied to The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of the device. Make sure the clearance constraint of the PCB layout must satisfy the design rule for high voltage. The surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can exposed pad of the TDFN2x2-8 performs the function of channeling heat away. It is recommended that connect be calculated by following formula: the exposed pad to a large copper ground plane on the backside of the circuit board through several thermal vias PD(MAX) = (TJ(MAX)-TA) / θJA to improve heat dissipation. The input and output capacitors should be placed close to the IC. The high current Where T J(MAX) is the maximum operation junction temperature, TA is the ambient temperature and the θJA is traces like input trace and output trace must be wide and short. the junction to ambient thermal resistance. For recommended operating conditions specification of APL3206/ A, where TJ(MAX) is 125oC and TA is the operated ambient temperature. The junction to ambient thermal resistance θJA for TDFN2x2-8 package is 165oC/W and TSOT-23-6A package is 220oC/W on the standard JEDEC 51-3 singlelayer thermal test board. The maximum power dissipaCopyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 13 www.anpec.com.tw APL3206/A Package Information TDFN2x2-8 A b E D D2 A1 E2 A3 L Pin 1 Corner e S Y M B O L MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 TDFN2x2-8 MILLIMETERS A3 INCHES 0.20 REF 0.008 REF b 0.18 0.30 0.007 0.012 D 1.90 2.10 0.075 0.083 D2 1.00 1.60 0.039 0.063 E 1.90 2.10 0.075 0.083 E2 0.60 1.00 0.024 0.039 0.45 0.012 e L 0.50 BSC 0.30 0.020 BSC 0.018 Note : 1. Follow from JEDEC MO-229 WCCD-3. Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 14 www.anpec.com.tw APL3206/A Package Information TSOT-23-6A D e E E1 SEE VIEW A b c 0.25 A GAUGE PLANE SEATING PLANE L A1 A2 e1 VIEW A S Y M B O L TSOT-23-6A INCHES MILLIMETERS MIN. MAX. 1.00 0.028 0.039 0.10 0.000 0.004 MIN. MAX. A 0.70 A1 0.01 A2 0.70 0.90 0.028 0.035 b 0.30 0.50 0.012 0.020 c 0.08 0.20 0.003 0.008 D 2.70 3.10 0.106 0.122 E 2.60 3.00 0.102 0.118 E1 1.40 1.80 0.055 0.071 e 0.95 BSC e1 L 0 0.037 BSC 1.90 BSC 0.075 BSC 0.30 0.60 0° 8° 0.012 0.024 0° 8° Note : Dimension D and E1 do not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 15 www.anpec.com.tw APL3206/A Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TDFN2x2-8 Application TSOT-23-6A A H T1 C d D W E1 F 178.0±2.00 50 MIN. 8.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 8.0±0.20 1.75±0.10 3.50±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.4 3.35 MIN 3.35 MIN 1.30±0.20 4.0±0.10 4.0±0.10 A H T1 C d D W E1 F 178.0±2.00 50 MIN. 8.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 8.0±0.30 1.75±0.10 3.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.0 MIN. 0.6+0.00 -0.40 3.20±0.20 3.10±0.20 1.50±0.20 4.0±0.10 4.0±0.10 (mm) Devices Per Unit Package Type TDFN2x2-8 TSOT-23-6A Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 Unit Tape & Reel Tape & Reel Quantity 3000 3000 16 www.anpec.com.tw APL3206/A Taping Direction Information TDFN2x2-8 USER DIRECTION OF FEED TSOT-23-6A USER DIRECTION OF FEED AAAX AAAX Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 AAAX AAAX 17 AAAX AAAX AAAX www.anpec.com.tw APL3206/A Classification Profile Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 18 www.anpec.com.tw APL3206/A Classification Reflow Profiles (Cont.) Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Description 5 Sec, 245°C 1000 Hrs, Bias @ 125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 19 www.anpec.com.tw