LTC4371 Dual Negative Voltage Ideal Diode-OR Controller and Monitor Description Features Controls N-Channel MOSFETs to Replace Power Schottky Diodes nn Low 15mV Forward Voltage Minimizes Dissipation nn Withstands > ±300V Transients nn Fast Turn-Off: <220ns nn Shunt Regulated for High Voltage Applications nn 4.5V Minimum Operation nn Low 350μA Quiescent Current nn 5mA Gate Pull-Up for 60Hz Applications nn High Impedance Drain Pins: <10μA Leakage nn Open Fuse and MOSFET Monitor nn 10-Pin (3mm × 3mm) DFN and MSOP Packages nn Applications –48V Telecom Power AdvancedTCA Systems nn Network Routers and Switches nn Computer Systems and Servers nn nn L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. The LTC®4371 is a two-input negative voltage ideal diode-OR controller that drives external N-channel MOSFETs as a low dissipation alternative to Schottky diodes in high power –48V systems. Low power dissipation and voltage loss eliminates the need for heatsinks and reduces PC board area. Power sources can be easily ORed together to increase total system power and reliability. The LTC4371 tolerates ±300V transients such as those experienced during lightning-induced surges and input supply short-circuit events. The internal shunt regulator and low 350μA quiescent current allow the use of a large value dropping resistor to protect the supply pin against high voltage transients, while the high impedance drain pins can be similarly protected by high value series resistors without compromising diode operation. The 220ns reverse current turn-off is achieved by a powerful 2A gate driver with low propagation delay, thereby minimizing peak reverse current under catastrophic fault conditions. Open MOSFET and fuse faults are indicated at the FAULTB pin, which is capable of sinking 5mA to drive an LED or opto isolator. Typical Application RTN –48V/50A Diode-OR Power Dissipation vs. Load Current RZ 30k RDA 20k VA –36V TO –72V DB GA 40 FAULTB GB SA SB VSS RDB 20k D1 GREEN LED = MOSFETS GOOD VOUT 50A LOAD M1* POWER DISSIPATION (W) LTC4371 DA C1 2.2μF VDD VZ vs Load Current R1 33k 30 SCHOTTKY DIODE (SBRT60U100CT) 20 POWER SAVED 10 M3* VB –36V TO –72V MOSFET (2–IPT020N10N3) M2* 4371 TA01a M4* *M1-M4: IPT020N10N3 0 0 10 20 30 CURRENT (A) 40 50 4371 TA01b 4371f For more information www.linear.com/LTC4371 1 LTC4371 Absolute Maximum Ratings (Notes 1, 2) Supply Voltage VDD..................................... –0.3V to 17V Input Voltage DA, DB (Note 3)..................................... –40V to 100V SA, SB................................................... –0.3V to 0.3V DC Currents VZ.......................................................................20mA DA, DB................................................................ ±1mA Single Pulse Current (6ms) DA, DB.........................10mA Output Voltages GA, GB.................................................... –0.3V to VDD FAULTB................................................... –0.3V to 17V Operating Ambient Temperature Range LTC4371C................................................. 0°C to 70°C LTC4371I..............................................–40°C to 85°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10 sec) MS Package....................................................... 300°C Pin Configuration TOP VIEW DA 1 10 DB GA 2 9 GB SA 3 11 VZ 4 VDD 5 TOP VIEW DA GA SA VZ VDD 8 SB 7 FAULTB 6 VSS 1 2 3 4 5 10 9 8 7 6 DB GB SB FAULTB VSS MS PACKAGE 10-LEAD PLASTIC MSOP DD PACKAGE 10-LEAD (3mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 160°C/W TJMAX = 125°C, θJA = 43°C/W (NOTE 4) EXPOSED PAD (PIN 11) PCB VSS CONNECTION OPTIONAL Order Information (http://www.linear.com/product/LTC4371#orderinfo) LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4371CDD#PBF LTC4371CDD#TRPBF LGSD 10-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C LTC4371IDD#PBF LTC4371IDD#TRPBF LGSD 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LTC4371CMS#PBF LTC4371CMS#TRPBF LTGSF 10-Lead Plastic MSOP 0°C to 70°C LTC4371IMS#PBF LTC4371IMS#TRPBF LTGSF 10-Lead Plastic MSOP –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. 2 4371f For more information www.linear.com/LTC4371 LTC4371 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C, IZ = 50µA, VDD = 12.4V, SA = SB = VSS unless otherwise noted. SYMBOL PARAMETER CONDITIONS VDD Input Supply Range IDD Input Supply Current Normal Operation Gate Fault to VSS ,Strong Pull-Up Disabled Gate Fault to VSS, Strong Pull-Up Enabled VZ MIN l 4.5 ∆VSD = ±0.1V VZ = 10.4V, ∆VSD = 0.1V, One GATE = VSS IZ = 50µA, ∆VSD = 0.1V, One GATE = VSS l l l 200 400 4.5 Shunt Regulator Voltage IZ = 50µA l 11.8 ∆VZ Shunt Regulator Load Regulation IZ = 50µA to 10mA l VZ(PU) VZ High Threshold to Enable Strong Gate Pull-Up VDD = VZ Rising ∆VZ(PU) VZ High Threshold Hysteresis VZ(PU) VZ Low Threshold to Enable Strong Gate Pull-Up ∆VSD Source-Drain Forward Servo Voltage ∆VGATE Gate Drive (VG – VS) IG = 0µA, –1µA; ∆VSD = 100mV IGATE(UP) Gate Pull-Up Current IGATE(DN) l 10.7 TYP MAX 16 V 300 550 7 450 750 9.5 µA µA mA 12.4 14 V 600 mV 11.2 11.8 0.5 VZ Falling UNITS V V 1.15 1.25 l 5 15 l VDD – 0.2 ∆VSD = 100mV, ∆VGATE = 5V l –3 –5 –8 mA Gate Pull-Down Current Strong Gate Pull-Down Current ∆VSD = –10mV, ∆VGATE = 5V ∆VSD = –100mV, ∆VGATE = 5V l l 7 1 10 2 13 3 mA A tOFF Gate Turn-Off Time in Fault Condition ∆VSD = 0.1V Step to –0.4V, CGATE = 3.3nF, ∆VGATE <1V l 220 ns ID DA, DB Leakage Current MOSFET Off MOSFET Open VD = 80V VD = –40V l l 10 –10 µA µA RD DA, DB Resistance ∆VSD = –50mV to 0.1V l 1 2 5 MΩ VBVD DA, DB Breakdown Voltage ID = 10mA, 6ms l 100 130 170 IS SA, SB Leakage Current VS = 0V l ±2 μA 150 200 225 mV l ∆VSD(FLT) Source-Drain Fault Detection Threshold l 1.35 25 VDD + 0.1 V mV V V VFAULTB FAULTB Output Low IFAULTB = 5mA l 0.4 V IFAULTB FAULTB Leakage Current VFAULTB = 16V l ±1 μA Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into pins are positive; all voltages are referenced to VSS unless otherwise specified. Note 3: An internal clamp limits the DA and DB pins to a minimum of 100V above VSS and –40V below VSS. This pin can be safely tied to higher voltages through a resistance that limits the current below 1mA DC or 10mA for a 6ms transient. Driving this pin with current beyond the clamp may damage the device. Note 4: Thermal resistance is specified with exposed pad soldered to a 3-inch by 4.5-inch, four layer FR4 board. If exposed pad is not soldered θJA = 93°C/W. 4371f For more information www.linear.com/LTC4371 3 LTC4371 Typical Performance Characteristics Gate CurrentVoltage vs Forward vs Forward Drop Voltage Shunt Regulator Load Regulation 12.75 –45 300 12.63 –30 200 100 0 IGATE (µA) 400 VZ (V) IDD (uA) Supply Current TA = 25°C, unless otherwise noted. 12.50 0 12.38 0 4 8 12 VDD (V) 16 12.25 0.01 0.1 1 IZ (mA) 4371 G01 Drain Current vs Drain Voltage 10 –15 10 15 100 VDD = 12.4V 15 4371 G02 Drain Current vs Drain Voltage 400 0 30 ∆VSD (mV) 45 60 4371 G03 Load CurrentVoltage vs Forward vs Forward Drop Voltage 50 VDD = 12.4V IPT020N10N3 (2) 7.5 40 200 ID (nA) ID (µA) 2.5 0.1 0 0 85°C 25°C –40°C –0.1 0 40 80 VD (V) –200 –0.50 4371 G04 Turn-Off Time vs Gate Capacitance GATE Capacitance 400 250 VDD = 12.4V ∆VSD = 0.1V TO –0.4V ∆VGATE ≤ 1V tOFF (ns) 200 100 4 0 0.25 VD (V) 0.50 10 20 30 CGATE (nF) 0 0.75 40 50 4371 G07 10 20 ∆VSD (mV) 30 40 4371 G06 Turn-Off Time vs Final Overdrive (T VFINAL, VINITIAL = 0.1V) OFF vs Final Overdrive 250 VDD = 12.4V ∆VSD = VINITIAL TO –0.4V 200 200 150 150 100 0 0 4371 G05 VDD = 12.4V ∆VSD = 0.1V TO VFINAL 100 50 50 0 20 Turn-Off Time vs Initial Overdrive Initial Overdrive 300 0 –0.25 30 10 85°C 25°C –40°C tOFF (ns) –0.2 –40 tOFF (ns) LOAD CURRENT (A) 5 0 0.2 0.4 0.6 VINITIAL (V) 0.8 1 4371 G08 0 0 –0.2 –0.4 –0.6 VFINAL (V) –0.8 –1 4371 G09 4371f For more information www.linear.com/LTC4371 LTC4371 Pin Functions DA, DB (Pins 1 and 10): Drain Voltage Kelvin Sense Inputs. DA and DB connect to the drains of the N-channel MOSFETs. The voltage sensed by SA – DA and SB – DB is used to control the gate drive and hence the ∆VSD drop across the MOSFETs, and it is also used for fault detection. For accurate Kelvin sensing of ∆VSD, connect these pins as closely as possible to the MOSFET drains. An external resistor protects the DA and DB pins from transients exceeding 100V. If the LTC4371 is used in a single channel application, DA and DB may be joined together and operated in parallel; otherwise connect the unused drain pin to VSS. Exposed Pad (Pin 11 – DD Package Only): Exposed pad may be left open or connected to VSS. FAULTB (Pin 7): Fault Output. Open drain output that pulls low to indicate that one or both of the external MOSFETs have failed open. FAULTB can sink up to 5mA to drive an opto isolator or LED. The maximum allowable pull-up voltage is 17V. Connect to VSS if unused. GA, GB (Pins 2 and 9): Gate Drive Outputs. GA and GB operate between VSS and VDD to control their associated MOSFET gates and emulate the behavior of a diode. For ∆VSD >15mV, the gate pin drives the MOSFET on, while ∆VSD <15mV produces the opposite effect. With a large positive ∆VSD, the gate pin pulls up with a strong 5mA source, while large negative ∆VSD activates a 2A pulldown with a maximum propagation delay of 220ns. If the LTC4371 is used in a single channel application, the gate pins may be joined together and operated in parallel to realize a two-fold increase in gate drive strength; otherwise the unused gate pin may be left open. SA, SB (Pins 3 and 8): Source Voltage Kelvin Sense Inputs. SA and SB connect to the sources of the N-channel MOSFETs. The voltage sensed by SA – DA and SB – DB is used to control the gate drive and hence the ∆VSD drop across the MOSFETs, and it is also used for fault detection. For accurate Kelvin sensing of ∆VSD, connect these pins as close as possible to the MOSFET sources. If the LTC4371 is used in a single channel application, SA and SB may be joined together and operated in parallel; otherwise connect the unused source pin to VSS. VDD (Pin 5): Positive Supply Voltage Input. Supply VDD directly from 4.5V to 16V, or in shunt regulated applications connect directly or through a buffer transistor biased by VZ. When connected directly to VZ, bypass VDD with 2.2μF to VSS. Maximum gate drive voltage is limited to VDD. VSS (Pin 6): Device Substrate and Negative Supply Voltage. VSS connects to VOUT at the joined sources of the N-channel MOSFETs. VZ (Pin 4): Shunt Regulator Supply Input. This pin serves as a shunt regulator for the VDD pin or as a regulator reference, and operates with a bias of 50μA to 10mA. Bypass with at least 100nF when used as a reference, and 2.2μF when connected to the VDD pin. If unused, connect VZ to VSS. See “Strong Gate Pull-Up” in the Applications Information for details on the relationship between the VZ pin voltage and gate pin drive strength. 4371f For more information www.linear.com/LTC4371 5 LTC4371 Block Diagram RTN RZ VA VB VDD VZ DA M1 GA DB AMPA – RDA 15mV 15mV +– –+ – AMPB GB RDB M2 + + SA SB 60V 60V 12.4V 130V 130V FAULTB FAULT DETECTION VSS 4371 BD VOUT 6 4371f For more information www.linear.com/LTC4371 LTC4371 Operation The LTC4371 controls N-channel MOSFETs to emulate two ideal diodes (see Block Diagram). By sensing the MOSFET’s source-to-drain voltage drop, amplifiers AMPA and AMPB control the gate of their respective external MOSFET to act as an ideal diode with a 15mV forward (∆VSD) drop. With low load currents, the amplifier regulates the MOSFET gate near its threshold to maintain a forward drop of 15mV. As load current increases, the gate voltage is driven higher to maintain a drop of 15mV. For very large load currents where the MOSFET gate is driven fully on, the forward drop rises linearly with current according to RDS(ON) • ILOAD. If the forward drop is less than 15mV, or if ∆VSD reverses, the amplifier turns the MOSFET off and the load current transfers to the other channel. When the power supply voltages are nearly equal, this regulation technique ensures that the load current is smoothly shared between the supplies without oscillation. The current balance depends on the RDS(ON) of the MOSFETs and the output resistance of the supplies. In the case of supply failure, such as supply VA, while conducting most or all of the load current is shorted to return, a large reverse current flows from return through M1 to any load capacitance and through M2 to supply VB. AMPA detects the current reversal and turns off M1 in less than 220ns. Fast turn-off prevents reverse current from rising to a damaging level. The remaining supply VB delivers load current through the body diode of M2, until the gate is driven on. With 700mV forward drop across M2, AMPB responds quickly and drives the gate with 5mA pull-up current, limiting the body diode conduction time to under 100μs. This minimizes power dissipation arising from switchover and is especially important in 60Hz AC applications. As the forward drop reduces, a weaker output stage takes over and regulates the forward drop, within the limitations of RDS(ON), to 15mV. The LTC4371 can be powered in –4.5V to –16V applications by connecting VDD directly to the power supply return. In higher voltage applications or to guard against input transients, VZ and VDD can be connected together and powered from return through a bias resistor, RZ. For repetitive 5mA gate pull-up current, VDD can be driven by a buffer biased by VZ. The VZ pin is shunt regulated to 12.4V with respect to VSS with 50μA minimum bias, and is capable of sinking up to 10mA. The LTC4371 is designed to withstand high voltage transients exceeding ±300V, such as those experienced during lightning-induced surges and input supply short circuit events, without damage. 130V internal clamps protect drain pins DA and DB against positive spikes. External resistors RDA and RDB are necessary to limit the peak clamp current to less than 10mA. In an application circuit, negative spikes are clamped by the MOSFET’s body diode to VOUT, such that the drain pin never sees more than –700mV with respect to VSS. A safely clamped negative transient on one input manifests itself as a positive transient on the second input and as an increased voltage from RTN to VOUT. The bias resistor, RZ, limits the current into the VZ shunt regulator to less than 10mA. A Fault Detection circuit monitors MOSFET ∆VSD; FAULTB pulls low if ∆VSD of either channel exceeds 200mV while the gate is driven fully on. This is an indication of an open circuit MOSFET and can be configured for fuse monitoring by moving the drain pin connection to the input side of the fuse. 4371f For more information www.linear.com/LTC4371 7 LTC4371 Applications Information High availability systems employ parallel connected power supplies or battery feeds to achieve redundancy and enhance system reliability. Schottky diodes are a popular means of ORing these supplies together at the point of load. The chief disadvantage of Schottky diodes is their significant forward voltage drop and resulting power and efficiency loss. This drop reduces the available supply voltage and dissipates significant power. The LTC4371 solves these problems by using an N-channel MOSFET as a low loss pass element to emulate the behavior of a diode (see Figure 1). An internal 12.4V shunt regulator at the VZ pin provides a means of operating the LTC4371 from higher voltage supplies. It regulates over a range of 50μA to 10mA. In the simplest configuration shown in Figure 2, VDD is connected directly to VZ and biased by resistor RZ from the return. A 2.2μF decoupling capacitor is required to stabilize the VZ shunt regulator, and to momentarily provide the 5mA fast pull-up current at the gate pins as needed. RTN RZ C1 2.2μF LTC4371 RTN RZ 30k VZ VSS R1 33k DA DB RDA 20k VA –36V TO –72V GA GB 4371 F02 VOUT C1 2.2μF VDD Figure 2. Simplest Solution: VDD Connected Directly to VZ FAULTB LTC4371 SA RDB 20k M1 IPT020N10N3 SB VSS D1 GREEN LED Bias resistor RZ is chosen to bias the shunt regulator and provide the maximum VDD current at the expected minimum input voltage according to: VOUT 25A LOAD 4371 F01 VB –36V TO –72V RZ < VIN(MIN) – VZ(MIN) IDD(MAX) + 50µA (1) Maximum bias resistor dissipation is calculated from: M2 IPT020N10N3 Figure 1. –36V to –72V/25A Ideal Diode-OR Controller The MOSFET is turned on when power passes in the forward direction (positive current flow from source to drain), allowing for a low voltage drop from load to supply. In the reverse direction, the MOSFET is turned off to block current flow. By these means, the MOSFET is made to approach the function and performance of an ideal diode. The MOSFET voltage drop, ∆VSD, is sensed by the DA and SA, or DB and SB pins. Powering VDD The LTC4371 is fundamentally a low voltage device operating over a range of 4.5V to 16V at the VDD pin, with respect to VSS. The gate amplifiers are powered from the VDD pin and pull-up to within 300mV of VDD. In low voltage applications such as –5V or –12V, the VDD pin can be powered directly from return, with VSS connected to VOUT. 8 VDD VZ PD(RZ) = (VIN(MAX) – VZ(MIN) )2 RZ (2) The maximum shunt regulator current must not exceed 10mA such that: RZ > VIN(MAX) – VZ(MIN) 10mA (3) In –48V applications a single 1206 size 30kΩ resistor is adequate to power the LTC4371. In the application shown in Figure 1, at 100V (a commonly specified maximum transient condition) peak dissipation in RZ just exceeds 250mW, while the maximum VZ current is slightly less than 3mA. Dissipation rises in certain applications so that a larger package or multiple series units are necessary to implement RZ. Examples include AC applications where the gate drivers demand additional current to supply repetitive For more information www.linear.com/LTC4371 4371f LTC4371 Applications Information pulses from the 5mA fast pull-up, applications where the input operating voltage exceeds 72V and applications with a wide range of input voltage, particularly those where the minimum input voltage approaches the operating voltage of the LTC4371. A wide input voltage range may also result in a situation where the maximum VZ current calculated in Equation 3 exceeds 10mA. For these cases an NPN transistor can be used to buffer the shunt regulator and power VDD, as shown in Figure 3. Equation 1 becomes: VIN(MIN) – VZ(MIN) RZ < IDD(MAX) 50µA + β RZ1 Q1 2N3904 VDD VZ C1 0.1μF M1 BSP125 (600V) LTC4371 VSS 4371 F04 RZ (or RZ2) may be split into multiple segments in order to achieve the desired standoff voltage or dissipation. Whereas 1206 size resistors are commonly rated for 200V working and 400V peak, pad spacing and circuit board design rules may limit the working rating to as little as 100V. Q1 In Figure 3, the voltage drop and power dissipation of Q1 may be augmented by the use of one or more resistors in series with the collector. The same applies for M1 in Figure 4. VDD LTC4371 VSS 4371 F03 VOUT Figure 3. VDD Connected to VZ with NPN for Repetitive 5mA Gate Pull-Up Current where 50μA represents the minimum VZ shunt regulator operating current and β is Q1’s DC current gain. The maximum power dissipation in RZ and the maximum VZ current are calculated from Equations 2 and 3. Dissipation in emitter follower Q1 is given by: RG 10Ω Figure 4. MOSFET Cascode for High Voltage > 250V Applications with 5mA Gate Pull-Up Current RZ C1 0.1μF RZ2 VOUT (4) RTN VZ RTN PD(Q1) =(VIN(MAX) + VBE – VZ(MIN) )•IDD(MAX) (5) In buffered applications, bypass VZ with a 100nF capacitor to VSS. Bypassing VDD is unnecessary. For applications at very high voltages, beyond 300V, small high voltage MOSFETs are more readily available than bipolar devices and the circuit of Figure 4 is preferred. RZ, calculated using Equation 4, is split into two parts, RZ1 and RZ2. RZ1 is sized to produce a 3V drop when operating at VIN(MIN). For all applications RZ (or RZ1 + RZ2) must limit the maximum VZ current to less than 10mA, as calculated using Equation 3. If voltage transients are anticipated, VIN(MAX) becomes the peak transient voltage. Transient requirements may force the use of Figure 3 or Figure 4 instead of Figure 2. The peak VZ current may also be reduced to less than 10mA by filtering, e.g. split RZ (or RZ2) into two equal parts and connect a bypass capacitor from the central node to VSS. Strong Gate Pull-Up For fast turn-on, a strong 5mA driver pulls up on the gate when the MOSFET forward drop (∆VSD) is large. In simple shunt-regulated applications such as shown in Figure 2, the bias resistor RZ may be incapable of supplying 5mA. In this case, a 2.2µF bypass capacitor is required to momentarily provide the strong pull-up current to fully charge the MOSFET gate. In normal operation the 5mA drive is not a DC condition, as it flows only long enough to deliver gate charge to the MOSFET. The amount of 4371f For more information www.linear.com/LTC4371 9 LTC4371 Applications Information charge is approximately equal to the total gate charge, Qg, as specified on the MOSFET’s data sheet. the range of 11.6V to 14.1V, compatible with standard 10V-specified MOSFETs. In low voltage applications, such as where the VDD pin is directly powered from less than 10V, the gate drive is compatible with logic-level and sub logic-level MOSFETs. If there is a fault wherein the MOSFET gate is shorted to VSS and ∆VSD is large, the 5mA pull-up becomes a continuous load on VDD. The extra VDD current overwhelms RZ and discharges the 2.2µF bypass capacitor. When VZ falls to the VZ(PU_EN) threshold of 10.7V, the 5mA pull-up current on both channels is disabled. The 5mA pull-up is enabled when VZ recovers to 11.2V. This feature prevents a shorted gate pin from collapsing VDD and, aside from disabling the 5mA pull-up, interfering with the operation of the second channel when using the configuration shown in Figure 2. The drain-source breakdown rating, BVDSS, must be greater than or equal to the highest input supply voltage. If an input is shorted, the full supply voltage of the opposing channel will appear across the MOSFET of the shorted channel. Avalanche may occur during input short circuits and lightning induced surges if the peak transient voltage exceeds BVDSS with respect to VOUT. In applications such as Figure 3 and 4, if the VDD supply is designed to deliver > 5mA, no VDD bypassing is required. Note that a shorted gate will demand a continuous current of 5mA whenever ∆VSD is large. The LTC4371 attempts to servo the forward drop across the MOSFET (∆VSD) to 15mV by controlling the gate, and flags a fault if the drop exceeds 200mV when the MOSFET is driven fully on. Thus an upper bound for RDS(ON) is set by: The 5mA pull-up is enabled when VZ is biased to >11.8V in its normal shunt regulator mode, or when VZ is <1.15V. Connecting VZ to VSS permanently enables the 5mA gate pull-up. If VZ is not used as a shunt regulator, the 5mA pull-up can be disabled by biasing VZ to voltage between 1.35V and 10.4V (with respect to VSS) as shown in Figure 5. RTN RZ 510k RG 10Ω M1 BSP125 D1 7.5V C1 10nF D2 7.5V C2 10nF LTC4371 VSS ILOAD(MAX) (6) Further, RDS(ON) must be small enough to conduct the maximum load current without excessive MOSFET dissipation, which is calculated from: PD(MOSFET) = ILOAD(MAX)2 • RDS(ON) (7) The definition of “excessive” is provided by the circuit designer based on package and circuit board thermal constraints. Loop Stability 4371 F05 VOUT Figure 5. MOSFET Follower for High Voltage > 250V Applications with 5mA Gate Pull-Up Current Disabled MOSFET Selection The LTC4371 drives N-channel MOSFETs to conduct the load current. The important features of the MOSFETs are threshold voltage, VGS(TH); maximum drain-source voltage, BVDSS; and on-resistance, RDS(ON). Full gate drive for the MOSFETs (∆V GATE ) is VDD + 100mV/–200mV. When used in shunt regulated circuits such as shown in Figure 2, full gate drive lies in 10 ∆VSD(FLT) Where ∆VSD(FLT) is 150mV minimum. VDD VZ RDS(ON) < The gate amplifiers are compensated by the input capacitance of the external MOSFETs. No further compensation components are necessary except in the case of very small MOSFETs. If CISS is less than 500pF, add a 1nF capacitor across the MOSFET gate and source terminals. High Voltage Transient Protection Although the LTC4371 drain pins, DA and DB are designed to handle voltages ranging from –40V to 100V with respect to VSS, they may be subjected to much higher voltages, even in –48V systems. DA and DB are directly exposed to 4371f For more information www.linear.com/LTC4371 LTC4371 Applications Information all voltages appearing at the input. Spikes and transients may arise from various conditions including lightning induced surges, electrostatic discharge, switching of adjacent loads, and input short circuits. The positive spike at the input is clamped to BVDSS relative to VOUT by MOSFET avalanche. BVDSS is inadequate protection for the DA and DB pins, as shall be discussed later. Although the energy stored in parasitic inductance during input short circuit faults is at least two orders of magnitude smaller than the avalanche energy rating of most MOSFETs, the peak current may exceed the avalanche current rating of the MOSFET. In this case and if positivegoing transient energy from other external sources exceeds the MOSFET’s avalanche energy rating, add TVS clamps across each MOSFET as shown in Figure 6. The dynamic behavior of an active ideal diode entering reverse bias is most accurately characterized by a delay, followed by a period of reverse recovery. During the delay phase some reverse current is built up, limited by parasitic resistance and inductance. During the reverse recovery phase, energy stored in the parasitic inductance is transferred to other elements in the circuit. Externally applied input transients in the negative direction are clamped by the body diodes of the MOSFETs to –700mV with respect to VOUT, if not connected directly through RDS(ON) to VOUT, and pose no particular hazard for the DA and DB pins. Negative input transients couple directly to the output which increases the RTN to VOUT voltage. Although the shunt resistor, RZ, limits the current into VZ to a safe level of less than 10mA, an output capacitor or TVS clamp may be required to protect downstream circuitry from negative input transients. Current slew rates during reverse recovery may reach 100A/μs or higher. High slew rates coupled with parasitic inductance in series with the input and output can cause destructive transients to appear at the drain, source and VSS pins of the LTC4371 during reverse recovery. A zero impedance short circuit directly across the input and return is especially troublesome because it permits the highest possible reverse current to build up during the delay phase. When the MOSFET finally interrupts the reverse current, the MOSFET drain and the LTC4371 drain pins experience a positive-going voltage spike, while the MOSFET source and the LTC4371 source and VSS pins spike in the negative direction. To protect the circuit biasing VDD, clamp or bypass VOUT as close as possible to the junction of the MOSFET sources and VSS and the point where the VDD bias circuit connects to return. 100V BVDSS(MIN) MOSFETs are commonly used in –48V applications, but BVDSS(MAX) is not guaranteed and cannot be relied upon to protect the DA and DB pins from exceeding their absolute maximum rating of 100V. Nevertheless, the 100V absolute maximum rating for DA and DB may be safely exceeded if certain precautions are taken. The internal 130V clamps shown in the Block Diagram tolerate RTN RZ 30k 33k VDD VZ INPUT SHORT LTC4371 DA VA –36V TO –72V VB –36V TO –72V INPUT PARASITIC INDUCTANCE – + 20k DB GA CLOAD FAULTB GB SA GREEN LED = MOSFETS GOOD SB VSS 20k 2.2μF OPT. OUTPUT PARASITIC INDUCTANCE – + VOUT REVERSE RECOVERY CURRENT INPUT PARASITIC INDUCTANCE + – OPT. Figure 6. Input Short Circuit Parasitics and Protection Against High Voltage Transients For more information www.linear.com/LTC4371 4371 F06 4371f 11 LTC4371 Applications Information up to 10mA for 6ms in breakdown. For protection against transients exceeding 100V, add series resistors RDA and RDB according to: RDA , RDB > VIN(PK) – VBVD(MIN) where VIN(PK) is the peak input voltage measured with respect to VSS, and VBVD(MIN) is the minimum drain pin breakdown voltage (100V). Because their presence incurs no particular performance penalty, a minimum value of 20kΩ is prudent and protects the DA and DB pins against transients up to 300V, as shown in Figure 7. A practical limit for RDA and RDB is 100kΩ, beyond which their resistance interferes with the operation of the gate amplifier. Some speed penalty is incurred for values greater than 20kΩ, as shown in Figure 8. If the speed penalty is unacceptable, add a resistor and capacitor across RDA and RDB as shown in Figure 9 to restore the response time. LTC4371 GA SA VSS RDA 20k VA DA GA VOUT M1 4371 F07 C1 100pF VA tOFF (ns) 4371 F08 Figure 9. High Voltage Drain Pin Protection with C1 and R1 Maintaining Fast Turn-Off Time High Voltage DC Applications An extra blocking device is necessary to protect the DA and DB pins in applications where the DC input voltage exceeds 100V. Even in –48V applications the equivalent DC input voltage may exceed 100V, as a result of a reverse connected supply feed that can impress up to double the maximum operating voltage across the inputs. Because the 130V DA and DB pin clamps are limited to clamping short-term spikes, some other means of limiting the maximum applied voltage is necessary in DC applications. The N-channel cascode shown in Figure 10 extends the DC input operating voltage to 600V. It safely clamps the drain pin to about 2V less than VZ, yet introduces only 500Ω series resistance when the input is in the vicinity of VOUT; fast turn-off time is maintained. RZ VDD = 12.4V ∆VSD = 0.1V TO –0.4V CGATE = 3.3nF VZ 450 LTC4371 DA 300 GA SA VSS D1 IN4148W 150 M2 BSS127 VA 0 20 40 60 80 DRAIN PIN RESISTANCE (kΩ) 100 4371 F09 Figure 8. Reverse Response Time vs. Drain Pin Resistance 12 VOUT M1 Drain Pin Resistance 0 VSS RDA 100k R1 10k Figure 7. 300V Drain Pin Protection 600 SA (8) 10mA DA LTC4371 M1 VOUT 4371 F10 Figure 10. Drain Protection for Applications Up to –600V 4371f For more information www.linear.com/LTC4371 LTC4371 Applications Information Fuse and Open MOSFET Detection The LTC4371 monitors ∆VSD of each channel as measured across SA – DA and SB – DB. If ∆VSD of either channel exceeds 200mV and the associated gate pin is driven fully on, FAULTB pulls low to indicate a fault. Conditions leading to high ∆VSD include excessive load current (ILOAD × RDS(ON) > 200mV), an open circuit MOSFET or an open fuse placed in series with the MOSFET. A high ∆VSD fault is detected on only the highest voltage input supply, i.e. the path that should be supplying power is, as a result of one of the aforementioned conditions, unable to do so. Temporary conditions, such as the initial 700mV drop experienced when an input first rises to the point of supplying current but before the gate has been driven on, are masked since the gate must also be high for fault detection. Figure 12 shows a protection method that extends DA and DB pin operation to ±600V. The drain pins are clamped by an 82V Zener diode. As shown, the DA pin is clamped at 82V with respect to VSS in the positive direction, and 700mV below VSS in the negative direction. When a high input voltage of either polarity is present, back-to-back depletion mode N-channel MOSFETs limit the current in the Zener diode to VGS(TH)/RDA (100μA for RDA = 20kΩ), a value that is indefinitely sustainable. LTC4371 DA DB GA GB SA SB VSS D1 1N4148W D2 1N4148W RDA 20k VA –36V TO –72V VB –36V TO –72V RDB 20k F1 VOUT M1 F2 M2 4371 F11 Figure 11. Fuse and Open MOSFET Detection VSS RDA 20k M2* VA M1 *M2, M3: BSP135 (600V) DEPLETION NMOS VOUT 4371 F12 Figure 12. Back-to-Back Drain Pin Limiter for ±600V FAULTB Pin The open drain FAULTB pin pulls low when the ∆VSD of either channel exceeds 200mV, while its gate is driven fully on. FAULTB can sink 5mA to drive an LED for visual indication, or an opto isolator to communicate across an isolation barrier. The FAULTB pin voltage is limited to 17V absolute maximum with respect to VSS in the high state and cannot be pulled up to return except in low voltage applications. LTC4371 DA SA M3* The ∆VSD monitor can be used to detect open fuses, as shown in Figure 11. An open fuse gives the same signature as an open MOSFET: ∆VSD increases beyond 200mV when the affected input surpasses the opposing channel. The connection shown in Figure 11 introduces a new problem: an open fuse and open MOSFET exposes the DA and DB pins to high negative voltage with respect to VSS. Diodes D1 and D2 clamp the DA, DB pins from exceeding the absolute maximum of –40V with respect to VSS. GA 82V In Figure 13, the FAULTB pin is used to shunt current away from a green LED; the LED indicates (illuminates when) no fault condition is present. The operating voltage is limited at the low end by the minimum acceptable LED current, and at the high end by the FAULTB pin’s 5mA capability. Figure 14 shows a simple implementation driving a red LED; the LED indicates a fault condition is present. While this simple configuration works well in –48V applications, the maximum operating voltage is limited to 100V, the LED 4371f For more information www.linear.com/LTC4371 13 LTC4371 Applications Information current varies widely with operating voltage, and dissipation in the 20kΩ resistor reaches ≈250mW at 72V input. These shortcomings are eliminated by the slightly more complex circuit shown in Figure 15. A cascode shields the FAULTB pin from the high input voltage and dissipates no power under normal conditions, while the LED current remains constant regardless of input voltage when indicating a fault. At 600V, cascode dissipation reaches 600mW maximum. RTN LTC4371 R1 33k FAULTB VSS D1 GREEN LED = MOSFETS GOOD 4371 F13 VOUT Figure 13. FAULTB Drives a Green LED in Shunt Mode RTN R1 20k 500mW Layout Considerations A sample layout for the LTC4371 DFN package and PGHSOF-8 MOSFET package is shown in Figure 16. The VDD bypass capacitor C1 provides AC current to the device; place it as close to VDD and VSS pins as possible. Connect the gate amplifier input pins, DA, DB, SA and SB, directly to the MOSFETs’ drain and source terminals using Kelvin connections for good accuracy. Place the MOSFET sources as close together as possible, with VSS connecting at their intersection. Keep the traces to the MOSFET drains and common source wide and short. A good rule-of-thumb for minimizing self-heating effects in the copper traces is to allow at least 1-inch trace width per 50 amperes, for a surface layer of 1-ounce copper. This current density corresponds to a selfheating effect of about 1.3W per square inch. The traces associated with the power path through the MOSFETs must have low resistance to maintain good efficiency and low drop. The resistance of 1-ounce copper is approximately 500μΩ per square. D1 RED LED = MOSFET BAD LTC4371 R2 3.9k FAULTB VB VSS M2 4371 F14 VOUT Figure 14. FAULTB Drives a Red LED in Series Mode RTN RDB D1 RED LED = MOSFET BAD M2 BSP125 VDD LTC4371 C1 VOUT RDA R2 10k LTC4371 FAULTB VSS 4371 F15 VA VOUT M1 –600V MAX Figure 15. FAULTB Driving an LED in a High Voltage Application 4371 F16 Figure 16. Recommended PCB Layout for M1, M2 and C1 14 4371f For more information www.linear.com/LTC4371 LTC4371 Applications Information Design Example The following design example demonstrates the calculations involved for selecting external components. Consider a –48V application with a –36V to –72V operating range, 200V peak transient and 25A maximum load current (see Figure 17). The simplest configuration is chosen to power VDD, since this arrangement easily handles the operating conditions found in a –48V telecom power system. The bias resistor, RZ, is calculated from Equation 1: RZ < 36V – 11.8V = 32.2kΩ 750µA (9) ∆VSD = 25A • 2mΩ = 50mV (11) which is well below the 150mV minimum ∆VSD fault threshold. From Equation 7, the maximum power dissipation in the MOSFET is: PD(MOSFET) = 25A 2 • 2mΩ = 1.25W (12) a reasonable value for the proposed package. The minimum recommended value of 20kΩ is chosen for RDA and RDB. 20kΩ protects the DA and DB pins to 300V. The worst case power dissipation in RZ: The maximum voltage drop across the MOSFET is: The nearest lower 5% value is 30kΩ. PD(RZ) = Next, choose the N-channel MOSFET. The 100V, IPT020N10N3 in a PG-HSOF-8 package with RDS(ON) = 2mΩ (max) offers a good solution. (72V – 11.8V)2 = 166mW (10) 30k A 30kΩ 0.25W resistor is selected for RZ. The maximum VZ current is confirmed from Equation 3 as a safe value of 2mA. A –200V transient pushes this to 6.3mA, safely below the maximum allowable VZ current of 10mA. The LED, D1, requires at least 1mA of current to turn on fully; therefore, R1 is set to 33k to accommodate the minimum input supply voltage of –36V. The maximum current is 2mA at –72V, but excursions to 200V give 6mA, slightly beyond the FAULTB pin’s 5mA capability. This means that if there is a fault present, a brief glitch might cause a “no fault” indication during a 200V transient. Since D1 is a visual indicator, we’ll accept the remote chance of a dim flash in exchange for the simple circuit solution. RTN RZ 30k VZ R1 33k FAULTB LTC4371 DA RDA 20k VA –36V TO –72V VB –36V TO –72V DB GA C1 2.2μF VDD GB SA RDB 20k M1 IPT020N10N3 M2 IPT020N10N3 SB VSS D1 GREEN LED = MOSFETS GOOD VOUT 25A LOAD 4371 F17 Figure 17. –36V to –72V/25A Ideal Diode-OR 4371f For more information www.linear.com/LTC4371 15 LTC4371 Applications Information mum IDD of 9.5mA (LTC4371) + 1mA (LED) = 10.5mA, Equation 4 gives: As a second design example, consider modifying the circuit of Figure 17 to handle 300V transients and to drive a red LED, which illuminates when a fault is present (see Figure 18). RDA and RDB are sized to handle transients to 300V, so no change in their value is necessary. Modifications are necessary to drive the red LED. 10.5mA = 525µA 20 36V – 11.8V RZ < = 44k 10mA 50uA+ 20 IBASE = A PZTA42, a 300V NPN with a minimum β = 20 is chosen to supply both the LED and the VDD pin. With a maxi- (13) The nearest lower 5% value is 43k. To produce 1mA LED current with variations in the circuit, R1 is chosen to be 8.2k. RTN RZ 43k VZ Q1 PZTA42 VDD FAULTB LTC4371 DA DB RDA 20k VA –36V TO –72V VB –36V TO –72V GA R1 8.2k D1 RED LED = MOSFET BAD GB SA RDB 20k M1 IPT020N10N3 SB VSS C1 0.1μF VOUT 25A LOAD M2 IPT020N10N3 4371 F18 Figure 18. –36V to –72V/25A Ideal Diode-OR 16 4371f For more information www.linear.com/LTC4371 LTC4371 Typical Applications RTN RZ 30k R1 33k VZ VDD FAULTB LTC4371 DA DB GA GB SA SB VSS 2.2µF D1 GREEN LED = MOSFETS GOOD RD 20k VA –36V TO –72V VOUT 100A LOAD M1 – M4 IPT020N10N3 4371 F19 Figure 19. –36V to –72V Single Channel Parallel Application with 2× Gate Drive RTN R2 100Ω LTC4371 DA DB C1 2.2µF VDD VZ R1 33k FAULTB GB SA SB VSS GA D1 GREEN LED = MOSFETS GOOD M1 VA –12V VOUT 100A LOAD M2 *3×PSMN0R9-3YLD VB –12V M3 M1– M3 PSMN0R9-3YLD M4 4371 F20 M5 M6 M4 – M6 PSMN0R9-3YLD Figure 20. –12V/100A Application with 5mA Gate Pull-Up Enabled 4371f For more information www.linear.com/LTC4371 17 LTC4371 Typical Applications RTN RZ 120k R1 100k LTC4371 DA DB D2 1N4148 C1 2.2μF VDD VZ GA FAULTB GB SA SB VSS D1 GREEN LED = MOSFETS GOOD D3 1N4148 M3 BSP89 M4 BSP89 VA –100V TO –240V VOUT 5A LOAD M1 IPB200N25N3 VB –100V TO –240V M2 IPB200N25N3 4371 F21 Figure 21. –100V to –240V/5A Ideal Diode-OR Controller RTN RZ 172k Q1 PZTA42 VDD VZ LTC4371 DA C1 0.1μF DB GA R1 100k FAULTB GB SA SB VSS D2 MMSZ5268BTIG D1 GREEN LED = FUSES/MOSFETS GOOD D3 MMSZ5268BTIG VA –100V TO –240V VB –100V TO –240V M3 BSP129 M5 BSP129 RDA 20k RDB 20k M4 BSP129 M6 BSP129 F1 M1 IPB200N25N3 VOUT 5A LOAD F2 M2 IPB200N25N3 4371 F22 Figure 22. –100V to –240V/5A Ideal Diode-OR Controller with Open Fuse and MOSFET Detection 18 4371f For more information www.linear.com/LTC4371 LTC4371 Typical Applications + RZ 10k LTC4371 DA 48V CT VA RDA 20k DB C1 2.2μF VDD VZ GA R1 22k 24VDC 4A FAULTB GB SA SB VSS RDB 20k + D1 GREEN LED = MOSFETS GOOD CL 4×1000μF SUNCON ME-WX – M1 IPT020N10N3 117VAC VB M2 IPT020N10N3 4371 F23 Figure 23. Full Wave Center Tap Rectifier 4371f For more information www.linear.com/LTC4371 19 LTC4371 Package Description Please refer to http://www.linear.com/product/4371#packaging for the most recent package drawings. MS Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661 Rev F) 0.889 ±0.127 (.035 ±.005) 5.10 (.201) MIN 3.20 – 3.45 (.126 – .136) 3.00 ±0.102 (.118 ±.004) (NOTE 3) 0.50 0.305 ±0.038 (.0197) (.0120 ±.0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 10 9 8 7 6 3.00 ±0.102 (.118 ±.004) (NOTE 4) 4.90 ±0.152 (.193 ±.006) DETAIL “A” 0.497 ±0.076 (.0196 ±.003) REF 0° – 6° TYP GAUGE PLANE 1 2 3 4 5 0.53 ±0.152 (.021 ±.006) DETAIL “A” 0.18 (.007) SEATING PLANE 0.86 (.034) REF 1.10 (.043) MAX 0.17 – 0.27 (.007 – .011) TYP 0.50 (.0197) BSC NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 20 0.1016 ±0.0508 (.004 ±.002) MSOP (MS) 0213 REV F 4371f For more information www.linear.com/LTC4371 LTC4371 Package Description Please refer to http://www.linear.com/product/4371#packaging for the most recent package drawings. DD Package 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699 Rev C) 0.70 ±0.05 3.55 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 3.00 ±0.10 (4 SIDES) R = 0.125 TYP 6 0.40 ±0.10 10 1.65 ±0.10 (2 SIDES) PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER PIN 1 TOP MARK (SEE NOTE 6) 0.200 REF 0.75 ±0.05 0.00 – 0.05 5 1 (DD) DFN REV C 0310 0.25 ±0.05 0.50 BSC 2.38 ±0.10 (2 SIDES) BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 4371f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. For more information www.linear.com/LTC4371 21 LTC4371 Typical Application –48V Ideal Diode-OR with Fuse and Open MOSFET Detection RTN RZ 30k LTC4371 DA C1 2.2μF VDD VZ DB GA R1 33k FAULTB GB SA SB VSS D1 GREEN LED = FUSES/MOSFETS GOOD D2 1N4148W D3 1N4148W RDA 20k RDB 20k F1 VA –36V TO –72V VOUT 25A LOAD M1 IPT020N10N3 F2 VB –36V TO –72V M2 IPT020N10N3 4371 TA02 Related Parts PART NUMBER DESCRIPTION COMMENTS LTC4354 Negative Voltage Diode-OR Controller and Monitor Controls Two N-Channel MOSFETs, 1.2µs Turn-Off, –80V Operation LTC4355 Positive Voltage Diode-OR Controller and Monitor Controls Two N-Channel MOSFETs, 0.4µs Turn-Off, 80V Operation LTC4357 Positive Voltage Ideal Diode Controller Controls Single N-Channel MOSFET, 0.5µs Turn-Off, 80V Operation LT®4250 –48V Hot Swap Controller Active Current Limiting, Supplies from –20V to –80V LTC4251/LTC4251-1/ LTC4251-2 –48V Hot Swap Controllers in SOT-23 Fast Active Current Limiting, Supplies from –15V LTC4252-1/LTC4252-2/ LTC4252-A1/LTC4252-A2 –48V Hot Swap Controllers in MS8/MS10 Fast Active Current Limiting, Supplies from –15V, Drain Accelerated Response LTC4261/LTC4261-2 Negative Voltage Hot Swap Controllers with ADC and I2C Monitoring 10-Bit ADC, Floating Topology, Adjustable Inrush 22 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC4371 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC4371 4371f LT 0216 • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2016