VISHAY SEMICONDUCTORS www.vishay.com Optocouplers and Solid-State Relays Application Note 73 High-Speed/Logic Gate Optocoupler (SFH67XX Series) INTRODUCTION The new SFH67XX series of high-speed optocouplers is capable of transmitting data rates up to 5 Mb/s typical and 2.5 Mb/s over the full specified operating temperature range. The combination of low input current (1.6 mA) and active logic-level output is a fit for nearly all logic applications where a galvanic insulation is necessary. The SFH67XX series features positive logic with TTL output levels. For improved noise immunity the detector incorporates a schmitt-trigger stage. The SFH6700/19 provides an enable input, which allows switching the output into the high ohmic state for bus applications. For applications which need an open collector output, the SFH6705 is offered.The SFH6731 and SFH6732 are the dual versions. The two channels are free of crosstalk and interference. To ensure a high common mode transient immunity of guaranteed 2.5 kV/μs at 400 V, the SFH671X/6732 series features an internal shield which consists of an additional ITO layer. The ITO (indium tin oxide) layer is an optically transparent but electrically conductive layer on top of the detector. The standard SFH670X series withstands 1.0 kV/μs at VCM = 50 V. The SFH67XX series is also available in an SMD version (option 7 and 9 with > 8 mm creepage and clearance distance). SFH6701/11 SFH6700/19 NC 1 SFH6702/12 NC 1 8 VCC NC 1 8 VCC 8 VCC Anode 2 7 Out Anode 2 7 Out Anode 2 7 NC Cathode 3 6 VE Cathode 3 6 NC Cathode 3 6 Out NC 4 NC 4 5 GND Three-State-Output 5 GND NC 4 Totem-Pole-Output SFH6705 NC 1 5 GND Totem-Pole-Output SFH6731/32 8 VCC Anode 1 8 VCC Anode 2 7 NC Cathode 2 7 Out 1 Cathode 3 6 Out Cathode 3 6 Out 2 Anode 4 5 GND NC 4 17850 5 GND Open-Collector-Output Dual/Totem-Pole-Output Fig. 1 - Variations in the SFH67XX Family LED ENABLE SFH6700/19 On L Off L On H Off H SFH6701/02/05/11/12/31/32 On Off OUTPUT H L Z Z H L Truth table (positive logic) H = logic high level, L = logic low level, Z = high ohmic state Rev. 1.3, 29-Nov-11 The circuits shown below are intended to give the design engineer a guideline for logic family interconnection. Input Circuitry Below are stated the most common interface circuits which work for this coupler series. Totem Pole Drive Circuits Figures 2 and 3 are two of the most commonly used circuits. The designer chooses R1 according to the equation: V OH – V F R 1 = -----------------------IF (valid for figure 2) (1) Document Number: 83701 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 APPLICATION NOTE DESIGN CONSIDERATIONS TABLE 1 Application Note 73 www.vishay.com Vishay Semiconductors High-Speed/Logic Gate Optocoupler (SFH67XX Series) (valid for figure 3) (2) SFH6700/19 VDD TTL/ R1 Data LS TTL IN LOGIC For critical applications, where a high leakage current is expected, a shunt LED circuit, as shown in figure 5, is a good solution. VCC 8 1 NC Out 2 7 VE 6 3 GND GND 5 4 NC 17851 Fig. 2 - Series LED Drive SFH6700/19 1 NC R1 VDD Data IN TTL/ CMOS LOGIC 2 3 4 NC Due to the coupler’s typically low input current threshold of 0.50 mA and the negative temperature gradient of the input current threshold (see figure 4), the output leakage current of the driver element at high temperatures may become an issue in certain applications where the circuit is operated at the upper temperature range. VCC 8 Out 7 VE 6 Normalized Input Current Threshold (%) V DD – V OL – V F R 1 = ---------------------------------------IF 50 40 30 20 10 0 - 10 - 20 - 30 - 60 - 40 - 20 17853 0 20 40 60 TA - Temperature (°C) 80 100 Fig. 4 - Typical Input Current Threshold (Normalized) vs. Temperature SFH6700/19 GND 5 1 NC GND VCC 8 17852 Fig. 3 - Series LED Drive VDD A good compromise between low power dissipation and symmetrical propagation delays with respect to some guard band is IF = 3 mA. In some applications a speed-up capacitor (typically around 100 pF) across R1 may be used to achieve faster switching times (please refer to the end of this section for details). R1 2 R2 TTL/ 3 Data CMOS IN LOGIC 4 NC 17854 Out 7 VE 6 GND 5 GND Fig. 5 - Shunt LED Drive Circuit with Leakage Current Protection APPLICATION NOTE TABLE 2 FIGURE 2 3 LOGIC GATE (E.G.) R1 VALUE 74LS04 750 Ω 74LS04 1.10 kΩ 74HCT04 1.10 kΩ Typical values for R1 at VDD = 5 Both circuits are simple and feature a minimal component count with low power dissipation. A logic source drive, as shown in figure 2, is not recommended due to speed and current limitations (especially in the CMOS logic family), and lower common mode transient immunity. Rev. 1.3, 29-Nov-11 The resistor R1 determines the forward LED current, and R2 shunts the LED. The choice of R2 depends on power dissipation considerations and the expected leakage current. The following equations can help designers determine the appropriate resistor values: V Fmax(LEDoff) 1V R 2 = ---------------------------------- ⋅ -------------------I Leak at Temp I Leakage V DD – V F – V OL R 1 = ----------------------------------------- ⋅ R 2 VF + IF R2 (3) (4) Document Number: 83701 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Application Note 73 www.vishay.com Vishay Semiconductors High-Speed/Logic Gate Optocoupler (SFH67XX Series) TABLE 3 SFH6700/19 VDD IF R1 VALUE R2 VALUE 5V 3 mA 1.0 kΩ 4.7 kΩ VDD Typical input circuit values to shunt around 250 μA away from the LED (according to figure 5) Data Open Collector IN Drain V DD – V F R 1 = ----------------------IF (5) R1 VCC 8 Out 2 7 VE 6 3 A better way to handle leakage current is presented in figure 6. This circuit provides excellent speed properties and leakage current protection. The silicon diode D1 ensures that the current is only sourced by VDD and is therefore not required for units driven by an open collector or open drain. The low forward voltage of D1 ensures that the LED stays off at logic low. The equation to choose R1 is: 1 NC GND 4 NC GND 5 17856 Fig. 7 - Open Collector/Drain Shunt Drive Circuit TABLE 4 VDD IF R1 VALUE 5V 3 mA 1.10 kΩ 10 V 3 mA 2.80 kΩ 15 V 3 mA 4.42 kΩ Typical input circuit values for a circuit according to figure 7 Input Circuitry for Improved Switching Speeds If switching speed is a concern, the use of a speed-up capacitor is a good solution. The resistor R2 limits the peak transient current IFpeak, whereas R1 and R2 determine the current at steady-state operation. The equations and reasonable resistor values are printed below. SFH6700/19 VDD Data IN 1 NC R1 TTL/ CMOS LOGIC 2 VCC 8 Out 7 A reasonable value for the speed-up capacitor CS is 100 pF. D1 VE 6 3 CS GND 4 NC GND 5 VDD 17855 R1 Fig. 6 - Logic Gate Shunt Drive Circuit SFH6700/19 1 NC R2 2 VCC 8 Out 7 Open Collector Drive Circuits APPLICATION NOTE A simple circuit, which also works for open collector drive circuits, has been presented in figures 3 and 5. In figure 5, the resistor R2 represents a leakage current protection path. A more efficient but more power-dissipating solution is presented in figure 7. This drive circuit provides good speed and protection against leakage currents. The resistor R1 is chosen in accordance with V DD – V F R 1 = ----------------------IF (6) Refer to table 4 for some typical resistor values. Note that leakage protection generally might only be an issue in some special applications. Data IN 17857 TTL/ CMOS LOGIC 3 GND 4 NC VE 6 GND 5 Fig. 8 - Series LED Drive with Speed-up Capacitor The equations for the resistor values are: V DD – V OL – V F R 1 = ---------------------------------------I Fpeak (7) V DD – V OL – V F R 1 = ---------------------------------------- – R2 IF (8) The maximum IFpeak for this transient is 50 mA for the SFH67XX series. Rev. 1.3, 29-Nov-11 Document Number: 83701 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Application Note 73 www.vishay.com Vishay Semiconductors High-Speed/Logic Gate Optocoupler (SFH67XX Series) There are three simple ways to connect CMOS logic to the SFH67XX coupler family: TABLE 5 VDD CS VALUE R1 VALUE R2 VALUE 5V 100 pF 1.0 kΩ 75 Ω Typical input circuit values for a circuit according to figure 8 Output Circuitry One advantage of the SFH67XX series is its easy connection to any logic system, because of the active output stage (totem pole/three state output). Either directly or via a pull-up resistor, all couplers can drive up to 16 LS TTL loads (4 TTL loads) easily. In general, a 0.1 μF bypass capacitor is strongly recommended for proper operation. • Using SFH67XX (totem pole) and a pull-up resistor (see figure 12) • Using SFH6705 (open collector) and a pull-up resistor (see figure 11) • Using an HCT logic device (see figure 10) Using an HCT device is the simplest and most convenient solution to eliminate the external pull-up resistor (see figure 10). The designer doesn’t have to worry about power consumption, rise times, or system speed. SFH6701/11 The SFH6700/19 with its three-state output fits best in bus applications because of the possibility to switch the couplers output into the high ohmic state (for a typical setup please refer to figure 28). 1 NC 2 VCC 8 Out VCC 7 HCT Input Drive Circuits for the Dual-Channel Devices The SFH6731/32 can be driven as simply as the single channel devices. 3 All the above drive circuits and equations (1) to (8) can be adapted to drive the dual-channel devices. (The use of the dual-channel devices reduces the number of parts and the required board space.) 4 NC NC 6 Data Out at CMOS Logic Level 0.1 µF GND 5 GND 17858 Fig. 10 - Interfacing to CMOS Logic Level via a HCT Device Interfacing to TTL/TTL-Compatible Logic Interfacing the SFH67XX coupler to LS TTL or any other compatible logic is quite simple. The active output of this coupler eliminates the need for an external pull up resistor, and minimizes parts count and board space requirements. The typical connection is seen in figure 9. Even HCT logic can be interfaced this way. SFH6701/11 1 NC 2 3 VCC 8 Out 7 VCC TTL/ LS TTL INPUT NC 6 APPLICATION NOTE GND 5 V CCmax – V OLmin R Pmin = ----------------------------------------------I OLmax + n ⋅ I IL (9) where n · IIL represents the total load current at low level VOL. (To ensure VOLmax < 0.5 V over temperature IOLmax should be set not higher than 6.4 mA). The maximum RP value can be determined by: Data Out 0.1 µF 4 NC Using the open collector device, as in figure 11, requires an external pull-up resistor RP . To determine the correct value of this pull-up resistor, use following equations: GND V CCmin – V IHmin R Pmin = -------------------------------------------I OHmax + n ⋅ I IH (10) In CMOS applications however, where IIH is in the μA region, the limiting factor can also be determined by the maximum allowable rise time tr (500 ns for HC logic). The equation –t 18014 Fig. 9 - Interfacing the Coupler to TTL, LSTTL or Compatible Logic Interfacing to CMOS Logic To ensure reliable logic switching, a pull-up resistor between the output and VCC is recommended (see Figures 11 and 12). For the HCT logic family, this pull-up resistor may be omitted, due to the matching switching level of the coupler’s output and the HCT input. Rev. 1.3, 29-Nov-11 ---------------- RP CL V H = V CC 1 – e (11) leads to – tr R Pmax = -----------------------------------------------------V IHmin C L ⋅ 1n 1 – -------------------- V CCmin (12) Document Number: 83701 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Application Note 73 www.vishay.com Vishay Semiconductors High-Speed/Logic Gate Optocoupler (SFH67XX Series) in which CL represents the total capacitance of the load, including the coupler (which is around 6 pF). The resistor value is a compromise between the requirement of power dissipation and switching speed. A low RP produces symmetrical and fast switching times but results in a higher power dissipation. Reasonable values are shown in table 6. Details of the relationship between the rise time t r and the pull-up resistor RP/load capacitance CL are shown in figure 14. SFH6705 1 NC V CC 8 2 NC 7 3 Out 6 VCC 0.1 µF Note that generally the RP value has a negligible influence on the delay time td, but it strongly determines the rise time, especially for the open collector type. Interfacing to 3.3 V Level Interfacing to the 3.3 V logic families (e.g. AC, AHC, or HC) is quite easy, and presented in figure 13. If the totem pole/three-state coupler is operated with VCC = 5 V, then the output “high” level of the coupler, which is then typically 3.2 V, matches perfectly with the 3.3 V logic input levels. In general, the output “high” voltage can be determined by VOH ≈ VCC - 1.8 V. (Even with VCC = 5.0 V ± 10 %, the output voltage is within the limits, and is guaranteed to be higher than 2.4 V over temperature to fulfill the 3 V logic requirement). Rp SFH6701/11 4 NC CMOS Input Data Out 1 NC GND 5 2 GND 17859 3 VCC 8 Out 7 By using a totem pole device, the equations (9) and (10) are also valid, but the pull-up resistor has only to bring up the voltage difference between VOH (≈ VCC - 1.8 V) and the input switching limit, e.g. 3.5 V for HC logic, which makes a ΔV of 0.3 V. This allows the use of a higher RP which results in lower power consumption. SFH6701/11 Out 2 VCC RP 7 CMOS Input Data Out NC 6 3 APPLICATION NOTE 0.1 µF 4 NC GND 5 3.3 V Logic Data Out 0.1 µF 4 NC VCC 8 3.3 V NC 6 Fig. 11 - Interfacing SFH6705 (Open Collector Output) to CMOS Logic 1 NC 5.0 V GND 17860 GND 5 GND 17861 Fig. 13 - Interfacing to 3.3 V Logic with VCC = 5 V Interfacing to other Levels If shifting to any other level is intended (e.g. 2.5 V logic, like the ALVC or ALVT series), the SFH6705 with its open collector output is qualified. RP works as a pull-up resistor to ensure the proper logic high level. The basic principles are the same as described in the section “interfacing to CMOS logic” in equations (9) to (12). Pull-Up Resistor Considerations for the Open Collector Type SFH6705 As previously mentioned above, the pull-up resistor has to be chosen in accordance with the equations (9), (10), and (12). Figure 14 plots the expected rise time tr versus the time constant τ = RP x CL. Unlike the rise time tr, the fall time tf is mostly independent of RP and around 5 ns. Fig. 12 - Interfacing SFH67XX (Totem Pole Output) to CMOS Logic TABLE 6 VCC RP (OPEN COLLECTOR) RP (TOTEM POLE) 5V 820 Ω 1.10 kΩ Typical values for Rp by connecting to CMOS logic (according to figures 11 and 12). Rev. 1.3, 29-Nov-11 Document Number: 83701 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Application Note 73 www.vishay.com Vishay Semiconductors High-Speed/Logic Gate Optocoupler (SFH67XX Series) A layout which implements these hints is seen in figure 16. Note that this layout reduces creepage and clearance distance as well. 1000 900 Rise Time, t r (ns) 800 700 600 VCC (top layer) SFH6719 500 400 300 200 100 0 1 10 100 RC Time Constant (ns) 18015 0.1 µF 1000 Fig. 14 - Typical Rise Time vs. Load for VCC = 5 V (Test Circuit See Figure 15) SFH6705 1 NC VCC 8 2 NC 7 VCC = 5 V 0.1 µF Fig. 16 - Principle Board Layout for Enhanced CMTI (Fits to Schematic in Figure 18) Out RP A circuit which enhances CMTI safety is shown in figure 17. tr Out 6 3 4 NC GND (bottom layer) 17863 5 GND The diode D1 is intended to sink parasitic current, which is caused by stray capacitance, away from the LED to prevent a false turn-on. Out CL GND IF Time SFH6719 17862 D1* Fig. 15 - Test Circuit for Rise Time tr vs. Time Constant VDD COMMON-MODE TRANSIENT IMMUNITY (CMTI) APPLICATION NOTE The SFH6711/12/19 feature a guaranteed common mode transient immunity (CMTI) of 2.5 kV/μs at 400 V. This is achieved by using a faraday shield which is transparent to infrared light, but electrically conducting. This shield prevents the photodiode from being turned on by common-mode transients. 1 NC 2 VCC 8 Out 7 R1 Data IN VE 6 3 CMOS LOGIC 4 NC GND 5 GND 17864 Fig. 17 - Input Circuitry for Improved CMTI In general there are some design rules to achieve a high CMTI. These recommendations are especially important for low LED drive current devices, like the SFH67XX series: * Diode D1: Any signaling diode • Connect the unused pins 1 and 4 to the virtually grounded input potential (either GND or VDD). The transistor shunts the LED in the off-state and prevents a false turn on. This circuit tolerates very high common mode transients in the LED off-state. An improvement in the LED on-state can be reached by choosing a high IF current. For VDD = 5 V, R1 is typically around 1.1 kΩ. • Minimize stray capacitance. • Avoid long distances between LED input circuit and coupler. Another input circuit for high CMTI is shown in figure 18. • Choose an appropriate high LED forward current to improve CMH (common mode transient immunity at logic “high” level). Rev. 1.3, 29-Nov-11 Document Number: 83701 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Application Note 73 www.vishay.com Vishay Semiconductors High-Speed/Logic Gate Optocoupler (SFH67XX Series) Pulse Width Distortion SFH6719 VCC 8 1 NC VDD R1 Out 2 Data IN RS 7 Q1* VE 6 3 4 NC GND 5 GND 17865 Pulse width distortion (PWD) is defined as the difference between tPHL and tPLH (PWD = |tPHL – tPLH|). This value is important in applications where symmetrical switching times are required, e.g. in systems which are based on pulse width modulation. In transmission systems, the PWD should not exceed 30 % of the minimum propagation delay time. At IF = 3.0 mA LED forward current, the SFH67xx has a typical PWD of around 20 ns over temperature, which corresponds to a maximum PWD of 20 %. Note that the use of a speed up capacitor decreases tPLH but might increase the PWD. Fig. 18 - Input Circuitry for High CMTI A common way to achieve ultra-high CMTI is presented in figure 19. The balanced input impedance principle works with four resistors, R1 = R2 and R3 = R4. R1 and R2 are used to minimize any noticeable LED current when the transistor is on. To achieve maximum performance, the stray capacitance from anode or cathode to the output side of the coupler has to be kept as low as possible. Reasonable values with Q1 = 2N2222 are R3 = R4= 510 Ω and R1 = R2 omitted. Note that R1 and R2 can be omitted, depending on the VCE of the transistor Q1. SFH6719 1 NC VCC 8 VDD R3* 2 Q1** Signal IN R4* Out 7 R1* VE 6 3 R2* 4 NC GND 5 Pulse Width Distor tion, PWD (ns) * Transistor Q1: Any switching transistor (e.g. 2N2222) * Resistor R1 = R2 and R3 = R4: To achieve a balanced input impedance ** Transistor Q1: Any switching transistor DYNAMIC OPERATION The SFH67XX series of active pull-up outputs offer a guaranteed maximum propagation delay time of 300 ns over temperature and as well as a guaranteed 2.5 Mb/s data rate over temperature. 30 20 10 0 - 60 - 40 - 20 0 20 40 60 Temperature, TA (°C) 80 100 Fig. 20 - Typical Pulse Width Distortion over Temperature at IF = 3 mA (Test Circuit See Figure 24) Propagation Delay Skew Propagation delay skew (tPSK) is the difference between the minimum propagation delay, either tPHL or tPLH, and the maximum propagation delay, either tPLH or tPHL, between any SFH67XX coupler under the same operation conditions. Propagation delay skew is therefore an important value for parallel data transmission, where synchronized data is needed. Propagation Delay Skew, t PSK (ns) APPLICATION NOTE Fig. 19 - Balanced Input Impedance Circuitry 40 17867 GND 17866 50 60 50 40 30 20 10 17868 0 - 60 - 40 - 20 0 20 40 60 80 100 TA - Temperature (°C) Fig. 21 - Typical Propagation delay Skew over Temperature at IF = 3 mA (Test Circuit See Figure 24) Rev. 1.3, 29-Nov-11 Document Number: 83701 7 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Application Note 73 www.vishay.com Vishay Semiconductors High-Speed/Logic Gate Optocoupler (SFH67XX Series) In logic circuits, the overall PWD and tPSK are determined by all input and output logic gates in the signal path. To minimize the overall PWD, two identical couplers may be used as shown in figure 22. But the minimum PWD is achieved at the cost of a higher overall propagation delay. 5V SFH6702/12 VCC 8 1.1 kΩ 1 NC 1k 2 74LS04 3 5V 4 NC GND 5 Optocouplers are commonly used as an interface between two circuits, where galvanic insulation is required, either to protect humans or sensitive electronic equipment. Based on this requirement, some designs are presented below, which use the SFH67XX series. 5V IGBT/IPM Driver SFH6702/12 VCC 8 1 NC NC 7 1.1 kΩ 2 6 DESIGN IDEAS NC 7 3 6 0.1 µF 4 NC 0.1 µF 74LS04 GND 5 17869 Fig. 22 The SFH67XX series can be used as a fast driver for intelligent power modules (IPMs) using IGBT or MOSFET technology. The SFH67XX optocoupler series provide level shifting and galvanic insulation and is therefore the ideal interface to the control logic. With its guaranteed minimum 2.5 kV/μs at 400 V common mode transient immunity, the SFH671X also fulfills enhanced switching requirements. Eye Pattern Diagram Switching Loads A typical eye pattern diagram for 5 Mb/s data transmission is presented in figure 23. The eye pattern testing was done with a pseudo random data sequence (NRZ coding). The SFH67XX series can easily handle currents up to 25 mADC and voltages up to 15 V. Figures 26 and 27 show how it can handle loads which are beyond these limits. In figure 26, R1 is used as a pull-up resistor and the load current is handled and limited by the external transistor Q1. Unlike figure 27, the schematic in figure 26 is qualified to support both high voltages and currents. The 5 V power supply might be raised up to 15 V to achieve a proper VGS voltage to turn the transistor fully on. The combination of the SFH67XX series with logic level power transistors provides a fast-switching solution that helps to reduce parts count. 17870 Fig. 23 Output Monitoring SFH6701/11 APPLICATION NOTE 1 NC 1.1 k 5V 74LS04 2 3 4 NC VCC 8 Out 7 NC 6 5V 74LS04 0.1 µF GND 5 GND Input Monitoring 17871 Fig. 24 Rev. 1.3, 29-Nov-11 Document Number: 83701 8 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Application Note 73 www.vishay.com Vishay Semiconductors High-Speed/Logic Gate Optocoupler (SFH67XX Series) + VS Galvanic Insulation + VCC IPM - Intelligent Power Module + HV SFH6711 IGBT/MOSFET Driver VCC 8 1 NC BAR 74 5V 2 Out 7 3 NC 6 IGBT Module 1.1 kΩ Data IN 74HCT04 Protection/ Suppression Unit 0.1 µF 4 NC GND 5 GND GND 17872 Fig. 25 VCC 8 1 NC Time Multiplexed Bus Line Access with Optical Insulation Barrier VSS SFH6712 5V LOAD 2 NC 7 3 Out 6 R1** 1 kΩ Q1* BSP89 0.1µF BUZ104SL BUZ73L GND 5 4 NC 17873 Q1: Any n-channel Opto-Insulated DAC Interface When galvanic insulation in digital-to-analog-conversion or analog-to-digital-conversion systems is required, the SFH67XX series is a good choice for an interface. GND Fig. 26 * Transistor transistor The schematic in figure 28 shows the use of a common data bus line with 4 independent data lines in time multiplexing mode. The 2-line to 4-line address decoder selects one of the 4 data lines by enabling the output, whereas all the other outputs remain in the high ohmic state. enhancement-mode ** Resistor R1: R1 might be omitted, depending on the necessary VGS of Q1 to turn Q1 fully on Setups like the one in figure 29 provide a fast and part saving insulation barrier. The low propagation delay skew of the SFH67XX devices makes them ideal for use in parallel data transfer. The SFH67XX series provide an optimal interface solution for the SAB 80 C167/C165 micro-controllers by supporting the 5 Mb/s data rate at a 20 MHz CPU clock. APPLICATION NOTE SFH6711 1 NC VCC 8 2 Out 7 VSS 1 kΩ Q1* SP0610T 3 NC 6 0.1µF LOAD 4 NC GND 5 GND 17874 Fig. 27 * Transistor transistor Q1: Rev. 1.3, 29-Nov-11 Any p-channel enhancement-mode Document Number: 83701 9 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Application Note 73 www.vishay.com Vishay Semiconductors High-Speed/Logic Gate Optocoupler (SFH67XX Series) Galvanic Insulation Barrier 5 5V V Common Data Bus SFH6700/19 1 NC 1.1 kΩ 2 V CC 8 Out 7 0.1 µF Data Line 1 VE 6 3 74HCT04 4 NC GND 5 SFH6700/19 1 NC V CC 8 1.1 kΩ 2 Out 7 3 VE 6 0.1 µF Data Line 2 74HCT04 4 NC A GND 5 Y0 B Y1 74HCT139 2-Line to 4-Line Y2 Decoder SFH6700/19 1 NC V CC 8 G 1.1 kΩ 2 Select Inputs Enable Y3 Out 7 0.1 µF Data Line 3 VE 6 3 74HCT04 Truth Tabl e 4 NC GND 5 APPLICATION NOTE SFH6700/19 1 NC 1.1 kΩ V CC 8 2 Out 7 3 VE 6 G B A Active on Bus Line H X X None (all high ohmic) L L L Data Line 1 L L H Data Line 2 L H L Data Line 3 L H H Data Line 4 0.1 µF Data Line 4 74HCT04 4 NC GND 5 Common Data Bus 17875 Fig. 28 - Typical Setup for a Common Bus Line with 4 Different Lines in Time Multiplex Mode Rev. 1.3, 29-Nov-11 Document Number: 83701 10 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Application Note 73 www.vishay.com Vishay Semiconductors High-Speed/Logic Gate Optocoupler (SFH67XX Series) 5V Galvanic Insulation Barrier 0.33 µF 5V 78L05 0.33 µF D1 MAX845 Transformer Driver SD D2 GND1 GND2 2.2 µF 0.33 µF 2 x BAW56 Diodes 0.1 µF HALO TGM-030P3 Transformer SAB 80C167 Microcontroller** V DD REFAB SFH6731/32 Synchronous Serial Channel (SSC)/SPI 1.1 kΩ 1 V CC 8 CL REFCD Out 1 P3.13/SCLK CLK P3.9/MTSR Data 2 74HCT04* 7 3 6 1.1 kΩ 4 GND 5 1 NC 1.1 kΩ 2 10 kΩ DIN 74HCT04* 3 4 NC FBB 10 kΩ 10 kΩ OUTB 10 kΩ 10 kΩ 7 NC 6 GND 5 Channel A 0...5 V Channel B 0...5 V FBC CS 0.1 µF CS OUTA MAX525 Digital-to-Analog Converter V CC 8 Out FBA 0.1 µF Out 2 74HCT04* 10 kΩ SCLK SFH6701/11 PX.Y 2.5 V + V CC FS MAX873 DOUT OUTC FBD UPO PDL GNDD 10 kΩ 10 kΩ OUTD Channel C 0...5 V Channel D 0...5 V AGND 17876 Fig. 29 - Fully Galvanic Insulated Digital-to-Analog-Conversion System (4 Channel DAC) APPLICATION NOTE * Inverter 74HCT04 is used to allow 3 mA LED current ** Any C16X micro-controller can be used Rev. 1.3, 29-Nov-11 Document Number: 83701 11 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000