SN54GTL16612A, SN74GTL16612A 18-BIT LVTTL-TO-GTL+ UNIVERSAL BUS TRANSCEIVERS www.ti.com SCES187D – JANUARY 1999 – REVISED JULY 2005 • FEATURES • • • • • • Members of the Texas Instruments Widebus™ Family Universal Bus Transceiver (UBT™) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Modes Translate Between GTL/GTL+ Signal Levels and LVTTL Logic Levels Support Mixed-Mode (3.3-V and 5-V) Signal Operation on A-Port and Control Inputs B-Port Transition Time Optimized for Distributed Backplane Loads Ioff Supports Partial-Power-Down Mode Operation Bus Hold on A-Port Inputs Eliminates the Need for External Pullup/Pulldown Resistors Distributed VCC and GND-Pin Configuration Minimizes High-Speed Switching Noise ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Ceramic Flat (WD) Packages • • • • xxx DESCRIPTION The 'GTL16612A devices are 18-bit universal bus transceivers (UBT) that provide LVTTL-to-GTL+ and GTL+-to-LVTTL signal-level translation. They allow for transparent, latched, clocked, or clock-enabled modes of data transfer. These devices provide a high-speed interface between cards operating at LVTTL logic levels and backplanes operating at GTL+ signal levels. High-speed (about two times faster than standard LVTTL or TTL) backplane operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and output edge control (OEC™). Improved GTL+ OEC circuits minimize bus settling time and have been designed and tested using several backplane models. Figure 1 shows actual device output waveforms using a synchronous clock at 75 MHz. The test backplane is a 16-slot, 14-inch board with loaded impedance of 33 Ω. VTT is 1.5 V, VREF is 1 V, and RTT pullup resistor is 50 Ω. The driver is in slot 8, with receivers in alternate slots 1, 3, 5, 7, 10, 12, 14, and 16. Receiver slot-1 signals are shown. The signal becomes progressively worse as the receiver moves closer to the driver or the spacing between receiver cards is reduced. The clock is independent of the data, and the system clock frequency is limited by the backplane flight time to about 80-90 MHz. This frequency can be increased even more (30% to 40%) if the clock is generated and transmitted together with the data from the driver card (source synchronous). VTT VTT 1.8 0.25” 0.875” R TT R TT TI GTL16612 0.25” 1.6 0.625” Conn. 1” Conn. 0.625” 0.625” Conn. 1” 1” Conn. Volts − V 1.4 0.625” Fairchild GTLP16612 1.2 1.0 TI GTL16612A 0.8 1” 0.6 Rcvr Rcvr Rcvr 0.4 Drvr Slot 1 Slot 2 Slot 8 0 Slot 16 10 20 30 t − Time − ns Figure 1. Test Backplane Model With Output Waveform Results Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus, UBT, OEC, TI are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999–2005, Texas Instruments Incorporated On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. SN54GTL16612A, SN74GTL16612A 18-BIT LVTTL-TO-GTL+ UNIVERSAL BUS TRANSCEIVERS www.ti.com SCES187D – JANUARY 1999 – REVISED JULY 2005 DESCRIPTION (CONTINUED) Additional design considerations can be found in Application Information at the end of this data sheet. These 18-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, clocked, and clock-enabled modes. These UBTs can replace any of the functions shown in Table 1. Table 1. 'GTL16612A UBT Replacement Functions FUNCTION 8 BIT 9 BIT 10 BIT Transceiver '245, '623, '645 '863 Buffer/driver '241, '244, '541 Latched transceiver 16 BIT 18 BIT '861 '16245, '16623 '16863 '827 '16241, '16244, '16541 '16825 '16543 '16472 '16373 '16843 '16646, '16652 '16474 '543 Latch '373, '573 Registered transceiver '646, '652 Flip-flop '374, '574 '843 '841 '821 '16374 Standard UBT '16500, '16501 Universal bus driver '16835 Registered transceiver with CLK enable '2952 Flip-flop with CLK enable '377 '16470, '16952 '823 Standard UBT with CLK enable '16823 '16600, '16601 'GTL16612A UBT replaces all above functions xxx GTL+ is the Texas Instruments (TI™) derivative of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3. The AC specification of the 'GTL16612A is given only at the preferred higher noise margin GTL+, but this device can be used at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTL+ (VTT = 1.5 V and VREF = 1 V) signal levels. The B port normally operates at GTL or GTL+ levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V tolerant. VREF is the reference input voltage for the B port. To improve signal integrity, the 'GTL16612A B-port output transition time is optimized for distributed backplane loads. VCC (5 V) supplies the internal and GTL circuitry, while VCC (3.3 V) supplies the LVTTL output buffers. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock or latch enable can be controlled by the clock-enable (CEAB and CEBA) inputs. For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CEAB is low and CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB if CEAB also is low. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that for A to B, but uses OEBA, LEBA, CLKBA, and CEBA. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The SN54GTL16612A is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74GTL16612A is characterized for operation from –40°C to 85°C. 2 www.ti.com SN54GTL16612A, SN74GTL16612A 18-BIT LVTTL-TO-GTL+ UNIVERSAL BUS TRANSCEIVERS SCES187D – JANUARY 1999 – REVISED JULY 2005 SN54GTL16612A . . . WD PACKAGE SN74GTL16612A . . . DGG OR DL PACKAGE (TOP VIEW) OEAB LEAB A1 GND A2 A3 VCC (3.3 V) A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC (3.3 V) A16 A17 GND A18 OEBA LEBA 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 CEAB CLKAB B1 GND B2 B3 VCC (5 V) B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VREF B16 B17 GND B18 CLKBA CEBA 3 SN54GTL16612A, SN74GTL16612A 18-BIT LVTTL-TO-GTL+ UNIVERSAL BUS TRANSCEIVERS www.ti.com SCES187D – JANUARY 1999 – REVISED JULY 2005 FUNCTION TABLE (1) INPUTS CEAB OEAB LEAB X H L L L (1) (2) (3) OUTPUT B MODE X Z Isolation X B0 (2) X B0 (3) CLKAB A X X L H L L L X L H X L L X L H X H H L L L ↑ L L L L L ↑ H H H L L X X B0 (3) Latched storage of A data Transparent Clocked storage of A data Clock inhibit A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, LEBA, CLKBA, and CEBA. Output level before the indicated steady-state input conditions were established, provided that CLKAB was high before LEAB went low Output level before the indicated steady-state input conditions were established LOGIC DIAGRAM (POSITIVE LOGIC) 35 VREF 1 OEAB CEAB 56 55 CLKAB 2 LEAB 28 LEBA 30 CLKBA CEBA 29 27 OEBA CE 1D 3 A1 C1 CLK CE 1D C1 CLK To 17 Other Channels 4 54 B1 SN54GTL16612A, SN74GTL16612A 18-BIT LVTTL-TO-GTL+ UNIVERSAL BUS TRANSCEIVERS www.ti.com SCES187D – JANUARY 1999 – REVISED JULY 2005 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC Supply voltage range VI Input voltage range (2) VO Voltage range applied to any output in the high or power-off state (2) IO Current into any output in the low state IO Current into any A-port output in the high state (3) MIN MAX 3.3 V –0.5 4.6 5V –0.5 7 A-port and control inputs –0.5 7 B port and VREF –0.5 4.6 A port –0.5 7 B port –0.5 4.6 A port 128 B port 80 Continuous current through each VCC or GND UNIT V V V mA 64 mA ±100 mA IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA θJA Package thermal impedance (4) Tstg Storage temperature range (1) (2) (3) (4) DGG package 64 DL package 56 –65 150 °C/W °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This current flows only when the output is in the high state and VO > VCC. The package thermal impedance is calculated in accordance with JESD 51. Recommended Operating Conditions (1) (2) (3) SN54GTL16612A MIN NOM MAX MIN NOM MAX 3.3 V 3.15 3.3 3.45 3.15 3.3 3.45 5V 4.75 5 5.25 4.75 5 5.25 GTL 1.14 1.2 1.26 1.14 1.2 1.26 GTL+ 1.35 1.5 1.65 1.35 1.5 1.65 GTL 0.74 0.8 0.87 0.74 0.8 0.87 GTL+ 0.87 1 1.1 0.87 1 1.1 VCC Supply voltage VTT Termination voltage VREF Supply voltage VI Input voltage VIH High-level input voltage B port VIL Low-level input voltage B port IIK Input clamp current IOH High-level output current IOL Low-level output current TA Operating free-air temperature (1) (2) (3) SN74GTL16612A B port VTT VTT Except B port 5.5 5.5 Except B port VREF + 50 mV VREF + 50 mV 2 2 UNIT V V V V V VREF – 50 mV VREF – 50 mV 0.8 0.8 –18 –18 mA A port –32 –32 mA A port 64 64 B port 34 34 Except B port –55 125 –40 85 V mA °C All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Normal connection sequence is GND first, VCC = 5 V second, and VCC = 3.3 V, I/O, control inputs, VTT, and VREF (any order) last. VTT and RTT can be adjusted to accommodate backplane impedances as long as they do not exceed the DC absolute IOL ratings. Similarly, VREF can be adjusted to optimize noise margins, but normally is 2/3 VTT. 5 SN54GTL16612A, SN74GTL16612A 18-BIT LVTTL-TO-GTL+ UNIVERSAL BUS TRANSCEIVERS www.ti.com SCES187D – JANUARY 1999 – REVISED JULY 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH A port TEST CONDITIONS VCC (3.3 V) = 3.15 V, VCC (5 V) = 4.75 V II = –18 mA VCC (3.3 V) = 3.15 V to 3.45 V, VCC (5 V) = 4.75 V to 5.25 V IOH = –100 µA VCC (3.3 V) = 3.15 V, VCC (5 V) = 4.75 V A port VOL II VCC (3.3 V) = 3.15 V, VCC (5 V) = 4.75 V IOH = –32 mA IOZH IOZL Cio (1) (2) (3) (4) (5) 6 2.4 2.4 2 0.4 0.5 0.5 IOL = 64 mA 0.6 0.55 0.65 0.65 VI = 5.5 V 10 10 VI = 5.5 V 1000 20 VI = VCC (3.3 V) VI = 0 VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V VI = VCC (3.3 V) VCC = 0, VI or VO = 0 to 4.5 V VI = 0 VI = 2 V 1 1 –30 –30 5 5 –5 –5 1000 100 75 75 –75 –75 VI = 0 to VCC (3.3 V) (2) ±500 1 1 VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V B port VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, VO = 1.5 V 10 10 A port VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, VO = 0 –1 –1 B port VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, VO = 0.65 V –10 –10 VO = VCC (3.3 V) VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, IO = 0, VI = VCC (3.3 V) or GND (3), VI = VTT or GND (4) Outputs high 1 1 Outputs low 5 5 Outputs disabled 1 1 VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, IO = 0, VI = VCC (3.3 V) or GND (3), VI = VTT or GND (4) Outputs high 120 120 Outputs low 120 120 Outputs disabled 120 120 1 1 VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, One A-port or control input at 2.7 V, Other A-port or control inputs at VCC (3.3 V) or GND Control inputs VI = 3.15 V or 0 A port VO = 3.15 V or 0 B port VO = 1.5 V or 0 V V µA µA µA ±500 A port A or B port UNIT 2 0.4 A port ∆ICC (3.3 V) (5) Ci VCC (3.3 V) – 0.2 IOL = 32 mA VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V ICC A or (3.3 V) B port ICC (5 V) VCC (3.3 V) – 0.2 IOL = 16 mA VCC (3.3 V) = 0 or 3.45 V, VCC (5 V) = 0 or 5.25 V VCC (3.3 V) = 3.15 V, VCC (5 V) = 4.75 V –1.2 0.2 VCC (3.3 V) = 3.15 V, VCC (5 V) = 4.75 V, IOL = 34 mA A port –1.2 0.2 VI = 0.8 V II(hold) MIN TYP (1) MAX IOL = 100 µA Control inputs Ioff SN74GTL16612A MIN TYP (1) MAX V IOH = –8 mA B port B port SN54GTL16612A 4 12 4 8.5 18 8.5 10 8 All typical values are at VCC (3.3 V) = 3.3 V, VCC (5 V) = 5 V, TA = 25°C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. This is the VI for A-port or control inputs. This is the VI for B port. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. µA µA mA mA mA pF pF SN54GTL16612A, SN74GTL16612A 18-BIT LVTTL-TO-GTL+ UNIVERSAL BUS TRANSCEIVERS www.ti.com SCES187D – JANUARY 1999 – REVISED JULY 2005 Timing Requirements over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTL+ (unless otherwise noted) (see Figure 2) SN54GTL16612A (1) MIN fclock tw tsu th (1) SN74GTL16612A MAX Clock frequency MIN MAX 85 Pulse duration Setup time Hold time 85 LEAB or LEBA high 3.3 3.3 CLKAB or CLKBA high or low 5.7 5.7 A before CLKAB↑ 1 1 B before CLKBA↑ 2.7 1.8 A before LEAB↓ 1.7 0.5 B before LEBA↓ 1.2 1.2 CEAB before CLKAB↑ 1.3 1.2 CEBA before CLKBA↑ 1.8 1.4 A after CLKAB↑ 3.2 1.9 B after CLKBA↑ 4.3 0.5 A after LEAB↓ 3.2 2.7 B after LEBA↓ 4.2 3.5 CEAB after CLKAB↑ 2.4 1.2 CEBA after CLKBA↑ 1.1 1.1 UNIT MHz ns ns ns Product preview Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTL+ (see Figure 2) PARAMETER TO (OUTPUT) SN54GTL16612A (1) MIN TYP (2) SN74GTL16612A MAX MIN TYP (2) MAX fmax 85 tPLH 2 7.3 2.5 6.9 2.2 7.4 2.5 6.9 2.2 7.5 3.2 7.3 2.3 7.9 3.2 7.3 2.1 8 3.4 7.8 2.5 7.9 3.4 7.8 1.8 7.4 2.8 7 1.8 7 2.8 7 tPHL tPLH tPHL tPLH tPHL ten tdis A B LEAB B CLKAB B OEAB B 85 Transition time, B outputs (20% to 80%) 2.6 2.6 tf Transition time, B outputs (80% to 20%) 2.6 2.6 tPHL tPLH tPHL tPLH tPHL ten tdis B A LEBA A CLKBA A OEBA A UNIT MHz tr tPLH (1) (2) FROM (INPUT) ns ns ns ns ns ns 1.4 6.3 1.5 5.7 1.3 6.2 1.5 5.7 1.5 6.1 1.8 5.7 1 6 1.8 5.7 1.8 5.8 2.3 5.5 2 5.9 2.3 5.5 0.5 6.2 1.8 6.1 1.3 6.6 1.8 6.1 ns ns ns ns Product preview All typical values are at VCC (3.3 V) = 3.3 V, VCC (5 V) = 5 V, TA = 25°C. 7 SN54GTL16612A, SN74GTL16612A 18-BIT LVTTL-TO-GTL+ UNIVERSAL BUS TRANSCEIVERS www.ti.com SCES187D – JANUARY 1999 – REVISED JULY 2005 PARAMETER MEASUREMENT INFORMATION VTT 6V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) 500 Ω TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 25 Ω S1 Open 6V GND From Output Under Test CL = 30 pF (see Note A) LOAD CIRCUIT FOR A OUTPUTS LOAD CIRCUIT FOR B OUTPUTS tw 3V 3V Timing Input 1.5 V 0V 1.5 V 1.5 V Input tsu 0V VOLTAGE WAVEFORMS PULSE DURATION 3V Input Test Point 1.5 V 1.5 V th 3V Data Input A Port 1.5 V Data Input B Port VREF 1.5 V 0V VTT VREF 0V 0V tPLH VOLTAGE WAVEFORMS SETUP AND HOLD TIMES tPHL VTT Output VREF VREF 3V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (A port to B port) tPZL VREF VREF 0V tPLH Output Waveform 1 S1 at 6 V (see Note B) 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (B port to A port) 1.5 V tPLZ 3V 1.5 V tPZH tPHL VOH Output 1.5 V 0V VTT Input Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ VOH 1.5 V VOH − 0.3 V ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES (A port) NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. Figure 2. Load Circuits and Voltage Waveforms 8 SN54GTL16612A, SN74GTL16612A 18-BIT LVTTL-TO-GTL+ UNIVERSAL BUS TRANSCEIVERS www.ti.com SCES187D – JANUARY 1999 – REVISED JULY 2005 APPLICATION INFORMATION GTL Background Information GTL was approved as JEDEC standard JESD 8-3 in 1993 and originally was created as a reduced-swing I/O driver technology to support high-speed buses and backplanes. The GTL bus is designed to work with low voltage swings. The input buffer works like an analog comparator rather than like an inverter, which allows the GTL inputs to switch quickly without needing to be driven rail to rail. GTL drivers were designed to pull a 1.2-V signal down to 0.4 V when switched on. This, however, placed the reference voltage for the input comparator at 0.8 V, which made it susceptible to ground-bounce noise. A variant of GTL, called GTL+, is being used to address this noise-margin concern. The GTL+ termination voltage is raised to 1.5 V, with the driver pulling down to a VOL of 0.5 V. This moved the reference voltage to 1 V and out of the range of most ground bounces. TI GTL devices operate at, and are specified for, both GTL and the improved-noise-margin GTL+ standard. However, the 'GTL16612A devices deviate from this history. They are designed with slow rising and falling edges, to offer significant system frequency improvement in heavily loaded backplanes. They are AC specified only at GTL+ because most applications are moving to this improved-noise-margin standard; they operate at either GTL or GTL+. Devices named GTL or GTLP indicate reduced voltage-swing operation at a VTT of 1.2 V (GTL standard) or 1.5 V (improved-noise-margin GTL+ standard). Fast-edge GTL devices are best for point-to-point or lower-frequency backplanes. Slow-edge GTL devices extend backplane operations to cover even higher frequencies. Input Characteristics The input characteristics are identical on both A and B ports. Both ports are very high impedance and have an input diode to provide protection against high negative-voltage spikes. The input diode conducts and prevents more sensitive components from being destroyed as the result of electrostatic discharges or line reflections. GTL Output Characteristics The principle of the GTL bus is based on open-drain drivers, as shown in Figure 3. Output To Other Inputs VTT RTT VTT Input RTT GTL Bus Figure 3. GTL Bus: An Open-Drain Bus The devices actively drive the bus low, whereas, the termination voltage source (VTT) pulls it high. Only the pullup resistor (RTT), which usually is of a low resistance, limits the current. The pullup resistor value should match the fully loaded backplane impedance, not the trace impedance, to provide an optimum termination of the bus and avoid line reflections. The resistance of the GTL output is in the range of a few ohms. However, in the high state, the output transistor is in the high-impedance state. RTT needs to be greater than 25 Ω at GTL+ signal levels, not to exceed the 'GTL16612A absolute maximum output current of 80 mA, and should be greater than 50 Ω at GTL+ signal levels, not to exceed the recommended output current limit of 34 mA. 9 SN54GTL16612A, SN74GTL16612A 18-BIT LVTTL-TO-GTL+ UNIVERSAL BUS TRANSCEIVERS www.ti.com SCES187D – JANUARY 1999 – REVISED JULY 2005 APPLICATION INFORMATION OEC The 'GTL16612A GTL output consists of an improved edge-control circuit that provides optimized rise and fall times, typically 2.6 ns (20% to 80%), for backplanes under various loading conditions. Using the definition of slew rate ∆t/∆v = tr or tf/(VOH – VOL), the slew rate of the device typically is 5 ns/V. As a comparison, these values are significantly more than those of previous GTL or standard TTL devices, which are usually about 1 ns/V, or less. Termination Voltage, VTT The termination voltage (VTT) should be derived from a voltage regulator that can provide up to 50-mA current per signal line. There are various voltage regulators that meet these requirements. Depending on the application, the regulators should be mounted either directly on the backplane or on the daughter boards. It is highly recommended that ceramic bypass capacitors be used (due to high impedance) at the termination resistors because several signal lines may be switching simultaneously, causing considerable current fluctuations at the termination voltage. Reference Voltage, VREF The GTL reference voltage (VREF) can be derived using a simple voltage divider between VTT and GND with an R-to-2R ratio and a bypass capacitor (0.01–0.1 µF) as close to the VREF terminal as possible (see Figure 4). Generating VREF from VTT ensures the maximum possible signal-to-noise ratio (SNR) even with an unstable termination voltage. It also is recommended to generate VREF locally on each plug-in card, instead of on the backplane. VTT R VREF 2R C Figure 4. Suggested Connection of VREF Terminal Partial Power Down Device power can be switched off without having to remove the device from the system. This is a partial power down. 'GTL16612A can be used in a partial-power-down application where VCC = 0 because the inputs and outputs are at high impedance and are able to tolerate active bus signals. This is reflected in the Ioff parameter, which specifies the maximum input or output leakage current. Bus-Hold Circuit Bus hold on A-port inputs (LVTTL side) prevents any unused or floating inputs from damaging the device. To change the logic state stored by the bus-hold circuit, a current of about 250-300 µA must be overridden. There is no bus hold on the B port (GTL side). A bus-hold circuit on the GTL side would defeat the purpose of the open-drain outputs, which take on the high-impedance state to allow the bus to achieve a logic high state via the pullup resistors. 10 SN54GTL16612A, SN74GTL16612A 18-BIT LVTTL-TO-GTL+ UNIVERSAL BUS TRANSCEIVERS www.ti.com SCES187D – JANUARY 1999 – REVISED JULY 2005 APPLICATION INFORMATION Source-Synchronous Clock Applications When the clock originates at the driver card and is carried out with the data, the backplane maximum frequency can be achieved. This is possible because the backplane flight time no longer is the limiting factor. Figure 5 shows results of the 'GTL16612A operating at 100 MHz in a source-synchronous mode. 1.6 Driver (slot 1) CLK = 100 MHz 1.4 Receiver (slot 12) Volts − V 1.2 1.0 0.8 0.6 0.4 Receiver (slot 2) 0.2 15 20 25 30 t − Time − ns Figure 5. Source-Synchronous Clock Summary 'GTL16612A devices provide significant benefits when designing high-speed parallel backplanes. • B port specifically optimized for distributed backplane levels • Improved B-port GTL edge-control circuitry provides better signal integrity at higher frequencies. • Reduced power consumption over BTL technology • Similar to 'LVTH16601, with the B port operating at GTL+ signal levels • Data throughput is 1.35 Gbit/s at 75-MHz clock speed. • Provide about two times the data throughput over existing TTL devices, using existing parallel backplane designs Additional information on http://www.ti.com/sc/gtl. GTL devices and backplane design considerations can be found at 11 PACKAGE OPTION ADDENDUM www.ti.com 24-Jun-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74GTL16612ADGGR OBSOLETE TSSOP DGG 56 TBD Call TI Call TI SN74GTL16612ADL OBSOLETE SSOP DL 56 TBD Call TI Call TI SN74GTL16612ADLR OBSOLETE SSOP DL 56 TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / E 12/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO-118 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. 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