Fractional-N Frequency Synthesizer ADF4153 Data Sheet FEATURES GENERAL DESCRIPTION RF bandwidth to 4 GHz 2.7 V to 3.3 V power supply Separate VP allows extended tuning voltage Y version available: −40°C to +125°C Programmable fractional modulus Programmable charge pump currents 3-wire serial interface Analog and digital lock detect Power-down mode Pin-compatible with ADF4110/ADF4111/ADF4112/ADF4113 and ADF4106 Consistent RF output phase Loop filter design possible with ADIsimPLL Qualified for automotive applications The ADF4153 is a fractional-N frequency synthesizer that implements local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a Σ-Δ based fractional interpolator to allow programmable fractional-N division. The INT, FRAC, and MOD registers define an overall N divider (N = (INT + (FRAC/MOD))). In addition, the 4-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete phaselocked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a voltage controlled oscillator (VCO). APPLICATIONS A simple 3-wire interface controls all on-chip registers. The device operates with a power supply ranging from 2.7 V to 3.3 V and can be powered down when not in use. CATV equipment Base stations for mobile radio (GSM, PCS, DCS, WiMAX, SuperCell 3G, CDMA, W-CDMA) Wireless handsets (GSM, PCS, DCS, CDMA, W-CDMA) Wireless LANs, PMR Communications test equipment FUNCTIONAL BLOCK DIAGRAM AVDD DVDD VP SDVDD RSET ADF4153 REFERENCE 4-BIT R COUNTER ×2 DOUBLER REFIN + PHASE FREQUENCY DETECTOR – VDD HIGH-Z CHARGE PUMP DGND LOCK DETECT MUXOUT CP OUTPUT MUX CURRENT SETTING VDD RDIV RFCP3 RFCP2 RFCP1 NDIV N-COUNTER RFINA RFINB THIRD ORDER FRACTIONAL INTERPOLATOR CLK DATA MODULUS REG INTEGER REG 03685-001 LE FRACTION REG 24-BIT DATA REGISTER AGND DGND CPGND Figure 1. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. 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Technical Support www.analog.com ADF4153 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 R Divider Register, R1................................................................ 16 Applications ....................................................................................... 1 Control Register, R2 ................................................................... 16 General Description ......................................................................... 1 Noise and Spur Register, R3 ...................................................... 17 Functional Block Diagram .............................................................. 1 Reserved Bits ............................................................................... 17 Revision History ............................................................................... 3 Initialization Sequence .............................................................. 18 Specifications..................................................................................... 4 RF Synthesizer: A Worked Example ........................................ 18 Timing Specifications .................................................................. 5 Modulus ....................................................................................... 18 Absolute Maximum Ratings ............................................................ 6 Reference Doubler and Reference Divider ............................. 18 ESD Caution .................................................................................. 6 12-Bit Programmable Modulus ................................................ 18 Pin Configurations and Function Descriptions ........................... 7 Fastlock with Spurious Optimization ...................................... 19 Typical Performance Characteristics ............................................. 8 Spur Mechanisms ....................................................................... 19 Circuit Description ........................................................................... 9 Spur Consistency ........................................................................ 20 Reference Input Section ............................................................... 9 Phase Resync ............................................................................... 20 RF Input Stage ............................................................................... 9 Filter Design—ADIsimPLL....................................................... 20 RF INT Divider ............................................................................. 9 Interfacing ................................................................................... 20 INT, FRAC, MOD, and R Relationship ..................................... 9 PCB Design Guidelines for Chip Scale Package .................... 21 RF R Counter ................................................................................ 9 Applications Information .............................................................. 22 Phase Frequency Detector (PFD) and Charge Pump ............ 10 Local Oscillator for a GSM Base Station Transmitter ........... 22 MUXOUT and Lock Detect ...................................................... 10 Outline Dimensions ....................................................................... 23 Input Shift Registers ................................................................... 10 Ordering Guide .......................................................................... 24 Program Modes .......................................................................... 10 Automotive Products ................................................................. 24 N Divider Register, R0 ............................................................... 16 Rev. F | Page 2 of 24 Data Sheet ADF4153 REVISION HISTORY 11/13—Rev. E to Rev. F Change to ICP Sink/Source Parameter, Table 1 .............................. 4 Changes to Ordering Guide ...........................................................24 7/12—Rev. D to Rev. E Updated Outline Dimensions ........................................................23 Changes to Ordering Guide ...........................................................24 8/10—Rev. C to Rev. D Changes to Features Section ............................................................ 1 Changes to Noise Characteristics Parameter, Table 1 .................. 5 Changes to Figure 4........................................................................... 7 Changes to Ordering Guide ...........................................................24 Added Automotive Products Section ...........................................24 10/08—Rev. B to Rev. C Added Y Version (Throughout) ...................................................... 1 Changes to Ordering Guide ...........................................................23 08/05—Rev. A to Rev. B Changes to Features .......................................................................... 1 Changes to Applications ................................................................... 1 Changes to Specifications ................................................................. 3 Changes to Absolute Maximum Ratings ........................................ 5 Changes to Figure 7 to Figure 9....................................................... 7 Deleted Figure 8 to Figure 10; Renumbered Sequentially ........... 8 Deleted Figure 11 and Figure 14; Renumbered Sequentially ...... 9 Changes to Table 9 ..........................................................................13 Added Initialization Sequence Section ........................................ 17 Changes to Fastlock with Spurious Optimization Section ........ 18 Inserted Figure 16; Renumbered Sequentially ............................ 18 Added Spur Mechanisms Section ................................................. 18 Added Table 11; Renumbered Sequentially ................................. 18 Added Spur Consistency Section .................................................. 19 Changes to Phase Resync Section ................................................. 19 Inserted Figure 17; Renumbered Sequentially ............................ 19 Deleted Spurious Signals— Predicting Where They Will Appear Section .............................. 20 Changes to Figure 19 ...................................................................... 20 Changes to Figure 20 ...................................................................... 21 Added Applications Section .......................................................... 21 Changes to Figure 22 Caption ....................................................... 22 Changes to Ordering Guide ........................................................... 22 1/04—Rev. 0 to Rev. A Renumbered Figures and Tables ...................................... Universal Changes to Specifications................................................................. 3 Changes to Pin Function Description ............................................ 7 Changes to RF Power-Down Section ........................................... 17 Changes to PCB Design Guidelines for Chip Scale Package Section ............................................................................... 21 Updated Outline Dimensions........................................................ 22 Updated Ordering Guide ............................................................... 22 7/03—Revision 0: Initial Version Rev. F | Page 3 of 24 ADF4153 Data Sheet SPECIFICATIONS AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 Ω. Table 1. Parameter RF CHARACTERISTICS (3 V) RF Input Frequency (RFIN) REFERENCE CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency 4 CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy RSET Range ICP Three-State Leakage Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD, SDVDD VP IDD Low Power Sleep Mode B Version 1 Y Version 2 Unit 0.5/4.0 0.5/4.0 0.5/4.0 0.5/4.0 GHz min/max GHz min/max 1.0/4.0 1.0/4.0 GHz min/max 10/250 10/250 MHz min/max 0.7/AVDD 10 ±100 0.7/AVDD 10 ±100 V p-p min/max pF max µA max 32 32 MHz max 5 312.5 2.5 1.5/10 1 2 2 2 5 312.5 2.5 1.5/10 4.5 2 2 2 mA typ µA typ % typ kΩ min/max nA typ % typ % typ % typ 1.4 0.6 ±1 10 1.4 0.6 ±1 10 V min V max µA max pF max 1.4 0.4 1.4 0.4 V min V max 2.7/3.3 AVDD AVDD/5.5 24 1 2.7/3.3 AVDD AVDD/5.5 24 1 V min/V max V min/V max mA max µA typ Rev. F | Page 4 of 24 Test Conditions/Comments See Figure 12 for input circuit B Version: −8 dBm minimum/0 dBm maximum Y Version: −6.5 dBm minimum/0 dBm maximum For lower frequencies, ensure slew rate (SR) > 400 V/µs −10 dBm/0 dBm minimum/maximum See Figure 11 for input circuit For f < 10 MHz, use a dc-coupled, CMOS-compatible square wave; slew rate > 25 V/µs Biased at AVDD/2 3 Programmable; see Table 9 With RSET = 5.1 kΩ With RSET = 5.1 kΩ Sink and source current 0.5 V < VCP < VP – 0.5 0.5 V < VCP < VP – 0.5 VCP = VP/2 Open-drain 1 kΩ pull-up to 1.8 V IOL = 500 µA 20 mA typical Data Sheet ADF4153 Parameter NOISE CHARACTERISTICS Normalized Phase Noise Floor (PNSYNTH) 5 Normalized 1/f Noise (PN1_f) 6 Phase Noise Performance 7 1750 MHz Output 8 B Version 1 Y Version 2 Unit Test Conditions/Comments −220 −220 dBc/Hz typ PLL loop BW = 500 kHz −114 −114 dBc/Hz typ −102 −102 dBc/Hz typ Measured at 10 kHz offset, normalized to 1 GHz @ VCO output @ 5 kHz offset, 25 MHz PFD frequency Operating temperature for B version is −40°C to +85°C. Operating temperature for Y version is −40°C to +125°C. 3 AC coupling ensures AVDD/2 bias. 4 Guaranteed by design. Sample tested to ensure compliance. 5 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider value) and 10 log(FPFD). PNSYNTH = PNTOT − 10 log(FPFD) − 20 log(N). 6 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, FRF, and at an offset frequency, f, is given by PN = P1_f + 10 log(10 kHz/f) + 20 log(FRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL. 7 The phase noise is measured with the EV-ADF4153SD1Z and the Agilent E5500 phase noise system. 8 fREFIN = 100 MHz; FPFD = 25 MHz; offset frequency = 5 kHz; RFOUT = 1750 MHz; N = 70; loop BW = 20 kHz; lowest noise mode. 1 2 TIMING SPECIFICATIONS AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 Ω. Table 2. Parameter t1 t2 t3 t4 t5 t6 t7 Limit at TMIN to TMAX (B Version) 20 10 10 25 25 10 20 Unit ns min ns min ns min ns min ns min ns min ns min t4 Test Conditions/Comments LE setup time DATA to CLK setup time DATA to CLK hold time CLK high duration CLK low duration CLK to LE setup time LE pulse width t5 CLK t3 t2 DATA DB23 (MSB) DB22 DB2 DB0 (LSB) (CONTROL BIT C1) DB1 (CONTROL BIT C2) t7 LE t1 03685-026 t6 LE Figure 2. Timing Diagram Rev. F | Page 5 of 24 ADF4153 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, GND = AGND = DGND = 0 V, VDD = AVDD = DVDD = SDVDD, unless otherwise noted. Table 3. Parameter VDD to GND VDD to VDD VP to GND VP to VDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN, RFIN to GND Operating Temperature Range Industrial (B Version) Extended (Y Version) Storage Temperature Range Maximum Junction Temperature TSSOP θJA Thermal Impedance LFCSP θJA Thermal Impedance (Paddle Soldered) Reflow Soldering Peak Temperature Time at Peak Temperature Maximum Junction Temperature Rating −0.3 V to +4 V −0.3 V to +0.3 V −0.3 V to +5.8 V −0.3 V to +5.8 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −40°C to +85°C −40°C to +125°C −65°C to +125°C 150°C 112°C/W 30.4°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of <2 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly. ESD CAUTION 260°C 40 sec 150°C Rev. F | Page 6 of 24 Data Sheet ADF4153 20 19 18 17 16 CP RSET VP DVDD DVDD PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 16 VP 2 15 DVDD 3 14 MUXOUT AGND 4 ADF4153 13 LE RFINB 5 TOP VIEW (Not to Scale) 12 DATA RFINA 6 11 CLK AVDD 7 10 SDVDD REFIN 8 9 DGND PIN 1 INDICATOR ADF4153 TOP VIEW (Not to Scale) 15 MUXOUT 14 LE 13 DATA 12 CLK 11 SDVDD 03685-002 AVDD AVDD REFIN DGND DGND 6 7 8 9 10 CP CPGND 1 2 3 4 5 NOTES 1. THE LFCSP HAS AN EXPOSED PADDLE THAT MUST BE CONNECTED TO GND. Figure 3. TSSOP Pin Configuration 03685-003 RSET CPGND AGND AGND RFINB RFINA Figure 4. LFCSP Pin Configuration Table 4. Pin Function Descriptions Pin No. TSSOP 1 Pin No. LFCSP 19 Mnemonic RSET Description Connecting a resistor between RSET and ground sets the maximum charge pump output current. The relationship between ICP and RSET is I CPMAX = 2 20 CP 3 4 5 1 2, 3 4 CPGND AGND RFINB 6 7 5 6, 7 RFINA AVDD 8 8 REFIN 9 10 9, 10 11 DGND SDVDD 11 12 CLK 12 13 DATA 13 14 LE 14 15 MUXOUT 15 16, 17 DVDD 16 18 VP 21 EP 25.5 R SET where RSET = 5.1 kΩ and ICPMAX = 5 mA. Charge Pump Output. When enabled, CP provides ±ICP to the external loop filter, which in turn drives the external VCO. Charge Pump Ground. This is the ground return path for the charge pump. Analog Ground. This is the ground return path of the prescaler. Complementary Input to the RF Prescaler. This pin should be decoupled to the ground plane with a small bypass capacitor, typically 100 pF (see Figure 12). Input to the RF Prescaler. This small signal input is normally ac-coupled from the VCO. Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. AVDD has a value of 3 V ± 10%. AVDD must have the same voltage as DVDD. Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of 100 kΩ (see Figure 11). This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled. Digital Ground. Σ-Δ Power. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. SDVDD has a value of 3 V ± 10%. SDVDD must have the same voltage as DVDD. Serial Clock Input. The serial clock is used to clock in the serial data to the registers. The data is latched into the shift register on the CLK rising edge. This input is a high impedance CMOS input. Serial Data Input. The serial data is loaded MSB first; the two LSBs are the control bits. This input is a high impedance CMOS input. Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one of four latches; the latch is selected using the control bits. This multiplexer output allows either the RF lock detect, the scaled RF, or the scaled reference frequency to be externally accessed. Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. DVDD has a value of 3 V ± 10%. DVDD must have the same voltage as AVDD. Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, it can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V. Exposed Pad. The exposed paddle must be connected to GND. Rev. F | Page 7 of 24 ADF4153 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS Loop bandwidth = 20 kHz, reference = 250 MHz, VCO = Sirenza 1750T VCO, evaluation board = EV-ADF4153SD1Z, measurements taken on the Agilent E5500 phase noise system. 5 –30 –40 –50 0 –5 –70 AMPLITUDE (dBm) PHASE NOISE (dBc/Hz) –60 20kHz LOOP BW, LOWEST NOISE MODE RF = 1.7202MHz, PFD = 25MHz, N = 68, FRAC = 101, MOD = 125, ICP = 625µA, DSB INTEGRATED PHASE ERROR = 0.23° RMS SIRENZA 1750T VCO –80 –90 –100 –110 –120 –130 –10 P = 4/5 –15 –20 –25 –140 –30 –160 –170 1k 10k 100k 1M FREQUENCY (Hz) 10M –35 P = 8/9 0 0.5 1.0 100M –70 3.5 4.0 4.5 6 20kHz LOOP BW, LOW NOISE AND SPUR MODE RF = 1.7202MHz, PFD = 25MHz, N = 68, FRAC = 101, MOD = 125, ICP = 625µA, DSB INTEGRATED PHASE ERROR = 0.33° RMS SIRENZA 1750T VCO 5 4 3 –80 2 –90 1 ICP (mA) PHASE NOISE (dBc/Hz) –60 3.0 Figure 8. RF Input Sensitivity –30 –50 2.5 FREQUENCY (GHz) Figure 5. Single-Sideband Phase Noise Plot (Lowest Noise Mode) –40 2.0 1.5 03685-011 03685-004 –150 –100 –110 –120 0 –1 –2 –130 –3 –140 03685-005 –160 –170 1k 10k 100k 1M FREQUENCY (Hz) 10M 03685-012 –4 –150 –5 –6 100M 0 4 5 –90 20kHz LOOP BW, LOW SPUR MODE RF = 1.7202MHz, PFD = 25MHz, N = 68, FRAC = 101, MOD = 125, ICP = 625µA, DSB INTEGRATED PHASE ERROR = 0.36° RMS SIRENZA 1750T VCO PHASE NOISE (dBc/Hz) –92 –70 –80 –90 –100 –110 –120 –130 –94 –96 –98 –100 –140 –160 –170 1k –102 10k 100k 1M FREQUENCY (Hz) 10M –104 –60 100M Figure 7. Single-Sideband Phase Noise Plot (Low Spur Mode) 03685-014 –150 03685-006 PHASE NOISE (dBc/Hz) –60 3 Figure 9. Charge Pump Output Characteristics –30 –50 2 VCP (V) Figure 6. Single-Sideband Phase Noise Plot (Low Noise and Spur Mode) –40 1 –40 –20 0 20 40 TEMPERATURE (°C) 60 Figure 10. Phase Noise vs. Temperature Rev. F | Page 8 of 24 80 100 Data Sheet ADF4153 CIRCUIT DESCRIPTION REFERENCE INPUT SECTION RF INT DIVIDER The reference input stage is shown in Figure 11. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. The RF INT CMOS counter allows a division ratio in the PLL feedback counter. Division ratios from 31 to 511 are allowed. POWER-DOWN CONTROL 100kΩ NC SW2 INT, FRAC, MOD, AND R RELATIONSHIP The INT, FRAC, and MOD values, in conjunction with the R counter, make it possible to generate output frequencies that are spaced by fractions of the phase frequency detector (PFD). See the RF Synthesizer: A Worked Example section for more information. The RF VCO frequency (RFOUT) equation is TO R COUNTER REFIN NC RFOUT = FPFD × (INT + (FRAC/MOD)) BUFFER 03685-027 SW1 SW3 NO Figure 11. Reference Input Stage RF INPUT STAGE The RF input stage is shown in Figure 12. It is followed by a 2-stage limiting amplifier to generate the current-mode logic (CML) clock levels needed for the prescaler. where: RFOUT is the output frequency of the external voltage controlled oscillator (VCO). INT is the preset divide ratio of the binary 9-bit counter (31 to 511). MOD is the preset fractional modulus (2 to 4095). FRAC is the numerator of the fractional division (0 to MOD − 1). The PFD frequency is given by: FPFD = REFIN × (1 + D)/R 1.6V BIAS GENERATOR (2) where: REFIN is the reference input frequency. D is the REFIN doubler bit. R is the preset divide ratio of the binary 4-bit programmable reference counter (1 to 15). AVDD 2kΩ (1) 2kΩ RFINA RF R COUNTER The 4-bit RF R counter allows the input reference frequency (REFIN) to be divided down to produce the reference clock to the PFD. Division ratios from 1 to 15 are allowed. AGND 03685-015 RFINB RF N DIVIDER FROM RF INPUT STAGE Figure 12. RF Input Stage N = INT + FRAC/MOD TO PFD N-COUNTER THIRD-ORDER FRACTIONAL INTERPOLATOR MOD REG FRAC VALUE 03685-016 INT REG Figure 13. RF N Divider Rev. F | Page 9 of 24 ADF4153 Data Sheet PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP INPUT SHIFT REGISTERS The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. Figure 14 is a simplified schematic of the phase frequency detector. The PFD includes a fixed delay element that sets the width of the antibacklash pulse, which is typically 3 ns. This pulse ensures that there is no dead zone in the PFD transfer function and gives a consistent reference spur level. HI D1 Q1 UP U1 +IN PROGRAM MODES CLR1 DELAY HI The ADF4153 digital section includes a 4-bit RF R counter, a 9-bit RF N counter, a 12-bit FRAC counter, and a 12-bit modulus counter. Data is clocked into the 24-bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of four latches on the rising edge of LE. The destination latch is determined by the state of the two control bits (C2 and C1) in the shift register. These are the 2 LSBs, DB1 and DB0, as shown in Figure 2. The truth table for these bits is shown in Table 5. Table 6 shows a summary of how the registers are programmed. CHARGE PUMP U3 Table 5 through Table 10 show how to set up the program modes in the ADF4153. CP The ADF4153 programmable modulus is double buffered. This means that two events have to occur before the part uses a new modulus value. First, the new modulus value is latched into the device by writing to the R divider register. Second, a new write must be performed on the N divider register. Therefore, to ensure that the modulus value is loaded correctly, the N divider register must be written to any time that the modulus value is updated. CLR2 DOWN D2 Q2 03685-017 U2 –IN Figure 14. PFD Simplified Schematic MUXOUT AND LOCK DETECT The output multiplexer on the ADF4153 allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2, and M1 (see Table 8). Figure 15 shows the MUXOUT section in block diagram form. DVDD THREE-STATE OUTPUT LOGIC LOW Table 5. C2 and C1 Truth Table C2 0 0 1 1 DIGITAL LOCK DETECT R COUNTER DIVIDER MUX MUXOUT CONTROL N COUNTER DIVIDER ANALOG LOCK DETECT DGND 03685-018 LOGIC HIGH s Figure 15. MUXOUT Schematic Rev. F | Page 10 of 24 Control Bits C1 0 1 0 1 Register N Divider Register R Divider Register Control Register Noise and Spur Register Data Sheet ADF4153 Table 6. Register Summary FASTLOCK N DIVIDER REG (R0) 9-BIT INTEGER VALUE (INT) DB23 DB22 FL1 N9 DB21 DB20 N8 N7 DB19 DB18 N6 N5 DB17 N4 CONTROL BITS 12-BIT FRACTIONAL VALUE (FRAC) DB16 DB15 DB14 N3 N2 N1 DB13 DB12 DB11 DB10 DB9 DB8 F12 F11 F10 F9 F8 F7 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 F6 F5 F4 F3 F2 F1 C2 (0) C1 (0) DB16 DB15 R3 R2 DB14 DB13 DB12 R1 M12 M11 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 M10 M8 M7 M6 M5 M4 M3 M2 M1 M9 DB1 DB0 C2 (0) C1 (1) CONTROL REG (R2) RESYNC CONTROL BITS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 S4 S3 S2 S1 CP3 CP2 CP1 CP0 U5 U4 U3 U2 U1 U6 CP CURRENT SETTING DB0 C2 (1) C1 (0) NOISE AND SPUR REG (R3) NOISE AND SPUR MODE RESERVED DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 0 T8 T7 T6 T5 0 0 0 T1 Rev. F | Page 11 of 24 CONTROL BITS DB1 C2 (1) DB0 C1 (1) 03685-019 R4 COUNTER RESET DB17 P1 NOISE AND SPUR MODE DB18 0 CP THREE-STATE DB19 POWERDOWN M1 LDP M2 PD POLARITY DB21 DB20 CP/2 M3 CONTROL BITS 12-BIT INTERPOLATOR MODULUS VALUE (MOD) RESERVED DB22 P3 4-BIT R COUNTER REFERENCE DOUBLER DB23 PRESCALER MUXOUT RESERVED LOAD CONTROL R DIVIDER REG (R1) ADF4153 Data Sheet FASTLOCK Table 7. N Divider Register Map (R0) 9-BIT INTEGER VALUE (INT) DB23 DB22 FL1 N9 N8 N7 DB19 DB18 N6 DB17 N5 N4 DB16 DB15 N3 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 N1 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 C2 (0) C1 (0) N2 F12 F11 F10 F3 F2 F1 FRACTIONAL VALUE (FRAC) 0 0 0 0 . . . 1 0 0 0 0 . . . 1 0 0 0 0 . . . 1 .......... .......... .......... .......... .......... .......... .......... .......... 0 0 0 0 . . . 1 0 0 1 1 . . . 0 0 1 0 1 . . . 0 0 1 2 3 . . . 4092 1 1 1 .......... 1 0 1 4093 1 1 1 .......... 1 1 0 4094 1 1 1 .......... 1 1 1 4095 N9 N8 N7 N6 N5 N4 N3 N2 N1 INTEGER VALUE (INT) 0 0 0 0 . . . 1 0 0 0 0 . . . 1 0 0 0 0 . . . 1 0 1 1 1 . . . 1 1 0 0 0 . . . 1 1 0 0 0 . . ... 1 1 0 0 0 . . . 1 1 0 0 1 . . . 0 1 0 1 0 . . . 1 31 32 33 34 . . . 509 1 1 1 1 1 1 1 1 0 510 1 1 1 1 1 1 1 1 1 511 FASTLOCK NORMAL OPERATION FASTLOCK ENABLED 03685-020 FL1 0 1 DB21 DB20 CONTROL BITS 12-BIT FRACTIONAL VALUE (FRAC) Rev. F | Page 12 of 24 Data Sheet ADF4153 DB23 DB22 DB21 DB20 P3 P3 0 1 M3 M2 LOAD CONTROL NORMAL OPERATION LOAD RESYNC DB19 DB18 0 M1 P1 0 1 P1 4-BIT R COUNTER DB17 DB16 DB15 DB14 R4 R2 R3 R1 PRESCALER 4/5 8/9 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 M12 M11 M10 M8 M7 M6 M5 M4 M3 M2 M1 M9 M10 0 0 0 . . . 1 .......... .......... .......... .......... .......... .......... .......... M3 0 0 1 . . . 1 M2 1 1 0 . . . 0 M1 0 1 0 . . . 0 INTERPOLATOR MODULUS VALUE (MOD) 2 3 4 . . . 4092 1 1 1 .......... 1 0 1 4093 1 1 1 .......... 1 1 0 4094 1 1 1 .......... 1 1 1 4095 R2 R1 RF R COUNTER DIVIDE RATIO 0 0 0 0 . . . 1 0 0 0 1 . . . 1 0 1 1 0 . . . 0 1 0 1 0 . . . 0 1 2 3 4 . . . 12 1 1 0 1 13 1 1 1 0 14 1 1 1 1 15 M2 M1 MUXOUT 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 THREE-STATE OUTPUT DIGITAL LOCK DETECT N DIVIDER OUTPUT LOGIC HIGH R DIVIDER OUTPUT ANALOG LOCK DETECT FASTLOCK SWITCH LOGIC LOW DB0 M11 0 0 0 . . . 1 R3 0 0 0 0 1 1 1 1 DB1 C2 (0) C1 (1) M12 0 0 0 . . . 1 R4 M3 CONTROL BITS 12-BIT INTERPOLATOR MODULUS VALUE (MOD) 03685-021 MUXOUT PRESCALER RESERVED LOAD CONTROL Table 8. R Divider Register Map (R1) Rev. F | Page 13 of 24 ADF4153 Data Sheet REFERENCE DOUBLER CP/2 PD POLARITY LDP POWERDOWN CP THREE-STATE COUNTER RESET Table 9. Control Register Map (R2) CONTROL BITS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 S4 S3 S2 S1 U6 CP3 CP2 CP1 CP0 U5 U4 U3 U2 U1 C2 (1) C1 (0) RESYNC CP CURRENT SETTING REFERENCE DOUBLER DISABLED ENABLED U6 0 1 S4 S3 S2 S1 RESYNC 0 0 0 . . . 1 1 1 0 0 0 . . . 1 1 1 0 1 1 . . . 0 1 1 1 0 1 . . . 1 0 1 1 2 3 . . . 13 14 15 U2 0 1 U1 COUNTER RESET 0 1 DISABLED ENABLED CP THREE-STATE DISABLED THREE-STATE U3 POWER-DOWN 0 1 NORMAL OPERATION POWER-DOWN ICP (mA) CP2 0 0 0 0 1 1 1 1 CP1 0 0 1 1 0 0 1 1 CP0 0 1 0 1 0 1 0 1 2.7kΩ 1.18 2.46 3.54 4.72 5.9 7.08 8.26 9.45 5.1kΩ 0.63 1.25 1.88 2.50 3.13 3.75 4.38 5.00 10kΩ 0.32 0.64 0.96 1.28 1.59 1.92 2.23 2.55 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0.59 1.23 1.77 2.36 2.95 3.54 4.13 4.73 0.31 0.63 0.94 1.25 1.57 1.88 2.19 2.50 0.16 0.32 0.48 0.64 0.8 0.96 1.12 1.28 Rev. F | Page 14 of 24 U4 0 1 U5 0 1 LDP 24 PFD CYCLES 40 PFD CYCLES PD POLARITY NEGATIVE POSITIVE 03685-022 CP3 0 0 0 0 0 0 0 0 Data Sheet ADF4153 NOISE AND SPUR MODE NOISE AND SPUR MODE RESERVED Table 10. Noise and Spur Register (R3) RESERVED CONTROL BITS DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 T8 T7 T6 T5 0 0 0 T1 C2 (1) C1 (1) DB10, DB5, DB4, DB3 RESERVED 0 RESERVED DB9, DB8, DB7, DB6, DB2 NOISE AND SPUR SETTING 00000 11100 11111 LOW SPUR MODE LOW NOISE AND SPUR MODE LOWEST NOISE MODE Rev. F | Page 15 of 24 03685-023 THESE BITS MUST BE SET TO 0 FOR NORMAL OPERATION. ADF4153 Data Sheet N DIVIDER REGISTER, R0 Prescaler (P/P + 1) With R0[1, 0] set to [0, 0], the on-chip N divider register is programmed. Table 7 shows the input data format for programming this register. The dual-modulus prescaler (P/P + 1), along with the INT, FRAC, and MOD counters, determines the overall division ratio from the RFIN to the PFD input. 9-Bit INT Value Operating at CML levels, it takes the clock from the RF input stage and divides it down for the counters. It is based on a synchronous 4/5 core. When set to 4/5, the maximum RF frequency allowed is 2 GHz. Therefore, when operating the ADF4153 above 2 GHz, this must be set to 8/9. The prescaler limits the INT value. These nine bits control what is loaded as the INT value. This is used to determine the overall feedback division factor. It is used in Equation 1 (see the INT, FRAC, MOD, and R Relationship section). 12-Bit FRAC Value These 12 bits control what is loaded as the FRAC value into the fractional interpolator. This is part of what determines the overall feedback division factor. It is also used in Equation 1. The FRAC value must be less than or equal to the value loaded into the MOD register. Fastlock When set to logic high, fastlock is enabled. This sets the charge pump current to its maximum value. When set to logic low, the charge pump current is equal to the value programmed into the function register. Also, if MUXOUT is programmed to setting the fastlock switch, MUXOUT is shorted to ground when the fastlock bit is 1 and is high impedance when this bit is 0. R DIVIDER REGISTER, R1 With R1[1, 0] set to [0, 1], the on-chip R divider register is programmed. Table 8 shows the input data format for programming this register. Load Control When set to logic high, the value being programmed in the modulus is not loaded into the modulus. Instead, it sets the resync delay of the Σ-Δ. This is done to ensure phase resync when changing frequencies. See the Phase Resync section for more information and a worked example. MUXOUT The on-chip multiplexer is controlled by DB22, DB21, and DB20 on the ADF4153. See Table 8 for the truth table. With P = 4/5, NMIN = 31. With P = 8/9, NMIN = 91. 4-Bit R Counter The 4-bit R counter allows the input reference frequency (REFIN) to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 15 are allowed. 12-Bit Interpolator MOD Value These programmable bits set the fractional modulus. This is the ratio of the PFD frequency to the channel step resolution on the RF output. Refer to the RF Synthesizer: A Worked Example section for more information. The ADF4153 programmable modulus is double buffered. This means that two events have to occur before the part uses a new modulus value. First, the new modulus value is latched into the device by writing to the R divider register. Second, a new write must be performed on the N divider register. Therefore, any time that the modulus value has been updated, the N divider register must then be written to in order to ensure that the modulus value is loaded correctly. CONTROL REGISTER, R2 With R2[1, 0] set to [1, 0], the on-chip control register is programmed. Table 9 shows the input data format for programming this register. RF Counter Reset Digital Lock Detect The digital lock detect output goes high if there are 24 successive PFD cycles with an input error of less than 15 ns (for LDP is 0, see the Control Register, R2 section for a more thorough explanation of the LDP bit). It stays high until a new channel is programmed or until the error at the PFD input exceeds 30 ns for one or more cycles. If the loop bandwidth is narrow compared to the PFD frequency, the error at the PFD inputs may drop below 15 ns for 24 cycles around a cycle slip. Therefore, the digital lock detect may go falsely high for a short period until the error again exceeds 30 ns. In this case, the digital lock detect is reliable only as a loss-of-lock detector. DB2 is the RF counter reset bit for the ADF4153. When this is 1, the RF synthesizer counters are held in reset. For normal operation, this bit should be 0. RF Charge Pump Three-State DB3 puts the charge pump into three-state mode when programmed to 1. It should be set to 0 for normal operation. RF Power-Down DB4 on the ADF4153 provides the programmable power-down mode. Setting this bit to 1 performs a power-down. Setting this bit to 0 returns the synthesizer to normal operation. While in software power-down mode, the part retains all information in its registers. Only when supplies are removed are the register contents lost. Rev. F | Page 16 of 24 Data Sheet ADF4153 When a power-down is activated, the following events occur: NOISE AND SPUR REGISTER, R3 1. All active dc current paths are removed. 2. The synthesizer counters are forced to their load state conditions. With R3[1, 0] set to [1, 1], the on-chip noise and spur register is programmed. Table 10 shows the input data format for programming this register. 3. The charge pump is forced into three-state mode. Noise and Spur Mode 4. The digital lock detect circuitry is reset. 5. The RFIN input is debiased. 6. The input register remains active and capable of loading and latching data. Noise and spur mode allows the user to optimize a design either for improved spurious performance or for improved phase noise performance. When the low spur setting is chosen, dither is enabled. This randomizes the fractional quantization noise so that it resembles white noise rather than spurious noise. As a result, the part is optimized for improved spurious performance. This operation would normally be used when the PLL closed-loop bandwidth is wide, for fast-locking applications. (Wide-loop bandwidth is seen as a loop bandwidth greater than 1/10 of the RFOUT channel step resolution (fRES).) A wide-loop filter does not attenuate the spurs to the same level as a narrow-loop bandwidth. Lock Detect Precision (LDP) When DB5 is programmed to 0, 24 consecutive PFD cycles of 15 ns must occur before digital lock detect is set. When this bit is programmed to 1, 40 consecutive reference cycles of 15 ns must occur before digital lock detect is set. Phase Detector Polarity DB6 in the ADF4153 sets the phase detector polarity. When the VCO characteristics are positive, this should be set to 1. When they are negative, it should be set to 0. Charge Pump Current Setting DB7, DB8, DB9, and DB10 set the charge pump current setting. This should be set to the charge pump current that the loop filter is designed with (see Table 9). REFIN Doubler Setting DB11 to 0 feeds the REFIN signal directly to the 4-bit RF R counter, disabling the doubler. Setting this bit to 1 multiplies the REFIN frequency by a factor of 2 before feeding into the 4-bit R counter. When the doubler is disabled, the REFIN falling edge is the active edge at the PFD input to the fractional synthesizer. When the doubler is enabled, both the rising and falling edges of REFIN become active edges at the PFD input. When the doubler is enabled and the lowest spur mode is chosen, the in-band phase noise performance is sensitive to the REFIN duty cycle. The phase noise degradation can be as much as 5 dB for the REFIN duty cycles outside a 45% to 55% range. The phase noise is insensitive to the REFIN duty cycle in the lowest noise mode and in the lowest noise and spur mode. The phase noise is insensitive to REFIN duty cycle when the doubler is disabled. When the low noise and spur setting is enabled, dither is disabled. This optimizes the synthesizer to operate with improved noise performance. However, the spurious performance is degraded in this mode compared to the low spur setting. To further improve noise performance, the lowest noise setting option can be used, which reduces the phase noise. As well as disabling the dither, it also ensures that the charge pump is operating in an optimum region for noise performance. This setting is extremely useful where a narrow-loop filter bandwidth is available. The synthesizer ensures extremely low noise and the filter attenuates the spurs. The typical performance characteristics give the user an idea of the trade-off in a typical W-CDMA setup for the different noise and spur settings. RESERVED BITS These bits should be set to 0 for normal operation. The maximum allowed REFIN frequency when the doubler is enabled is 30 MHz. Rev. F | Page 17 of 24 ADF4153 Data Sheet INITIALIZATION SEQUENCE The following initialization sequence should be followed upon powering up the part: 1. Write all zeros to the noise and spur register. This ensures that all test modes are cleared. 2. Write again to the noise and spur register, this time selecting which noise and spur mode is required. For example, writing Hexadecimal 0003C7 to the part selects lowest noise mode. 3. 4. 5. 6. Enable the counter reset in the control register by writing a 1 to DB2; also select the required settings in the control register. If using the phase resync function, set the resync bits to the required settings. Load the R divider register (with load control DB23 set to 0). Load the N divider register. Disable the counter reset by writing a 0 to DB2 in the control register. The part now locks to the set frequency. If using the phase resync function, an extra step is needed after Step 3. This involves loading the R divider register with load control = 1 and the required delay interval in place of the MOD value. The previous sequence can then be followed ensuring that in Step 4 the value of MOD is written to the R divider register with load control = 0. For example, in a GSM 1800 system, where 1.8 GHz RF frequency output (RFOUT) is required, a 13 MHz reference frequency input (REFIN) is available and a 200 kHz channel resolution (fRES) is required on the RF output. MOD = REFIN/fRES MOD = 13 MHz/200 kHz = 65 From Equation 4: FPFD = [13 MHz × (1 + 0)/1] = 13 MHz (5) 1.8 G = 13 MHz × (INT + FRAC/65) where INT = 138; FRAC = 30 (6) MODULUS The choice of modulus (MOD) depends on the reference signal (REFIN) available and the channel resolution (fRES) required at the RF output. For example, a GSM system with 13 MHz REFIN sets the modulus to 65. This means that the RF output resolution (fRES) is the 200 kHz (13 MHz/65) necessary for GSM. With dither off, the fractional spur interval depends on the modulus values chosen. See Table 11 for more information. REFERENCE DOUBLER AND REFERENCE DIVIDER See the Spur Consistency and Phase Resync sections for more information on the phase resync feature. The reference doubler on-chip allows the input reference signal to be doubled. This is useful for increasing the PFD comparison frequency. Making the PFD frequency higher improves the noise performance of the system. Doubling the PFD frequency usually improves noise performance by 3 dB. It is important to note that the PFD cannot be operated above 32 MHz due to a limitation in the speed of the Σ-Δ circuit of the N divider. RF SYNTHESIZER: A WORKED EXAMPLE 12-BIT PROGRAMMABLE MODULUS The following equation governs how the synthesizer is programmed: Unlike most other fractional-N PLLs, the ADF4153 allows the user to program the modulus over a 12-bit range. This means that the user can set up the part in many different configurations for the application, when combined with the reference doubler and the 4-bit R counter. RFOUT = [INT + (FRAC/MOD)] × [FPFD] (3) where: RFOUT is the RF frequency output. INT is the integer division factor. FRAC is the fractionality. MOD is the modulus. The following is an example of an application that requires 1.75 GHz RF and 200 kHz channel step resolution. The system has a 13 MHz reference signal. The PFD frequency is given by: FPFD = [REFIN × (1 + D)/R] where: REFIN is the reference frequency input. D is the RF REFIN doubler bit. R is the RF reference division factor. (4) One possible setup is feeding the 13 MHz directly to the PFD and programming the modulus to divide by 65. This results in the required 200 kHz resolution. Another possible setup is using the reference doubler to create 26 MHz from the 13 MHz input signal. This 26 MHz is then fed into the PFD. The modulus is now programmed to divide by 130. This also results in 200 kHz resolution and offers superior phase noise performance over the previous setup. Rev. F | Page 18 of 24 Data Sheet ADF4153 The programmable modulus is also very useful for multistandard applications. If a dual-mode phone requires PDC and GSM 1800 standards, the programmable modulus is of great benefit. PDC requires 25 kHz channel step resolution, whereas GSM 1800 requires 200 kHz channel step resolution. A 13 MHz reference signal can be fed directly to the PFD. The modulus is programmed to 520 when in PDC mode (13 MHz/520 = 25 kHz). The modulus is reprogrammed to 65for GSM 1800 operation (13 MHz/65 = 200 kHz). It is important that the PFD frequency remains constant (13 MHz). This allows the user to design one loop filter that can be used in both setups without running into stability issues. It is the ratio of the RF frequency to the PFD frequency that affects the loop design. By keeping this relationship constant, the same loop filter can be used in both applications. FASTLOCK WITH SPURIOUS OPTIMIZATION As mentioned in the Noise and Spur Mode section, the part can be optimized for spurious performance. However, in fastlocking applications, the loop bandwidth needs to be wide, and therefore the filter does not provide much attenuation of the spurs. The programmable charge pump can be used to get around this issue. The filter is designed for a narrow-loop bandwidth so that steady-state spurious specifications are met. This is designed using the lowest charge pump current setting. To implement fastlock during a frequency jump, the charge pump current is set to the maximum setting for the duration of the jump by asserting the fastlock bit in the N divider register. This widens the loop bandwidth, which improves lock time. To maintain loop stability while in wide bandwidth mode, the loop filter needs to be modified. This is achieved by switching in a resistor (R1A) in parallel with the damping resistor in the loop filter (see Figure 16). MUXOUT needs to be set to the fastlock switch to use the internal switch. For example, if the charge pump current is increased by 16, the damping resistor, R1, needs to be decreased by ¼ while in wide bandwidth mode. CP VCO ADF4153 C2 C1 MUXOUT FL R1A 03685-029 R1 Figure 16. ADF4153 with Fastlock The value of R1A is then chosen so that the total parallel resistance of R1 and R1A equals 1/4 of R1 alone. This gives an overall 4× increase in loop bandwidth, while maintaining stability in wide bandwidth mode. When the PLL has locked to the new frequency, the charge pump is again programmed to the lowest charge pump current setting by setting the fastlock bit to 0. The internal switch opens and the damping resistor reverts to its original value. This narrows the loop bandwidth to its original cutoff frequency to allow better attenuation of the spurs than the wide-loop bandwidth. SPUR MECHANISMS The following section describes the three different spur mechanisms that arise with a fractional-N synthesizer and how to minimize them in the ADF4153. Fractional Spurs The fractional interpolator in the ADF4153 is a third-order Σ-Δ modulator (SDM) with a modulus (MOD) that is programmable to any integer value from 2 to 4095. In low spur mode (dither enabled), the minimum allowed value of MOD is 50. The SDM is clocked at the PFD reference rate (FPFD) that allows PLL output frequencies to be synthesized at a channel step resolution of FPFD/MOD. In lowest noise mode and low noise and spur mode (dither off), the quantization noise from the Σ-Δ modulator appears as fractional spurs. The interval between spurs is FPFD/L, where L is the repeat length of the code sequence in the digital Σ-Δ modulator. For the third-order modulator used in the ADF4153, the repeat length depends on the value of MOD, as shown in Table 11. Table 11. Fractional Spurs with Dither Off Condition (Dither Off) If MOD is divisible by 2, but not 3 If MOD is divisible by 3, but not 2 If MOD is divisible by 6 Otherwise Repeat Length 2 × MOD 3 × MOD 6 × MOD MOD Spur Interval Channel step/2 Channel step/3 Channel step/6 Channel step In low spur mode (dither enabled), the repeat length is extended to 221 cycles, regardless of the value of MOD, which makes the quantization error spectrum look like broadband noise. This can degrade the in-band phase noise at the PLL output by as much as 10 dB. Therefore, for lowest noise, dither off is a better choice, particularly when the final loop BW is low enough to attenuate even the lowest frequency fractional spur. Integer Boundary Spurs Another mechanism for fractional spur creation is interactions between the RF VCO frequency and the reference frequency. When these frequencies are not integer related (which is the point of a fractional-N synthesizer), spur sidebands appear on the VCO output spectrum at an offset frequency that corresponds to the beat note or difference frequency between an integer multiple of the reference and the VCO frequency. These spurs are attenuated by the loop filter and are more noticeable on channels close to integer multiples of the reference where the difference frequency can be inside the loop bandwidth, therefore, the name integer boundary spurs. Rev. F | Page 19 of 24 ADF4153 Data Sheet Reference Spurs LE SYNC (INTERNAL) PLL SETTLES TO INCORRECT PHASE The output of a fractional-N PLL can settle to any one of MOD phase offsets with respect to the input reference, where MOD is the fractional modulus. The phase resync feature in the ADF4153 can be used to produce a consistent output phase offset with respect to the input reference. This is necessary in applications where the output phase and frequency are important, such as digital beam-forming. When phase resync is enabled, an internal timer generates sync signals at intervals of tSYNC given by the following formula: tSYNC = RESYNC × RESYNC_DELAY × tPFD PLL SETTLES TO CORRECT PHASE AFTER RESYNC PHASE –100 PHASE RESYNC LAST CYCLE SLIP FREQUENCY SPUR CONSISTENCY When jumping from Frequency A to Frequency B and then back again using some fractional-N synthesizers, the spur levels often differ each time Frequency A is programmed. However, in the ADF4153, the spur levels on any particular channel are always consistent. tSYNC 03685-030 Reference spurs are generally not a problem in fractional-N synthesizers because the reference offset is far outside the loop bandwidth. However, any reference feedthrough mechanism that bypasses the loop can cause a problem. One such mechanism is feedthrough of low levels of on-chip reference switching noise out through the RFIN pin back to the VCO, resulting in reference spur levels as high as –90 dBc. Care should be taken in the PCB layout to ensure that the VCO is well separated from the input reference to avoid a possible feed-through path on the board. 0 100 200 300 400 500 600 TIME (µs) 700 800 900 1000 Figure 17. Phase Resync Example FILTER DESIGN—ADIsimPLL A filter design and analysis program is available to help the user implement PLL design. Visit www.analog.com/pll for a free download of the ADIsimPLL software. The software designs, simulates, and analyzes the entire PLL frequency domain and time domain response. Various passive and active filter architectures are allowed. INTERFACING The ADF4153 has a simple SPI®-compatible serial interface for writing to the device. CLK, DATA, and LE control the data transfer. When latch enable (LE) is high, the 22 bits that are clocked into the input register on each rising edge of SCLK are transferred to the appropriate latch. See Figure 2 for the timing diagram and Table 5 for the register truth table. The maximum allowable serial clock rate is 20 MHz. where tPFD is the PFD reference period. RESYNC is the decimal value programmed in Bits DB[15…12] of Register R2 and can be any integer in the range of 1 to 15. If RESYNC is programmed to its default value of all zeros, then the phase resync feature is disabled. If phase resync is enabled, then RESYNC_DELAY must be programmed to a value that is an integer multiple of the value of MOD. RESYNC_DELAY is the decimal value programmed into the MOD bits (DB[13…3] of Register R1 when load control (Bit DB23 of Register R1) = 1. ADuC812 Interface Figure 18 shows the interface between the ADF4153 and the ADuC812 MicroConverter®. Because the ADuC812 is based on an 8051 core, this interface can be used with any 8051-based micro-controller. The MicroConverter is set up for SPI master mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF4153 needs a 24bit word, which is accomplished by writing three 8-bit bytes from the MicroConverter to the device. After the third byte is written, the LE input should be brought high to complete the transfer. When a new frequency is programmed, the second next sync pulse after the LE rising edge is used to resynchronize the output phase to the reference. The tSYNC time should be programmed to a value that is at least as long as the worst-case lock time. Doing so guarantees that the phase resync occurs after the last cycle slip in the PLL settling transient. In the example shown in Figure 17, the PFD reference is 25 MHz and MOD = 125 for a 200 kHz channel spacing. tSYNC is set to 400 µs by programming RESYNC = 10 and RESYNC_DELAY = 1000. ADuC812 SCLOCK MOSI ADF4153 CLK DATA LE I/O PORTS 03685-024 MUXOUT (LOCK DETECT) Figure 18. ADuC812 to ADF4153 Interface Rev. F | Page 20 of 24 Data Sheet ADF4153 When operating in this mode, the maximum SCLOCK rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the output frequency can be changed is 180 kHz. ADSP-21xx Interface Figure 19 shows the interface between the ADF4153 and the ADSP-21xx digital signal processor. As discussed previously, the ADF4153 needs a 24-bit serial word for each latch write. The easiest way to accomplish this using the ADSP-21xx family is to use the autobuffered transmit mode of operation with alternate framing. This provides a means for transmitting an entire block of serial data before an interrupt is generated. Set up the word length for eight bits and use three memory locations for each 24-bit word. To program each 24-bit latch, store the three 8-bit bytes, enable the autobuffered mode, and write to the transmit register of the DSP. This last operation initiates the autobuffer transfer. ADSP-21xx ADF4153 SCLK DT TFS The lands on the chip scale package (CP-20) are rectangular. The printed circuit board (PCB) pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land should be centered on the pad. This ensures that the solder joint size is maximized. The bottom of the chip scale package has a central thermal pad. The thermal pad on the PCB should be at least as large as this exposed pad. On the PCB, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. This ensures that shorting is avoided. Thermal vias can be used on the PCB thermal pad to improve thermal performance of the package. If vias are used, they should be incorporated in the thermal pad at 1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with one ounce of copper to plug the via. The user should connect the PDB thermal pad to AGND. DATA LE MUXOUT (LOCK DETECT) 03685-025 I/O FLAGS CLK PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE Figure 19. ADSP-21xx to ADF4153 Interface Rev. F | Page 21 of 24 ADF4153 Data Sheet APPLICATIONS INFORMATION LOCAL OSCILLATOR FOR A GSM BASE STATION TRANSMITTER The charge pump current is ICP = 5 mA. ADIsimPLL is used to calculate the loop filter. It is designed for a loop bandwidth of 20 kHz and a phase margin of 45 degrees. Figure 20 shows the ADF4153 being used with a VCO to produce the local oscillator (LO) for a GSM base station transmitter. The loop filter output drives the VCO, which in turn is fed back to the RF input of the PLL synthesizer. It also drives the RF output terminal. A T-circuit configuration provides 50 Ω matching between the VCO output, the RF output, and the RFIN terminal of the synthesizer. The reference input signal is applied to the circuit at REFIN and, in this case, is terminated in 50 Ω. A 25 MHz reference is used, which is fed directly to the PFD. To achieve 200 kHz channel spacing, a modulus of 125 is necessary. Note that with a modulus of 125, which is not divisible by 2, 3 or 6, subfractional spurs are avoided. See the Spur Mechanisms section for more information. In a PLL system, it is important to know when the loop is in lock. This is achieved by using the MUXOUT signal from the synthesizer. The MUXOUT pin can be programmed to monitor various internal signals in the synthesizer. One of these is the lock detect signal. The charge pump output of the ADF4153 drives the loop filter. VDD VP 10pF 100nF 100nF 15 7 10 AVDD DVDD 1000pF 8 100pF 14 VP CP 1000pF FREFIN VCC 160Ω 2 ADF4153 14 3 4 DGND AGND CPGND SPI-COMPATIBLE SERIAL BUS RFINA RSET RFINB 10 100pF 18Ω 18Ω 18Ω 8.2nF 270nF MUXOUT 5.1kΩ 82Ω 22nF CLK DATA LE 2 VCO190-902T REFIN 51Ω RFOUT 16 SVDD 100nF 10µF 6 LOCK DETECT 100pF 51Ω 5 100pF 9 DECOUPLING CAPACITORS SHOULD BE PLACED AS CLOSE AS POSSIBLE TO THE PINS. Figure 20. Local Oscillator for a GSM Base Station Transmitter Rev. F | Page 22 of 24 03685-028 10µF Data Sheet ADF4153 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 21. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters 4.10 4.00 SQ 3.90 0.60 MAX 0.60 MAX 15 PIN 1 INDICATOR 20 16 1 PIN 1 INDICATOR 3.75 BCS SQ 0.50 BSC 2.25 2.10 SQ 1.95 EXPOSED PAD 5 10 1.00 0.85 0.80 SEATING PLANE 12° MAX 0.80 MAX 0.65 TYP 0.30 0.23 0.18 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 6 11 BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1 Figure 22. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-20-1) Dimensions shown in millimeters Rev. F | Page 23 of 24 0.25 MIN 04-09-2012-B TOP VIEW 0.75 0.60 0.50 ADF4153 Data Sheet ORDERING GUIDE Model 1, 2 ADF4153BRU ADF4153BRU-REEL7 ADF4153BRUZ ADF4153BRUZ-RL ADF4153BRUZ-RL7 ADF4153YRUZ ADF4153YRUZ-RL ADF4153YRUZ-RL7 ADF4153BCPZ ADF4153BCPZ-RL ADF4153BCPZ-RL7 ADF4153YCPZ ADF4153YCPZ-RL ADF4153YCPZ-RL7 ADF4153WYRUZ-RL7 EV-ADF4153SD1Z 1 2 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 16-Lead Thin Shrink Small Outline Package [TSSOP] Evaluation Board Package Option RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 CP-20-1 CP-20-1 CP-20-1 CP-20-1 CP-20-1 CP-20-1 RU-16 Z = RoHS Compliant Part. W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The ADF4153WYRUZ-RL7 model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for this model. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2003–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03685-0-11/13(F) Rev. F | Page 24 of 24