PDF Meeting Transient Specifications in Mil Vehicles

MEETING TRANSIENT SPECIFICATIONS
FOR ELECTRICAL SYSTEMS IN MILITARY VEHICLES
By Arthur Jordan Sr. Applications Engineer, Vicor
Electrical systems in military vehicles are normally required
to meet stringent transient requirements. Typical of these
specifications are MIL-STD-1275B in the U.S.A. and DEF-STAN
61-5 (Part 6)/Issue 5 in the UK. Although the specified levels
of these surges and spikes are outside the capability of
Vicor 2nd Generation modules, it is quite possible, with simple
circuitry, to make the 24 V input (18-36 V input range) DC-DC
converter modules compliant to these specifications for the
28 V vehicle voltage system. Other electro-magnetic
compatibility requirements, such as MIL-STD-461E and/or
DEF-STAN 59-41, apply to military vehicles, but these are
outside the scope of this application note. In order to meet
additional conducted emission requirements an input filter,
preceding the transient protection circuit covered in this
application note, will be required.
The transients on this 28 V rail fall into two types:
i) Spikes: typically high voltage rise, short duration and low energy.
ii) Surges: typically lower voltages rise, long duration and high energy.
Many systems are battery plus generator fed with spike
and surge requirements that can be easily met using the
M-FIAM5 filter and transient protection module. The level of
immunity imposed by MIL-STD-1275 and DEF STAN 61-5;
however, require additional protection such as that presented here. Incidentally, both surges and spikes are most
onerous in generator-only systems. Table 1 summarizes the
worst-case spike and surge requirements for the two
specifications.
Table 1 Worst-case transient requirements
Spikes
Surges
MIL-STD-1275B
DEF-STAN 61-5
Amplitude ±250 V 50 µs
spike width in a burst up
to 1 ms duration with
15 mJ maximum energy
content per spike.
Amplitude +270 V &
-220 V 10 µs max. Plus
+110 V train of spikes
lasting up to 5 ms.
100 V for 50 ms from a
0.5 Ω source impedance,
repeated 5 times once
per second.
100 V (+5/-0%) for 50 ms
from a 0.55 Ω source
impedance, repeated 5
times once per second.
(Annex C).
Note: Low line dips to 15 V specified in the above specifications are likely
to result in the DC-DC converter module turning off during this period.
Cranking voltages will also activate the under voltage lock out.
To protect the power converter module from these transients, two separate techniques must be used. For spikes,
a parallel transient filter, e.g. input TransZorbs®, can easily
remove these low energy high voltage bursts. Three P6KE33A
should be placed in series and connected across the input
rail, but a single 1.5KE100A could be an adequate
alternative for spike removal. For surges, because of their
duration and energy, the only feasible removal method is
a series surge suppression circuit, i.e., a properly controlled
power semiconductor(s) is/are placed in series with the
input line. Since the 24 V modules have a maximum input
voltage of 36 V, the ideal surge protection circuit would
allow current to be supplied to the load module, while
dropping the excess voltage associated with a surge event.
The series pass element must dissipate the power associated
with the excess voltage and load current. Large loads
require significant power handling capability. The most
suitable device for this application is a MOSFET. A BJT could
also be used, but during normal operation a 0.5-1 V drop
across this device would have to be tolerated.
Circuit Description and Operation
Figure 1 is a diagram of a transient/surge protection circuit.
High voltage, low energy spikes are absorbed by the capacitor and TransZorbs across the input. All of the remaining
circuitry addresses the problem of high energy surges by
performing two functions. (1) The output is clamped at 35 V
in the event that the input rises beyond that point. (2) If the
overvoltage condition at the input persists for a period
greater than 55 ms, the converter is shut down via the PC pin.
A charge pump provides full enhancement gate bias to
the MOSFET (Q1) during normal operation. This function is
accomplished by U1, an ICM7555 timer, which generates a
rectangular waveform at 109 kHz, that is peak detected
and level shifted by R3, C4, D1 & D3. Capacitor C7 limits
the rate of rise of the voltage across the output to 160-170
V/ms, which in turn, limits the inrush current at start up to
3.5 A with a 1000 µF (C5) capacitor across the output. The
V24 series of modules employ undervoltage lockout at
approximately 17 V, and a soft start feature. Start up takes
longer than 10 ms after crossing the lockout threshold.
Zener diode D5 limits the maximum voltage that can be
applied to the gate of the transient protection MOSFET
page 1 of 8
to 15 V, with respect to its source. If the input voltage
exceeds 35.3 Vdc, this circuit performs as a series pass linear
regulator. The output voltage is compared with the LM10’s
reference voltage (1.95 V). The error signal at the output of
the LM10 is used to control transistor Q2 (2N5550), causing
FET Q1 (IXTH75N10) to act as a voltage regulator. Capacitor
C6 is the main spike removal device (the TransZorbs are only
for added protection). C6 can also help reduce any high
frequency ringing that may be applied to the circuit,
although a small damping resistor in series with this
capacitor may be required if the TransZorbs are not to
be relied upon. D4 is added to limit the maximum voltage
U3
Q1
R6
0.03Ω
U4
D5
D6
R5
1K
ZENER
theoretical handling capability of this MOSFET is given in the
appendix. In short, this MOSFET, provided its case temperature is kept below 70˚C, will provide protection for a 125 W
load (a single V24 micro module, fully loaded) during a
100 V surge lasting 50 ms. A simple additional circuit, shown
in Figure 2, can provide extra system protection in the event
of a sustained overvoltage condition. If a surge lasts longer
than about 50-60 ms, or repeats faster than once per
second, this circuit will turn off the attached module.
Because the power dissipated in the MOSFET is proportional
to loading of the transient protection circuit, it will withstand
100 V surges, in the unloaded condition,
R4
100
D3
1N4148
R13
56k
D1
1N4148
D7
ZENER
D8
ZENER
C6
3.3uF
C4
R15 1nF
68
D4
1N4755
C7
220nF
Q2
2N5550
+
C3
10uF
R3
68
U1
UA555
Gnd
Trg
Out
Rst
Vcc
Dis
Thr
Ctl
+
C5
1000uF
R1
2.2k
R2
5.1k
R14
3.3k
D2
C2
C1
0.01uF
U6
R16
3.6k
1nf
U5
U2
R10 LM10C 1
7
3
10k
+ 6
R9
100k
2
C8
–
4
R11
2.7k
8
10nF
R12
300
Figure 1 Transient Protection Filter Circuit.
on C7, at high line, that may slow down the response time of
this circuit. Usually, this protection circuit should be placed
after the system’s EMI filter, because a differential source
inductance of at least 10 µH is recommended to ensure that
Q1 is not over stressed during high slew rate events.
Differential inductance in excess of this value is also required
to meet military EMI requirements. The value of C5 is
dependent on the module and the application, but it must
not exceed 1000 µF for this circuit. Normally, 330 µF is a large
enough input capacitor for a single module.
In the circuit of Figure 1 power handling is limited by FET Q1,
particularly during the surges. A brief explanation of the
almost indefinitely. This additional protection should be
employed in most applications.
U3
Transient Filter Input
D9
BZX84C36LT1
U7
To 'PC'
R7
11k
Q3
BC107BP
U6
R8
910
+
C9
470uF
U5
To '-IN'
Ground
Figure 2 Surge Duration Protection Circuit.
page 2 of 8
Low Line Operation
For the circuit of Figure 1 used at the suggested power, there
will be approximately 120 mV drop due to the ON resistance
of the MOSFET. Some further allowance should also be made
for the EMI filter and trace resistances. Therefore, low line
performance can be improved by using larger or paralleled
MOSFETs. Although the maximum undervoltage turn on
voltage for ‘V24’ range of modules is 18.0 V, they will in most
instances operate (with some derating) down to 16.5 V
input, once started. Please note that many applications do
not require operation during cranking but must operate
down to 22 V (with up to 4 V ripple for DEF STAN 61-5) and
18.4 V minimum (including ripple) for MIL-STD-1275B.
temperature does not exceed 57˚C before the application
of the surge. However, since distributors and suppliers often
do not stock these parts, a custom array of MOSFETs is often
the only recourse. MOSFETs will share current adequately
during a surge event if the following conditions are met.
a) All the MOSFETs in the array are of the same type
and ideally from the same production batch.
b) All the MOSFETs in the array are thermally
coupled to the same heat sink, (i.e. all the MOSFETs
need to have the same device temperature).
c) All the MOSFETs in the array have their own gate
resistor, (i.e. each MOSFET must have its own
22-100 Ω, R4 resistor).
d) Drain, gate and source, current traces should be
of similar lengths and impedance.
e) A small source resistor R6 can be added for
improved MOSFET current sharing, if required.
Filtering Higher Power Modules
To provide transient protection for higher power modules,
e.g. Mini and Maxi modules, either MOSFETs with larger Safe
Operating Areas (SOAs), or arrays of MOSFETs must be used.
Presently, there is limited availability of dies of the required
size to achieve the low thermal impedance required.
However, many manufacturers make packaged arrays of
MOSFETs for higher power applications such as the IRFK6J150
(six MOSFETs in parallel in this TO-240 package) that have a
sufficiently large SOA to provide protection for a single Mini
module (fully loaded) provided this HEX-pak case
A discussion of the reasoning behind these criteria is given
in the Appendix & Notes section. Under the above ideal
circumstances, sharing should be very accurate; however,
because points (a) and (b) are unlikely to be always met,
some degree of derating is advisable. Table 2 shows the
suggested power handling capability of the IXTH75N10 at
50˚C, 60˚C, 70˚C & 80˚C case temperatures.
Table 2 IXTH75N10 Power Handling vs. Case Temperature.
Case Temperature
Q1
Q1x
2
Q1x
3
Q1x
4
50˚C
163 W
288 W
403 W
500 W
60˚C
144 W
250 W
346 W
424 W
70˚C
125 W
212 W
289 W
348 W
80˚C
106 W
174 W
232 W
272 W
Therefore greater reliability will be achieved by having individual transient protection tailored for each module in a power application.
page 3 of 8
Appendix and Notes
Bill of Materials for the circuit shown in Figure 1.
Circuit Reference
U1
U2
Q1
Q2
Q3
D1
D2
D3
D4
D5
D6
D7
D8
D9
C1
C2
C3
C4
C5
C6
C7
C8
C9
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
Part Number
ICM7555
LM10CN
IXTH75N10
2N5550
BC107B
1N4148
BZX85C12
1N4148
1N4755
1N5245
P6KE33A
P6KE33A
P6KE33A
BZX84C36
Description & Notes
CMOS 555 Timer (Intersil)
Op Amp & band-gap reference
100 V 75 A Power MOSFET (IXYS)*
NPN Epitaxial BJT (Fairchild)
NPN BJT (Philips)
Silicon signal diode
12 V Zener (1.3 W).
Silicon signal diode
43 V Zener
15 V Zener
Transzorb (600 W)
Transzorb (600 W)
Transzorb (600 W)
36 V Zener
Capacitor MF 10 nF (63 V)
Capacitor MF 1 nF (63 V)
Capacitor 10 µF (16 V)
Capacitor MF 1 nF (63 V)
Module Input capacitor 220 µF-1000 µF
Capacitor MF 3.3 µF (100 V)
Capacitor MF 220 nF (63 V)
Capacitor MF 10 nF (63 V)
Capacitor 470 µF (6.3 V)
Resistor 2.2k (0.125 W)
Resistor 5.1k (0.125 W)
Resistor 68 Ω (0.125 W)
Resistor 100 Ω (0.125 W)*
Resistor 1k (2 W) Metal Oxide
Resistor 30 mΩ (2.5 W) Metal Oxide**
Resistor 11k (0.4 W)
Resistor 910 Ω (0.125 W)
Resistor 100k (0.125 W)
Resistor 10k (0.125 W)
Resistor 2.7k (0.125 W)
Resistor 300 Ω (0.125 W)
Resistor 56k (0.125 W)
Resistor 3.3k (0.125 W)
Resistor 68 Ω (0.125 W)
Resistor 3.6k (0.125 W)
* Additional MOSFETs and gate resistors are needed for higher power requirements, e.g., four for applications that use a 400 Watt converter module.
** Only for use with parallel MOSFETs applications when sharing is poor.
page 4 of 8
MOSFET Safe Operating Area (SOA)
The power handling capability of a device such as a
MOSFET is referred to as the safe operating area for that
device. A typical graph is shown in Figure 3.
More informative data can be often obtained from the
transient thermal impedance data for the device in
question. From this information the power handling of a
particular MOSFET at a particular die temperature can be
determined. Generally, the SOA data is available only at
25˚C junction temperature. Transient thermal impedance
data (see Figure 4) can be used to calculate the safe initial
temperature of the MOSFET, for a given pulse of defined
energy.
Figure 3 SOA curve for an IXTH75N10
Figure 4 Transient Thermal Impedance.
For example an IXTH75N10 with a 0.05 duty cycle (50 ms in
1sec) has a transient thermal impedance for a 50 ms pulse
of about 0.28˚C/W. Therefore if a current of 3.5 A is flowing
through a single MOSFET during a 100 V surge (of which 35.3
V appears across the module, provided the surge protection
circuit above is used) the expected die temperature rise is
estimated at:
∆T = 63.4˚C = (100 V-35.3 V) x 3.5 A x 0.28˚C/W
Since this MOSFET has a maximum operating junction
temperature of 150˚C (some manufacturers claim higher
maximum junction temperatures2) this limits the maximum
temperature, at the start of the surge to 86˚C. A further rise
of 5˚C is to be expected due to the 5 repeated surges,
limiting the maximum initial die temperature to 81˚C. This is
the reason for the recommended maximum starting case
temperatures in the text. The recommended maximum also
allows for a suitable safety margin, plus the normal conduction dissipation temperature rise, of the die junction above
case, occurring prior to the surge. (Note: A larger C5 value
can also reduce the SOA, as C5 is rapidly charged at the
beginning of a surge to 35.3 V, resulting in extra MOSFET
dissipation).
page 5 of 8
The choice of R6, point (e), should ideally be:
Expanding Power Handling
Ideally choosing a larger MOSFET is the best solution for
higher power applications, but these are often not available,
so the alternative is to parallel MOSFETs. MOSFETs will
approximately share load current provided the requirements
for points (a) & (b) in the above text are adhered to1,3,4.
Arrays of MOSFETs need individual gate resistances (c) to
prevent high-frequency oscillation, particularly when used in
a linear mode5. Normally, a value of between 22-100 ohms is
recommended; however, for this application, because fast
charging of the module input capacitance is not required
and may result in detrimental system reliability, a 100 Ω
resistor is more appropriate. A 100 Ω resistor may reduce the
requirement for circuit input impedance as well. Besides
point (d) being good engineering practice, it will help to
ensure that the instantaneous voltages applied to the gate
of each MOSFET are similar.
R6 >1/gm Therefore, R6 >1/25 = 0.04 Ω for the IXTH75N10
The larger the resistance of R6, the better the current
sharing, but at the expense of dissipation and low line
operation3. For example, a value of 100 mΩ would result in
about a 0.7 V drop across the filter during low line dips. That
may not be acceptable given the operating range of the
Vicor 2nd Generation 24 V input modules. Furthermore, each
resistor would dissipate about 2 W typically. However, as the
waveforms below show, even a much smaller value of
MOSFET source resistance can help. R6 between 30-50 mΩ
seems to be quite a good compromise with the IXTH75N10
in this application, but this device should not be necessary
if a well-laid-out design is used.
Waveforms & Data
Note: A mechanical switch in series with a 100 V source was used to simulate the surge.
Ch1
Ch1
Ch2
Ch2
Fig. 5 Turn On Characteristics at 400 W load.
Ch1 = ‘24’ Module Input voltage
Ch2 = Input Current 1275 Filter. 5 A/div.
Four IXTH75N10 in parallel
Fig. 6 Surge Performance
Ch1 = Voltage Applied to filter
Ch2 = Voltage Applied to V24A28C400AL at full load
Ch2
Ch2
Ch 1
Fig. 7 Surge Performance (Faster time-base)
Ch1 = Voltage Applied to V24A28C400AL at full load.
Ch2 = Voltage Applied to filter
Ch 1
Fig. 8 Input & Output Voltage (Surge End 70 W load).
Ch1 = Voltage Applied to V24A28C400AL.
Ch2 = Voltage Applied to filter
page 6 of 8
Ch1
Vin
Ch 2
Conn Vo
Fig. 9 Surge PC Voltage
Ch1 = Input to 1275 Filter
Ch2 = PC pin voltage during surge
Fig. 10 Input & Output Characteristics
Ch1 = Input to 1275 Filter
Ch2 = V24A28C400A output voltage at full load
Ch1
Ch1
Ch 2
Ch 2
Fig. 11 Input Current & Voltage
Ch1 = Input to 1275 filter
Ch2 = Input current to filter at full load 5 A/div
Fig. 13 FET 1 Current & Module Vin
Ch1 = Vin of V24A28C400A (Full Load)
Ch2 = FET 1 current 2 A/div
Fig. 12 Module Input Voltage & System Current
Ch1 = Vin for V24A28C400A
Ch2 = Filter input current 17-13A (5 A/div)
Ch1
Ch1
High 35.4 V
High 35.8 V
Ch 2
Ch 2
Fig. 14 FET 2 Current
Ch1 = Vin of V24A28C400A (Full Load)
Ch2 = FET 2 current 2 A/div
Note: FET 3 & 4 were laid out some distance from FETs 1 & 2 to show typical performance degradation.
page 7 of 8
Ch1
Ch1
High 35 V
High 35 V
Ch 2
Ch 2
Fig. 16 FET 4 Current
Ch1 = Vin of V24A28C400A (Full Load)
Ch2 = FET 4 current 2 A/div
Fig. 15 FET 3 Current
Ch1 = Vin of V24A28C400A (Full Load)
Ch2 = FET 3 current 2 A/div
Effect of adding an individual 30 mΩ source resistance to each MOSFET.
Ch1
Ch1
High 35 V
High 35 V
Ch 2
Ch 2
Fig. 17 Effect of 30 mR. FET 2 Current
Ch1 = Vin of V24A28C400A (Full Load)
Ch2 = FET 2 current 2 A/div
Fig. 18 Effect of 30 mR. FET 3 Current
Ch1 = Vin of V24A28C400A (Full Load)
Ch2 = FET 3 current 2 A/div
References.
(1)
(2)
(3)
(4)
(5)
MOSFET Linear Operation by Mark Alexander.
Safe Operating Area and Thermal Design for MOSPOWER Transistors by Rudy Severns.
Parallel Operation of Power MOSFETs by Rudy Severns
Thermally Forced Current Sharing in Paralleled Power MOSFETs by John G. Kassakian.
An Analysis and Experimental Verification of Parasitic Oscillations in Paralleled Power MOSFETs
by David Lau (from IEEE Transactions on Electron Devices, Vol. ED-31 No.7 July 1984).
Technical advice furnished by Vicor is provided as a free service, whose intent is to facilitate successful implementation of Vicor Products. Vicor
assumes no obligation or liability for the advice given, or results obtained. All such advice being given and accepted is at User's risk.
Vicor Corporation
25 Frontage Road / Andover, MA 01810
Tel. 978.470.2900 / Fax 978.475.6715 / vicorpower.com
Applications Engineer 800.927.9474
Factorized Power
Aug 04
APPNOTE_Mil_VTS
page 8 of 8