PI6C2972 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Low Voltage PLL Clock Driver Description Features The PI6C2972 are 3.3V compatible, PLL based clock driver devices targeted for high-performance CISC or RISC processor based systems. With output frequencies of up to 125 MHz and skews of 550ps the PI6C2972 are ideally suited for most synchronous systems. The devices offer twelve low skew outputs plus a feedback and sync output for added flexibility and ease of system implementation. • Fully Integrated PLL • Output Frequency up to 125 MHz • Compatible with PowerPC and Pentium Microprocessors • 3.3V VCC • + 100ps Typical Cycle–to–Cycle Jitter The PI6C2972 features an extensive level of frequency programmability between the 12 outputs as well as the input vs output relationships. Using the select lines output frequency ratios of 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 6:1 and 6:5 between outputs can be realized by pulsing low one clock edge prior to the coincident edges of the Qa and Qc outputs. The Sync output will indicate when the coincident rising edges of the above relationships will occur. The Power–On Reset ensures proper programming if the frequency select pins are set at power up. If the fselFB2 pin is held high, it may be necessary to apply a reset after power–up to ensure synchronization between the QFB output and the other outputs. The internal power–on reset is designed to provide this function, but with power–up conditions being dependent, it is difficult to guarantee. All other conditions of the fsel pins will automatically synchronize during PLL lock acquisition. • Packaging (Pb-free & Green available): - 52-pin LQFP (FC) fselFB0 VCCI QFB GNDO Ext_FB Qb3 VCCO Qb2 GND0 Qb1 VCCO Qb0 GNDO Pin Configuration fselb1 39 38 37 36 35 34 33 32 31 30 29 28 27 26 40 fselb0 41 25 QSync fsela1 42 24 GNDO fsela0 43 23 Qc0 Qa3 44 22 VCCO VCCO 45 21 Qc1 fselFB1 50 16 Qc3 GND0 51 15 GND0 VCO_Sel 52 14 9 10 11 12 13 2 3 4 5 6 7 8 The PI6C2972 is fully 3.3V compatible and requires no external loop filter components. All inputs accept LVCMOS/LVTTL compatible levels while the outputs provide LVCMOS levels with the capability to drive 50-ohm transmission lines. For series terminated lines each PI6C2972 output can drive two 50-ohm lines in parallel thus effectively doubling the fanout of the device. Inv_Clk VCCA 1 xtal1 xtal2 VCCO Qa0 TClk1 17 TClk0 49 TClk_Sel Qc2 VCCO Ref_Sel 18 PLL_EN 48 fselFB2 fselc1 Qa1 Frz_Data fselc0 19 Frz_Clk 20 47 GND1 46 MR/OE Qa2 GNDO The PI6C2972 offers a very flexible output enable/disable scheme. Note that all of the control inputs on the PI6C2972 have internal pull– up resistors. 1 PS8590C 09/22/04 PI6C2972 Low Voltage PLL Clock Driver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Block Diagram xtal_1 xtal_2 VC0_Sel PLL_En REF_Sel D Q Sync Frz 0 TCLK1 0 PHASE DETECTOR 1 TCLK_Sel Qa1 V TCLK0 1 VCO Qa0 Qa2 LPF Qa3 Ext_FB Q Sync Frz Qb0 Qb1 V D Qb2 Qb3 fselFB2 MR/OE D Qc0 Q V POWER-ON RESET Sync Frz Qc1 Sync Frz Qc2 ÷4, ÷6, ÷8, ÷12 D ÷4, ÷6, ÷8, ÷10 Q ÷2, ÷4, ÷6, ÷8 V Qc3 fselFBO:1 Frz_Clk 2 Sync Pulse D QFB Q 1 V fselc0:1 ÷2 2 Data Generator D Q Sync Frz QSync V fselb0:1 0 ÷4, ÷6, ÷8, ÷10 2 V fsela0:1 2 Output Disable Circuitry 12 Frz_Data Inv_Clk 2 PS8590C 09/22/04 PI6C2972 Low Voltage PLL Clock Driver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Function Table 1 fs e la1 fs e la0 Qa fs e lb1 fs e lb0 Qb fs e lc1 fs e lc0 Qc 0 0 1 1 0 1 0 1 ÷4 ÷6 ÷8 ÷12 0 0 1 1 0 1 0 1 ÷4 ÷6 ÷8 ÷ 10 0 0 1 1 0 1 0 1 ÷2 ÷4 ÷6 ÷8 Function Table 2 fs e lFB2 fs e lFB1 fs e lFB0 QFB 0 0 0 0 0 0 1 1 0 1 0 1 ÷4 ÷6 ÷8 ÷10 1 1 1 1 0 0 1 1 0 1 0 1 ÷8 ÷ 12 ÷ 16 ÷ 20 Function Table 3 Control Pin Logic '0' Logic '1' VCO_Sel Ref_Sel TCLK_Sel PLL_En MR/OE Inv_CLK VCO/2 TCLK TCLK0 Bypass PLL Master Reset/Output Hi- Z Non- Inverted Qc2, Qc3 VCO Xtal TCLK1 Enable PLL Enable Outputs Inverted Qc2, Qc3 Crystal Recommendations Parame te rs Value Crystal Cut Fundamental AT Cut Resonance Parallel Resonance Freq. Tolernace ±100ppm @ 25°C Freq. Temp. Stability ±175ppm (0° to 70°C) Operating Range 0° to 70°C Shunt Capacitance < 7pF ESR < 40- Ohm Drive Level 5mW Aging 5ppm / Year (First 3 years) 3 PS8590C 09/22/04 PI6C2972 Low Voltage PLL Clock Driver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Timing Diagrams fVCO 1:1 Mode Qa Qc Sync 2:1 Mode Qa Qc Sync 3:1 Mode Qc( 2) Qa( 6) Sync 3:2 Mode Qa( 4) Qc( 6) Sync 4:1 Mode Qc( 2) Qa( 8) Sync 4:3 Mode Qa( 6) Qc( 8) Sync 1:6 Mode Qa( 12) Qc( 2) Sync 4 PS8590C 09/22/04 PI6C2972 Low Voltage PLL Clock Driver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Absolute Maximum Ratings Symbol Parame te r M in. M a x. Units VCC Supply Voltage –0.3 4.6 V VI Input Voltage –0.3 VDD +0.3 V IIN Input Current ± 20 mA TSTOR Storage Temperature 125 °C –40 *Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. DC Characteristics (TA = 0°C to 70°C, VCC = 3.3V ± 5%)(4) Symbol Conditions Characte ris tic M in. VIH Input HIGH Voltage 2.0 VIL Input LOW Voltage Typ. M ax. 3.6 0.8 VOH IOH = 20mA(2) Output HIGH Voltage VOL IOL = 20mA(2) Output LOW Voltage 0.5 IIN Note 3 Input Current ±120 Maximum Quiescent Supply Current 190 215 ICCA Analog VCC Current 15 20 CIN Input Capacitance Per Output Power Dissipation Capacitance V 2.4 ICC C pd Units µΑ mA 4 pF 25 Notes: 1. VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the VCMR range and the input lies within the VPP specification. 2. The PI6C2972 outputs can drive series or parallel terminated 50 Ohm (or 50 Ohm to VCC/2) transmission lines on the incident edge. 3. Inputs have pull–up/pull–down resistors which affect input current. 4. Special thermal handling may be required in some configurations. 5 PS8590C 09/22/04 PI6C2972 Low Voltage PLL Clock Driver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PLL Input Reference Characteristic (TA = 0°C to 70°C) Symbol Conditions tr, tf fref Characte ris tics M in. TCLK Input Rise/Falls Note 5 M a x. Units 3.0 ns Reference Input Frequency Note 5 100, Note 5 MHz frefDC Reference Input Duty Cycle 25 75 % txtal Crystal Oscillator Frequency 10 25 MHz Notes: 5. Maximum input reference frequency is limited by the VCO lock range and the feedback divider or 100 MHz, minimum input reference frequency is limited by the VCO lock range and the feedback divider. AC Characteristics (TA = 0°C to 70°C, VCC = 3.3V ± 5%) Symbol Characte ris tics Conditions M in. tr, tf Output Rise/Fall Time (Note7) 0.8 to 2.0V 0 . 15 tpw Output Duty Cycle (Note7) tpd Propagation Delay Notes 7, 8, QFB = ÷8 TCLK0 TCLK1 tos Output- to- Output Skew Note 7 fVCO VCO Lock Range fmax Maximum Output Frequency Q (÷2) Q (÷4) Q (÷6) Q (÷8) Typ. M ax. Units 1.2 ns tCYCLE/2 –750 tCYCLE/2 ± 500 tCYCLE/2 +750 –270 –330 13 0 70 530 470 ps 550 200 480 125 120 80 60 Note 7 MHz tjitter Cycle–to–Cycle Jitter (Peak–to–Peak) ± 10 0 ps tPLZ, tPHZ Output Disable Time 2 8 tPZL,tPZH Output ENable TIme 2 10 tlock Maximum PLL Lock Time 10 ms fMAX Maximum Frz_Clk Frequency 20 MHz ns Notes: 7. 50 Ohm transmission line terminated into VCC/2 8. tpd is specified for a 50 MHz input reference. The window will shrink/grow proportionally from the minimum limit with shorter/ longer input reference periods. The tpd does not include jitter. 6 PS8590C 09/22/04 PI6C2972 Low Voltage PLL Clock Driver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Start Bit D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0–D3 are the control bits for Qa0–Qa3, respectively D4–D7 are the control bits for Qb0–Qb3, respectively D8–D10 are the control bits for Qc1–Qc3, respectively D11 is the control bit for QSync Freeze Data Input Protocol Packaging Mechanical: 52-Pin LQFP (FC) 12.00 BSC .472 Square 0.09 0.20 .004 .008 GAUGE PLANE 0.25 mm Square 10.00 BSC .394 0 7 0.45 .018 0.75 .030 1.00 REF .039 1.60 Max. .063 .004 0.10 Seating Plane 0.22 .009 0.38 .015 0.65 BSC .026 0.05 0.15 .002 .006 1.35 1.45 .053 .057 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Ordering Information Ordering Code PI6C2972FC PI6C2972FCE Package Code FC FC Package Type 52-pin LQFP Pb-free & Green, 52-pin LQFP Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 7 PS8590C 09/22/04