ICS830584I LOW SKEW, PCI-X 1-TO-4 FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS830584I is a low skew, general purpose ICS PCI-X 1-to-4 Fanout Buffer and a member of the HiPerClockS™ HiPerClockS™ family of High Performance Clock Solutions from IDT. Guaranteed output and partto-part skew characteristics make the ICS830584I ideal for those clock distribution applications demanding well defined performance and repeatablility. The ICS830584I is designed and characterized from -40°C to 85°C for industrial applications and is packaged in an 8 TSSOP package. • General purpose and PCI-X 1:4 clock buffer • Four single-ended LVCMOS/LVTTL clock outputs • One single-ended LVCMOS/LVTTL clock input • Maximum output frequency: 140MHz • Output enable control (outputs disabled in logic low state) • Output skew: 100ps (maximum) • Part-to-part skew: 400ps (maximum) • Additive phase jitter, RMS: 0.15ps (typical) • Space-saving 8 lead TSSOP package • Full 3.3V operating supply mode • -40°C to 85°C ambient operating temperature • Available in lead-free (RoHS 6) packages BLOCK DIAGRAM PIN ASSIGNMENT CLKIN OE Q0 GND Q0 Q1 8 7 6 5 Q3 Q2 VDD Q1 ICS830584I CLKIN 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View Q2 Q3 OE IDT ™ / ICS™ PCI-X 1-TO-4 FANOUT BUFFER 1 2 3 4 1 ICS830584AGI REV. B MARCH 31, 2009 ICS830584I LOW SKEW, PCI-X 1-TO-4 FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name Type Description Single-ended clock input reference signal. LVCMOS/LVTTL interface levels. Output enable control input pin. See Table 3, Function Table. LVCMOS / LVTTL interface levels. Single-ended clock outputs. LVCMOS/LVTTL interface levels. 1 CLKIN Input 2 OE Input 3, 5, 7. 8 Q0, Q1, Q2, Q3 Output 4 GND Power Power supply ground. 6 VDD Power Positive supply pin. TABLE 2. PIN CHARACTERISTICS Test Conditions Minimum Typical Maximum Units Symbol Parameter CIN Input Capacitance 4 pF ROUT Output Impedance 15 Ω TABLE 3. FUNCTION TABLE Inputs OE 0 CLKIN 0 Outputs Q0:Q3 0 0 1 0 1 0 0 1 1 1 IDT ™ / ICS™ PCI-X 1-TO-4 FANOUT BUFFER 2 ICS830584AGI REV. B MARCH 31, 2009 ICS830584I LOW SKEW, PCI-X 1-TO-4 FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause per manent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, θJA 121.5°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C TABLE 4A. RECOMMENDED OPERATING CONDITIONS, VDD = 3.3V ± 0.3V, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum 3.3 3.6 VDD Positive Supply Voltage 3.0 VIH High Level Input Voltage 0.7*VDD VIL Low Level Input Voltage VI Input Voltage IOH High-Level Output Current IOL Low-Level Output Current TA Operating Free-Air Temperature Units V V 0.3*VDD 0 -40 V VDD V -24 mA 24 mA 85 °C TABLE 4B. DC CHARACTERISTICS, VDD = 3.3V ± 0.3V, TA = -40°C TO 85°C Symbol Parameter VIK Input Voltage Test Conditions Minimum II = -18mA IOH = -1mA VOH Output High Voltage Typical† Output Low Voltage Units –1.2 V VDD – 0.2 V IOH = -24mA 2 V IOH = -12mA 2.4 V IOL = 1mA VOL Maximum 0.2 V IOL = 24mA 0.8 V IOL = 12mA 0.55 V VO = 1V –50 mA IOH Output High Current IOL Output Low Current II Input Current IDD Dynamic Current Ci Input Capacitance VI = 0V or VDD 3 pF Co Output Capacitance VI = 0V or VDD 3.2 pF VO = 1.65V –5 5 VO = 2V mA 60 VO = 1.65V mA 70 mA VI = 0V or VDD ±150 µA f = 67MHz 37 mA † All typical values are at respective nominal VDD and 25°C. IDT ™ / ICS™ PCI-X 1-TO-4 FANOUT BUFFER 3 ICS830584AGI REV. B MARCH 31, 2009 ICS830584I LOW SKEW, PCI-X 1-TO-4 FANOUT BUFFER TABLE 5. AC CHARACTERISTICS, VDD = 3.3V ± 0.3V, TA = -40°C TO 85°C Symbol Parameter t sk(o) Clock Frequency; NOTE 1 Propagation Delay, Low to High; NOTE 2 Propagation Delay, High to Low; NOTE 2 Output Skew; NOTE 3, 4 t sk(p) Pulse Skew t sk(pr) Process Skew t sk(pp) Par t-to-Par t Skew; NOTE 4, 5 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section fclk tpLH tpHL tjit Thigh CLK High Time Tlow CLK Low Time tR Output Rise Slew Rate‡ Test Conditions Minimum Typical† 0 Maximum Units 140 MHz 1.8 2.5 3 ns 1.8 2.4 3 ns 50 100 ps 170 ps 200 300 ps 250 400 ps 140MHz 140MHz, Integration Range: 10kHz – 20MHz 66MHz 6 ns 140MHz 3 ns 66MHz 6 ns 0.15 140MHz 3 0.2VDD to 0.6VDD 1.5 ps ns 2.7 4 V/ns Output Fall Slew Rate‡ 0.6VDD to 0.2VDD 1.5 2.7 4 V/ns tF † All typical values are at respective nominal VDD. ‡ This symbol is according to PCI-X terminology. NOTE 1: Switching characteristics over recommended ranges of supply voltages and operating free-air temperature, CL = 10pF, VDD = 3.3V ± 0.3V. NOTE 2: Measured from VDD/2 of the input to VDD/2 of the output. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDD/2. IDT ™ / ICS™ PCI-X 1-TO-4 FANOUT BUFFER 4 ICS830584AGI REV. B MARCH 31, 2009 ICS830584I LOW SKEW, PCI-X 1-TO-4 FANOUT BUFFER ADDITIVE PHASE JITTER band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz SSB PHASE NOISE dBc/HZ Input/Output Additive Phase Jitter at 140MHz (12kHz – 20MHz) = 0.15ps typical OFFSET FROM CARRIER FREQUENCY (HZ) device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the IDT ™ / ICS™ PCI-X 1-TO-4 FANOUT BUFFER 5 ICS830584AGI REV. B MARCH 31, 2009 ICS830584I LOW SKEW, PCI-X 1-TO-4 FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION VDD V DD Qx 140Ω 2 Yn V 10pF DD 140Ω Qy 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT Part 1 Qx 2 tsk(o) OUTPUT SKEW VDD VDD V DD 2 2 CLKIN 2 VDD VDD Part 2 Q0:Q3 V DD Qy 2 2 tpLH tpHL 2 tsk(pp) PART-TO-PART SKEW PROPAGATION DELAY V DD 2 Q0:Q3 t PW t odc = tcyc PERIOD t PW thigh x 100% 0.6VDD VIH(min) t PERIOD tlow Vtest VIL(max) 0.2VDD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 0.6VDD VF 0.2VDD Q0:Q3 Parameter 0.6VDD VR 0.2VDD tR 0.4VDD Peak-to-Peak (min) tF Value Unit VIH(min) 0.5VDD V VIL(max) 0.35VDD V Vtest 0.4VDD V NOTE: All parameters are according to PCI-X 1.0 specifications OUTPUT RISE/FALL SLEW RATES IDT ™ / ICS™ PCI-X 1-TO-4 FANOUT BUFFER CLOCK WAVEFORM 6 ICS830584AGI REV. B MARCH 31, 2009 ICS830584I LOW SKEW, PCI-X 1-TO-4 FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION, CONTINUED Supply Current vs Frequency 35 VDD=3.6V o TA=85 C 30 IDD - Supply Current - mA 25 20 15 10 5 0 0 20 40 60 80 100 120 140 160 f - Frequency - MHz IDT ™ / ICS™ PCI-X 1-TO-4 FANOUT BUFFER 7 ICS830584AGI REV. B MARCH 31, 2009 ICS830584I LOW SKEW, PCI-X 1-TO-4 FANOUT BUFFER APPLICATION INFORMATION RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: OE INPUT The OE pin must be tied either HIGH or LOW. Do not leave floating. LVCMOS OUTPUTS All unused LVCMOS outputs can be left floating. We recommend that there is no trace attached. RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 121.5°C/W 117.3°C/W 115.3°C/W TRANSISTOR COUNT The transistor count for ICS830584I is: 307 IDT ™ / ICS™ PCI-X 1-TO-4 FANOUT BUFFER 8 ICS830584AGI REV. B MARCH 31, 2009 ICS830584I LOW SKEW, PCI-X 1-TO-4 FANOUT BUFFER PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Maximum 8 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 3.10 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT ™ / ICS™ PCI-X 1-TO-4 FANOUT BUFFER 9 ICS830584AGI REV. B MARCH 31, 2009 ICS830584I LOW SKEW, PCI-X 1-TO-4 FANOUT BUFFER TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 830584AGILF 84AIL 8 lead "Lead-Free" TSSOP tube -40°C to 85°C 84AIL 8 lead "Lead-Free" TSSOP 2500 tape & reel -40°C to 85°C 830584AGILFT NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ PCI-X 1-TO-4 FANOUT BUFFER 10 ICS830584AGI REV. B MARCH 31, 2009 ICS830584I LOW SKEW, PCI-X 1-TO-4 FANOUT BUFFER REVISION HISTORY SHEET Rev Table Page B T4B 3 Description of Change DC Characteristics Table - corrected Input Current typo from ±5µA max. to ±150µA max. IDT ™ / ICS™ PCI-X 1-TO-4 FANOUT BUFFER 11 Date 3/18/08 ICS830584AGI REV. B MARCH 31, 2009 ICS830584I LOW SKEW, PCI-X 1-TO-4 FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Japan Asia Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) NIPPON IDT KK Sanbancho Tokyu Bld. 7F, 8-1 Sanbancho Chiyoda-ku, Tokyo 102-0075 +81 3 3221 9822 +81 3 3221 9824 (fax) Integrated Device Technology IDT (S) Pte. Ltd. 1 Kallang Sector, #07-01/06 Kolam Ayer Industrial Park Singapore 349276 +65 6 744 3356 +65 6 744 1764 (fax) IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 +44 (0) 1372 378851 (fax) © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA