HUF76633P3, HUF76633S3S
Data Sheet
October 1999
File Number
4693.3
38A, 100V, 0.036 Ohm, N-Channel, Logic
Level UltraFET Power MOSFET
Packaging
Features
JEDEC TO-220AB
JEDEC TO-263AB
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
GATE
SOURCE
DRAIN
(FLANGE)
HUF76633P3
HUF76633S3S
• Ultra Low On-Resistance
- rDS(ON) = 0.035Ω, VGS = 10V
- rDS(ON) = 0.036Ω, VGS = 5V
• Simulation Models
- Temperature Compensated PSPICE® and SABER©
Electrical Models
- Spice and SABER© Thermal Impedance Models
- www.Intersil.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
Symbol
• Switching Time vs RGS Curves
D
Ordering Information
PART NUMBER
G
S
Absolute Maximum Ratings
PACKAGE
BRAND
HUF76633P3
TO-220AB
76633P
HUF76633S3S
TO-263AB
76633S
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF76633S3ST.
TC = 25oC, Unless Otherwise Specified
HUF76633P3,
HUF76633S3S
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
100
V
100
V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
±16
V
Drain Current
Continuous (TC= 25oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC= 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC= 100oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC= 100oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM
38
39
27
27
Figure 4
A
A
A
A
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UIS
Figures 6, 17, 18
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
145
0.97
W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
Package Body for 10s, See Techbrief TB334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
-55 to 175
oC
300
260
oC
oC
NOTES:
1. TJ = 25oC to 150oC.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
1
CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures.
UltraFET™ is a trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation.
SABER© is a Copyright of Analogy Inc. 1-888-INTERSIL or 407-727-9207 | Copyright © Intersil Corporation 1999.
HUF76633P3, HUF76633S3S
TC = 25oC, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ID = 250µA, VGS = 0V (Figure 12)
100
-
-
V
ID = 250µA, VGS = 0V , TC = -40oC (Figure 12)
90
-
-
V
VDS = 95V, VGS = 0V
-
-
1
µA
VDS = 90V, VGS = 0V, TC = 150oC
-
-
250
µA
VGS = ±16V
-
-
±100
nA
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
BVDSS
IDSS
Gate to Source Leakage Current
IGSS
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 11)
1
-
3
V
Drain to Source On Resistance
rDS(ON)
ID = 39A, VGS = 10V (Figures 9, 10)
-
0.029
0.035
Ω
ID = 27A, VGS = 5V (Figure 9)
-
0.030
0.036
Ω
ID = 27A, VGS = 4.5V (Figure 9)
-
0.031
0.037
Ω
TO-220 and TO-263
-
-
1.03
oC/W
-
-
62
oC/W
-
-
185
ns
-
12
-
ns
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
RθJC
Thermal Resistance Junction to
Ambient
RθJA
SWITCHING SPECIFICATIONS (VGS = 4.5V)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
tr
-
110
-
ns
td(OFF)
-
43
-
ns
tf
-
58
-
ns
tOFF
-
-
150
ns
-
-
95
ns
-
7.5
-
ns
-
55
-
ns
td(OFF)
-
63
-
ns
tf
-
83
-
ns
tOFF
-
-
220
ns
-
56
67
nC
-
30
37
nC
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
VDD = 50V, ID = 27A
VGS = 4.5V, RGS = 4.7Ω
(Figures 15, 21, 22)
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
Fall Time
Turn-Off Time
VDD = 50V, ID = 39A
VGS = 10V,
RGS = 5.1Ω
(Figures 16, 21, 22)
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Qg(TOT)
VGS = 0V to 10V
Gate Charge at 5V
Qg(5)
VGS = 0V to 5V
Qg(TH)
VGS = 0V to 1V
Threshold Gate Charge
VDD = 50V,
ID = 27A,
Ig(REF) = 1.0mA
(Figures 14, 19, 20)
-
2
2.4
nC
Gate to Source Gate Charge
Qgs
-
6
-
nC
Gate to Drain “Miller” Charge
Qgd
-
15
-
nC
-
1820
-
pF
-
415
-
pF
-
115
-
pF
MIN
TYP
MAX
UNITS
ISD = 27A
-
-
1.25
V
ISD = 13A
-
-
1.0
V
trr
ISD = 27A, dISD/dt = 100A/µs
-
-
113
ns
QRR
ISD = 27A, dISD/dt = 100A/µs
-
-
425
nC
CAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 13)
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Diode Voltage
VSD
Reverse Recovery Time
Reverse Recovered Charge
2
TEST CONDITIONS
HUF76633P3, HUF76633S3S
Typical Performance Curves
50
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
40
VGS = 10V
30
VGS = 4.5V
20
10
0.2
0
0
0
25
50
75
100
125
150
175
25
50
75
100
125
150
175
TC, CASE TEMPERATURE (oC)
TC , CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
IDM, PEAK CURRENT (A)
500
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
175 - TC
I = I25
150
VGS = 10V
100
VGS = 5V
30
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10-5
10-4
10-3
10-2
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
3
10-1
100
101
HUF76633P3, HUF76633S3S
Typical Performance Curves
(Continued)
200
IAS, AVALANCHE CURRENT (A)
500
ID, DRAIN CURRENT (A)
100
100µs
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1ms
SINGLE PULSE
TJ = MAX RATED
TC = 25oC
1
10ms
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
100
STARTING TJ = 25oC
10
STARTING TJ = 150oC
1
1
10
100
300
0.001
0.01
VDS, DRAIN TO SOURCE VOLTAGE (V)
0.1
1
10
tAV, TIME IN AVALANCHE (ms)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
80
VGS = 10V
VGS = 5V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
80
60
40
TJ = 175oC
20
TJ = 25oC
40
VGS = 3V
20
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
TJ = -55oC
0
0
1.5
2.0
2.5
3.0
3.5
4.0
0
1
VGS, GATE TO SOURCE VOLTAGE (V)
2
3
4
5
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
3.0
50
45
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
ID = 39A
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
VGS = 3.5V
VGS = 4V
60
40
ID = 27A
35
ID = 15A
30
VGS = 10V, ID = 39A
2.5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
2.0
1.5
1.0
0.5
25
2
4
6
8
10
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
4
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
200
HUF76633P3, HUF76633S3S
Typical Performance Curves
(Continued)
1.2
1.2
ID = 250µA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
NORMALIZED GATE
THRESHOLD VOLTAGE
VGS = VDS, ID = 250µA
1.0
0.8
0.6
1.1
1.0
0.9
0.4
-80
-40
0
40
80
120
160
-80
200
-40
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
C, CAPACITANCE (pF)
CISS = CGS + CGD
COSS ≅ CDS + CGD
CRSS = CGD
100
VGS = 0V, f = 1MHz
10
0.1
40
80
120
160
200
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
VGS , GATE TO SOURCE VOLTAGE (V)
5000
1000
0
TJ , JUNCTION TEMPERATURE (oC)
10
VDD = 50V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 39A
ID = 27A
ID = 15A
2
0
1
10
0
100
10
20
30
40
50
60
Qg, GATE CHARGE (nC)
VDS , DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
400
500
VGS = 10V, VDD = 50V, ID = 39A
SWITCHING TIME (ns)
SWITCHING TIME (ns)
VGS = 4.5V, VDD = 50V, ID = 27A
300
tr
200
td(OFF)
tf
100
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
5
td(OFF)
300
tf
200
tr
100
td(ON)
td(ON)
0
0
0
400
50
0
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
50
HUF76633P3, HUF76633S3S
Test Circuits and Waveforms
VDS
BVDSS
L
tP
VARY tP TO OBTAIN
REQUIRED PEAK IAS
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
tP
0V
IAS
0
0.01Ω
tAV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 10V
VGS
Qg(5)
+
VDD
VGS = 5V
VGS
DUT
VGS = 1V
Ig(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
VDS
tON
tOFF
td(ON)
td(OFF)
tf
tr
RL
VDS
90%
90%
+
VGS
VDD
-
10%
10%
0
DUT
90%
RGS
VGS
VGS
0
FIGURE 21. SWITCHING TIME TEST CIRCUIT
6
10%
50%
50%
PULSE WIDTH
FIGURE 22. SWITCHING TIME WAVEFORM
HUF76633P3, HUF76633S3S
PSPICE Electrical Model
.SUBCKT HUF76633 2 1 3 ;
rev 10 September1999
CA 12 8 3.50e-9
CB 15 14 3.50e-9
CIN 6 8 1.70e-9
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
LDRAIN
DPLCAP
DRAIN
2
5
10
5
51
ESLC
11
-
RDRAIN
6
8
EVTHRES
+ 19 8
+
LGATE
GATE
1
EVTEMP
RGATE +
18 22
9
20
21
DBODY
-
16
MWEAK
6
MMED
MSTRO
RLGATE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
+
17
EBREAK 18
50
-
IT 8 17 1
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 2.04e-2
RGATE 9 20 2.15
RLDRAIN 2 5 10
RLGATE 1 9 51.7
RLSOURCE 3 7 21.3
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 4.85e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
DBREAK
+
RSLC2
ESG
LDRAIN 2 5 1.00e-9
LGATE 1 9 5.17e-9
LSOURCE 3 7 2.13e-9
RLDRAIN
RSLC1
51
EBREAK 11 7 17 18 120.7
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
RLSOURCE
S2A
S1A
12
S1B
CA
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
VBAT
5
8
EDS
-
-
IT
14
+
+
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
RBREAK
15
14
13
13
8
-
+
8
22
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*79),3.5))}
.MODEL DBODYMOD D (IS = 1.96e-12 RS = 3.87e-3 TRS1 = 9.93e-4 TRS2 = 4.97e-6 CJO = 1.53e-9 TT = 7.41e-8 M = 0.50)
.MODEL DBREAKMOD D (RS = 3.12e-1 TRS1 = 1.07e-3 TRS2 = 0)
.MODEL DPLCAPMOD D (CJO = 1.97e-9 IS = 1e-30 M = 0.87)
.MODEL MMEDMOD NMOS (VTO = 1.73 KP = 2.80 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.15)
.MODEL MSTROMOD NMOS (VTO = 2.04 KP = 80 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.50 KP = 0.10 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 21.5 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 9.74e-4 TC2 = -3.71e-7)
.MODEL RDRAINMOD RES (TC1 = 9.71e-3 TC2 = 2.90e-5)
.MODEL RSLCMOD RES (TC1 = 2.17e-3 TC2 = 1.27e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -2.08e-3 TC2 = -6.82e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.52e-3 TC2 = -1.21e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -6.00 VOFF= -1.50)
VON = -1.50 VOFF= -6.00)
VON = -0.50 VOFF= 0.0)
VON = 0.0 VOFF= -0.50)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
7
HUF76633P3, HUF76633S3S
SABER Electrical Model
REV 10 September 1999
template huf76633 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 1.96e-12, cjo = 1.53e-9, tt = 7.41e-8, m = 0.50)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 1.97e-9, is = 1e-30, m = 0.87 )
m..model mmedmod = (type=_n, vto = 1.73, kp = 2.8, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.04, kp = 80, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.50, kp = 0.1, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.00, voff = -1.50)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -1.50, voff = -6.00)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.50, voff = 0.0)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.0, voff = -0.50)
LDRAIN
DPLCAP
DRAIN
2
5
10
RSLC1
51
RLDRAIN
RDBREAK
RSLC2
c.ca n12 n8 = 3.50e-9
c.cb n15 n14 = 3.50e-9
c.cin n6 n8 = 1.70e-9
72
ISCL
EVTHRES
+ 19 8
+
LGATE
i.it n8 n17 = 1
GATE
1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 5.17e-9
l.lsource n3 n7 = 2.13e-9
RDRAIN
6
8
ESG
EVTEMP
RGATE + 18 22
9
20
21
DBODY
EBREAK
+
17
18
MSTRO
-
8
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
LSOURCE
7
RSOURCE
RLSOURCE
S1A
12
S2A
13
8
S1B
CA
RBREAK
15
14
13
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
-
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/79))** 3.5))
}
}
-
IT
14
+
+
spe.ebreak n11 n7 n17 n18 = 120.7
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
8
MWEAK
MMED
CIN
71
11
16
6
RLGATE
res.rbreak n17 n18 = 1, tc1 = 9.74e-4, tc2 = -3.71e-7
res.rdbody n71 n5 = 3.87e-3, tc1 = 9.93e-4, tc2 = 4.97e-6
res.rdbreak n72 n5 = 3.12e-1, tc1 = 1.07e-3, tc2 = 0
res.rdrain n50 n16 = 20.40e-3, tc1 = 9.71e-3, tc2 = 2.90e-5
res.rgate n9 n20 = 2.15
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 51.7
res.rlsource n3 n7 = 21.3
res.rslc1 n5 n51 = 1e-6, tc1 = 2.17e-3, tc2 = 1.27e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 4.85e-3, tc1 = 1.00e-3, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 = -1.52e-3, tc2 = 1.21e-7
res.rvthres n22 n8 = 1, tc1 = -2.08e-3, tc2 = -6.82e-6
DBREAK
50
-
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
RDBODY
VBAT
5
8
EDS
-
+
8
22
RVTHRES
SOURCE
3
HUF76633P3, HUF76633S3S
SPICE Thermal Model
th
JUNCTION
REV 9 September1999
HUF76633T
CTHERM1 th 6 2.90e-3
CTHERM2 6 5 1.25e-2
CTHERM3 5 4 1.00e-2
CTHERM4 4 3 6.50e-3
CTHERM5 3 2 2.75e-2
CTHERM6 2 tl 12.55
RTHERM1
RTHERM1 th 6 7.04e-3
RTHERM2 6 5 1.75e-2
RTHERM3 5 4 4.94e-2
RTHERM4 4 3 2.77e-1
RTHERM5 3 2 4.18e-1
RTHERM6 2 tl 5.54e-2
RTHERM2
CTHERM1
6
CTHERM2
5
RTHERM3
CTHERM3
SABER Thermal Model
SABER thermal model HUF76633T
4
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 2.90e-3
ctherm.ctherm2 6 5 = 1.25e-2
ctherm.ctherm3 5 4 = 1.00e-2
ctherm.ctherm4 4 3 = 6.50e-3
ctherm.ctherm5 3 2 = 2.75e-2
ctherm.ctherm6 2 tl = 12.55
RTHERM4
CTHERM4
3
RTHERM5
rtherm.rtherm1 th 6 = 7.04e-3
rtherm.rtherm2 6 5 = 1.75e-2
rtherm.rtherm3 5 4 = 4.94e-2
rtherm.rtherm4 4 3 = 2.77e-1
rtherm.rtherm5 3 2 = 4.18e-1
rtherm.rtherm6 2 tl = 5.54e-2
}
CTHERM5
2
RTHERM6
CTHERM6
tl
CASE
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