HUF76129D3, HUF76129D3S
Data Sheet
20A, 30V, 0.016 Ohm, N-Channel, Logic
Level UltraFET Power MOSFETs
These N-Channel power MOSFETs
are manufactured using the
innovative UltraFET™ process.
This advanced process technology
achieves the lowest possible on-resistance per silicon area,
resulting in outstanding performance. This device is capable
of withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, lowvoltage bus switches, and power management in portable
and battery-operated products.
September 1999
File Number
4394.5
Features
• Logic Level Gate Drive
• 20A, 30V
• Ultra Low On-Resistance, rDS(ON) = 0.016Ω
• Temperature Compensating PSPICE® Model
• Temperature Compensating SABER© Mode
• Thermal Impedance SPICE Model
• Thermal Impedance SABER Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
Formerly developmental type TA76129.
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Ordering Information
Symbol
PART NUMBER
PACKAGE
BRAND
HUF76129D3
TO-251AA
76129D
HUF76129D3S
TO-252AA
76129D
D
G
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-252AA variant in tape and reel, e.g., HUF76129D3ST.
S
Packaging
JEDEC TO-251AA
JEDEC TO-252AA
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
DRAIN
(FLANGE)
GATE
SOURCE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
UltraFET™ is a trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation.
SABER© is a Copyright of Analogy Inc. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
HUF76129D3, HUF76129D3S
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified
UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
30
V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
30
V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
±16
V
Drain Current
Continuous (TC = 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Continuous (TC = 100oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Continuous (TC = 100oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
20
20
20
Figure 4
A
A
A
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Figures 6, 17, 18
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
105
.83
W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
-55 to 150
oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg
300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
TA = 25oC, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
30
-
-
V
VDS = 25V, VGS = 0V
-
-
1
µA
VDS = 25V, VGS = 0V, TC = 150oC
-
-
250
µA
VGS = ±16V
-
-
±100
nA
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
BVDSS
IDSS
Gate to Source Leakage Current
IGSS
ID = 250µA, VGS = 0V (Figure 12)
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 11)
1
-
3
V
Drain to Source On Resistance
rDS(ON)
ID = 20A, VGS = 10V (Figure 9, 10)
-
0.014
0.016
Ω
ID = 20A, VGS = 5V (Figure 9)
-
0.0175
0.021
Ω
ID = 20A, VGS = 4.5V (Figure 9)
-
0.0195
0.023
Ω
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
RθJC
(Figure 3)
-
-
1.20
oC/W
Thermal Resistance Junction to Ambient
RθJA
TO-251, TO-252
-
-
100
oC/W
tON
VDD = 15V, ID ≅ 20A, RL = 0.75Ω,
VGS = 4.5V, RGS = 10Ω
(Figures 15, 21, 22)
-
-
275
ns
-
20
-
ns
tr
-
165
-
ns
td(OFF)
-
30
-
ns
tf
-
54
-
ns
tOFF
-
-
125
ns
SWITCHING SPECIFICATIONS (VGS = 4.5V)
Turn-On Time
Turn-On Delay Time
td(ON)
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
2
HUF76129D3, HUF76129D3S
TA = 25oC, Unless Otherwise Specified (Continued)
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
-
80
ns
-
7
-
ns
tr
-
47
-
ns
td(OFF)
-
60
-
ns
tf
-
54
-
ns
tOFF
-
-
110
ns
-
38
46
nC
-
22
26
nC
-
1.4
1.7
nC
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
VDD = 15V, ID ≅ 20A, RL = 0.75Ω,
VGS = 10V, RGS = 10Ω
(Figures 16, 21, 22)
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Qg(TOT)
Gate Charge at 5V
Qg(5)
Threshold Gate Charge
Qg(TH)
VGS = 0V to 10V VDD = 15V, ID ≅ 20A,
RL = 0.75Ω
VGS = 0V to 5V
Ig(REF) = 1.0mA
(Figures 14, 19, 20)
V
= 0V to 1V
GS
Gate to Source Gate Charge
Qgs
-
3.70
-
nC
Gate to Drain “Miller” Chatge
Qgd
-
11.20
-
nC
-
1425
-
pF
CAPACITANCE SPECIFICATIONS
VDS = 25V, VGS = 0V, f = 1MHz
(Figure 13)
Input Capacitance
CISS
Output Capacitance
COSS
-
720
-
pF
Reverse Transfer Capacitance
CRSS
-
170
-
pF
MIN
TYP
MAX
UNITS
ISD = 20A
-
-
1.25
V
trr
ISD = 20A, dISD/dt = 100A/µs
-
-
72
ns
QRR
ISD = 20A, dISD/dt = 100A/µs
-
-
107
nC
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Diode Voltage
VSD
Reverse Recovery Time
Reverse Recovered Charge
TEST CONDITIONS
Typical Performance Curves
25
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
0.2
0
20
15
VGS=10V
10
VGS=4.5V
5
0
0
25
50
75
100
125
TA , AMBIENT TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
3
150
25
50
75
100
125
150
TC, CASE TEMPERATURE (oC)
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
HUF76129D3, HUF76129D3S
Typical Performance Curves
(Continued)
2
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-2
10-3
10-1
t, RECTANGULAR PULSE DURATION (s)
100
101
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
2000
IDM, PEAK CURRENT (A)
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 10V
I
150 - TC
= I25
125
100
VGS = 5V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
10-5
10-4
10-3
10-2
t, PULSE WIDTH (s)
10-1
100
101
FIGURE 4. PEAK CURRENT CAPABILITY
TJ = MAX RATED
TC = 25oC
100µs
1ms
10
10ms
1
1
BVDSS MAX = 30V
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
100
100
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
500
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
1000
100
STARTING TJ = 25oC
10
STARTING TJ = 150oC
1
0.01
1
10
0.1
tAV, TIME IN AVALANCHE (ms)
100
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
4
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
HUF76129D3, HUF76129D3S
Typical Performance Curves
(Continued)
60
45
150oC
30
15
45
0
1
2
15
0
3
4
0
1
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
1.6
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
ID = 10A
24
ID = 5A
18
15
12
4
2
6
8
1.4
5
1.2
1.0
0.8
0.6
-80
10
0
-40
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
1.15
1.2
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
VGS = VDS, ID = 250µA
1.1
NORMALIZED GATE
THRESHOLD VOLTAGE
4
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 20A
VGS, GATE TO SOURCE VOLTAGE (V)
1.0
0.9
0.8
0.7
0.6
-80
3
FIGURE 8. SATURATION CHARACTERISTICS
27
21
2
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 7. TRANSFER CHARACTERISTICS
ID = 20A
VGS = 3.5V
VGS = 3V
VGS, GATE TO SOURCE VOLTAGE (V)
30
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
30
VDD = 15V
0
VGS = 10V
VGS = 5V
VGS = 4.5V
VGS = 4V
-55oC
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
60
25oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
5
ID = 250µA
1.10
1.05
1.00
0.95
0.90
-80
-40
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
HUF76129D3, HUF76129D3S
Typical Performance Curves
(Continued)
10
VGS , GATE TO SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
2000
1600
CISS
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
1200
COSS
800
400
CRSS
0
0
10
5
15
20
25
VDD = 15V
8
6
4
2
0
30
WAVEFORMS IN
DESCENDING ORDER:
ID = 20A
ID = 10A
ID = 2A
0
10
VDS , DRAIN TO SOURCE VOLTAGE (V)
20
Qg, GATE CHARGE (nC)
30
40
NOTE: Refer to Intersil Application Notes 7254 and 7260.
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
500
300
VGS = 4.5V, VDD = 15V, ID = 20A, RL= 0.75Ω
VGS = 10V, VDD = 15V, ID = 20A, RL= 0.75Ω
250
tr
SWITCHING TIME (ns)
SWITCHING TIME (ns)
400
300
td(OFF)
tf
200
100
td(OFF)
200
tf
150
100
tr
50
td(ON)
0
0
10
20
30
40
0
50
RGS, GATE TO SOURCE RESISTANCE (Ω)
td(ON)
0
10
20
30
40
50
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
Test Circuits and Waveforms
VDS
BVDSS
L
VARY tP TO OBTAIN
REQUIRED PEAK IAS
tP
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
0V
tP
IAS
0
0.01Ω
tAV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
6
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
HUF76129D3, HUF76129D3S
Test Circuits and Waveforms
(Continued)
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 10
VGS
Qg(5)
+
VDD
VGS = 5V
VGS
DUT
VGS = 1V
Ig(REF)
0
Qg(TH)
Ig(REF)
0
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
VDS
tON
tOFF
td(ON)
td(OFF)
tf
tr
RL
VDS
90%
90%
+
VGS
-
VDD
10%
0
10%
DUT
90%
RGS
VGS
VGS
0
FIGURE 21. SWITCHING TIME TEST CIRCUIT
7
10%
50%
50%
PULSE WIDTH
FIGURE 22. SWITCHING TIME WAVEFORM
HUF76129D3, HUF76129D3S
PSPICE Electrical Model
SUBCKT HUF76129D 2 1 3 ;
REV April 1998
CA 12 8 1.95e-9
CB 15 14 1.85e-9
CIN 6 8 1.31e-9
LDRAIN
DPLCAP
DRAIN
2
5
10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
DBREAK
+
RSLC2
5
51
ESLC
11
-
EBREAK 11 7 17 18 32
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
LGATE
GATE
1
EVTEMP
RGATE +
18 22
9
20
21
DBODY
-
16
MWEAK
6
MMED
MSTRO
RLGATE
LDRAIN 2 5 1e-9
LGATE 1 9 2.20e-9
LSOURCE 3 7 3.03e-9
+
17
EBREAK 18
50
-
IT 8 17 1
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RLSOURCE
S1A
12
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1.9e-3
RGATE 9 20 3.6e-1
RLDRAIN 2 5 10
RLGATE 1 9 22
RLSOURCE 3 7 30.3
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 10e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
RLDRAIN
RSLC1
51
S2A
14
13
13
8
S1B
CA
RBREAK
15
17
18
RVTEMP
S2B
13
CB
6
8
-
-
IT
14
+
+
EGS
19
VBAT
5
8
EDS
-
+
8
22
RVTHRES
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*1000),3.5))}
.MODEL DBODYMOD D (IS = 1.2e-12 IKF = 8 TIKF = 1e-2 RS = 7.7e-3 TRS1 = 3e-4 TRS2 = 1e-6 CJO = 2.23e-9 TT = 35e-9 M = 4e-1 XTI =4.75 )
.MODEL DBREAKMOD D (RS = 9.5e-2 TRS1 = 4e-3 TRS2 = 3e-5 IKF = 1e-1)
.MODEL DPLCAPMOD D (CJO = 1.12e-10 IS = 1e-30 N = 10 M = 6.5e-1 VJ = 1.45)
.MODEL MMEDMOD NMOS (VTO = 1.87 KP = 5.75 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1)
.MODEL MSTROMOD NMOS (VTO = 2.15 KP = 90 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.49 KP =2e-2 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 10)
.MODEL RBREAKMOD RES (TC1 = 9.8e-4 TC2 = -1e-10)
.MODEL RDRAINMOD RES (TC1 = 1e-2 TC2 = 1e-5)
.MODEL RSLCMOD RES (TC1 = 1e-6 TC2 = 1.05e-6)
.MODEL RSOURCEMOD RES (TC1 = 2.5e-3 TC2 = 2e-6)
.MODEL RVTHRESMOD RES (TC1 = -1.8e-3 TC2 = -1.1e-5)
.MODEL RVTEMPMOD RES (TC1 = -1.65e-3 TC2 = 1.45e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -10.0 VOFF= -0.50)
VON = -0.50 VOFF= -10.0)
VON = 0.00 VOFF= 0.50)
VON = 0.50 VOFF= 0.00)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
8
HUF76129D3, HUF76129D3S
SABER Electrical Model
nom temp=25 deg c
30v LL Ultrafet
REV April 1998
template huf76129D n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is=1.2e-12, xti=4.75, cjo=2.23e-9,tt=35e-8, m=4e-1)
d..model dbreakmod = (is=1e-14)
d..model dplcapmod = (cjo=1.12e-9,is=1e-30,n=10,m=6.5e-1, vj=1.45, fc=5e-1)
m..model mmedmod = (type=_n,vto=1.87,kp=5.75,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=2.15,kp=90,is=1e-30, tox=1)
DPLCAP
m..model mweakmod = (type=_n,vto=1.49,kp=2e-2,is=1e-30, tox=1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-10.0,voff=-0.5)
10
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-0.5,voff=10.0)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=0,voff=0.5)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.5,voff=0)
LDRAIN
DRAIN
2
5
RLDRAIN
RSLC1
51
RDBREAK
RSLC2
c.ca n12 n8 = 1.95e-9
c.cb n15 n14 = 1.85e-9
c.cin n6 n8 = 1.31e-9
72
ISCL
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
GATE
1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 2.2e-9
l.lsource n3 n7 = 3.03e-9
EVTHRES
+ 19 8
+
LGATE
i.it n8 n17 = 1
RDRAIN
6
8
ESG
EVTEMP
RGATE +
18 22
9
20
21
MWEAK
DBODY
EBREAK
+
17
18
MMED
MSTRO
CIN
-
8
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
LSOURCE
SOURCE
3
7
RSOURCE
RLSOURCE
S1A
12
S2A
13
8
S1B
CA
RBREAK
15
14
13
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/1000))** 3.5 ))
}
}
VBAT
5
8
EDS
-
-
IT
14
+
+
spe.ebreak n11 n7 n17 n18 = 37
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
9
71
11
16
6
RLGATE
res.rbreak n17 n18 = 1, tc1=9.8e-4,tc2=-1e-10
res.rdbody n71 n5 =7.7e-3, tc1=2.5e-3, tc2=1e-6
res.rdbreak n72 n5 =9.5e-2, tc1=4e-3, tc2=3e-5
res.rdrain n50 n16 = 1.9e-3, tc1=1e-2,tc2=1e-5
res.rgate n9 n20 = 3.6e-1
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 22
res.rlsource n3 n7 = 30.3
res.rslc1 n5 n51 = 1e-6, tc1=1e-6,tc2=-1.05e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 10e-3, tc1=2.5e-3,tc2=2e-6
res.rvtemp n18 n19 = 1, tc1=-1.8e-3,tc2=1.1e-5
res.rvthres n22 n8 = 1, tc1=-1.65e-3,tc2=-1.45e-6
DBREAK
50
-
RDBODY
-
+
8
22
RVTHRES
HUF76129D3, HUF76129D3S
SPICE Thermal Model
th
JUNCTION
REV April 1998
HUF76129D
CTHERM1 th 6 1.10e-5
CTHERM2 6 5 2.70e-2
CTHERM3 5 4 3.90e-2
CTHERM4 4 3 1.00e-2
CTHERM5 3 2 2.30e-2
CTHERM6 2 tl 1.80
RTHERM1
RTHERM1 th 6 1.00e-4
RTHERM2 6 5 5.00e-4
RTHERM3 5 4 2.90e-2
RTHERM4 4 3 4.80e-1
RTHERM5 3 2 2.80e-1
RTHERM6 2 tl 1.00e-1
RTHERM2
CTHERM1
6
CTHERM2
5
RTHERM3
CTHERM3
SABER Thermal Model
Saber thermal model HUF76129D
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th c2 = 1.10e-5
ctherm.ctherm2 c2 c3 = 2.70e-2
ctherm.ctherm3 c3 c4 = 3.90e-2
ctherm.ctherm4 c4 c5 = 1.00e-2
ctherm.ctherm5 c5 c6 = 2.30e-2
ctherm.ctherm6 c6 tl = 1.80
4
RTHERM4
CTHERM4
3
RTHERM5
rtherm.rtherm1 th c2 = 1.00e-4
rtherm.rtherm2 c2 c3 = 5.00e-4
rtherm.rtherm3 c3 c4 = 2.90e-2
rtherm.rtherm4 c4 c5 = 4.80e-1
rtherm.rtherm5 c5 c6 = 2.80e-1
rtherm.rtherm6 c6 tl = 1.00e-1
}
CTHERM5
2
RTHERM6
CTHERM6
tl
CASE
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