HUF76429D3, HUF76429D3S
Data Sheet
October 1999
File Number
4671.1
20A, 60V, 0.027 Ohm, N-Channel, Logic
Level UltraFET® Power MOSFET
Title
UF7
29D
Packaging
JEDEC TO-251AA
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
UF76
9D3
bjec
0A,
V,
27
m,
JEDEC TO-252AA
GATE
SOURCE
DRAIN
(FLANGE)
HUF76429D3
HUF76429D3S
D
gic
vel
raF
ann
gic
vel
raF
• Peak Current vs Pulse Width Curve
Ordering Information
PART NUMBER
G
S
rpor
on,
• Simulation Models
- Temperature Compensated PSPICE® and SABER™
Electriecal Models
- Spice and SABER Thermal Impedance Models
- www.intersil.com
• Switching Time vs RGS Curves
ann
eyw
s
tersi
• Ultra Low On-Resistance
- rDS(ON) = 0.023Ω, VGS = 10V
- rDS(ON) = 0.027Ω, VGS = 5V
• UIS Rating Curve
Symbol
wer
OSF
)
utho
Features
Absolute Maximum Ratings
PACKAGE
BRAND
HUF76429D3
TO-251AA
76429D
HUF76429D3S
TO-252AA
76429D
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF76429D3ST.
TC = 25oC, Unless Otherwise Specified
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
Continuous (TC= 25oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC= 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC= 100oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC= 100oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UIS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
Package Body for 10s, See Techbrief TB334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
HUF76429D3, HUF76429D3S
60
UNITS
V
60
±16
V
V
20
20
20
20
Figure 4
Figures 6, 17, 18
A
A
A
A
110
0.74
-55 to 175
W
W/oC
oC
300
260
oC
oC
NOTES:
1. TJ = 25oC to 150oC.
wer
OSF
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Product reliability information can be found at http://www.mtp.intersil.com/reliability.html
For severe environments, see our Automotive HUFA series.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2001 Fairchild Semiconductor Corporation
HUF76429D3, HUF76429D3S Rev. A
HUF76429D3, HUF76429D3S
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ID = 250µA, VGS = 0V (Figure 12)
60
-
-
V
ID = 250µA, VGS = 0V , TC = -40oC (Figure 12)
55
-
-
V
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
BVDSS
IDSS
IGSS
VDS = 55V, VGS = 0V
-
-
1
µA
VDS = 50V, VGS = 0V, TC = 150oC
-
-
250
µA
VGS = ±16V
-
-
±100
nA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 11)
1
-
3
V
Drain to Source On Resistance
rDS(ON)
ID = 20A, VGS = 10V (Figures 9, 10)
-
0.0205
0.023
Ω
ID = 20A, VGS = 5V (Figure 9)
-
0.024
0.027
Ω
ID = 20A, VGS = 4.5V (Figure 9)
-
0.025
0.029
Ω
TO-251 and TO-252
-
-
1.36
oC/W
-
-
100
oC/W
-
-
220
ns
-
13
-
ns
ns
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
RθJC
Thermal Resistance Junction to
Ambient
RθJA
SWITCHING SPECIFICATIONS (VGS = 4.5V)
Turn-On Time
Turn-On Delay Time
tON
td(ON)
Rise Time
Turn-Off Delay Time
tr
-
134
-
td(OFF)
-
30
-
ns
tf
-
55
-
ns
tOFF
-
-
130
ns
-
-
65
ns
-
7.7
-
ns
Fall Time
Turn-Off Time
VDD = 30V, ID = 20A
VGS = 4.5V, RGS = 7.5Ω
(Figures 15, 21, 22)
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
tON
td(ON)
VDD = 30V, ID = 20A
VGS = 10V,RGS = 8.2Ω
(Figures 16, 21, 22)
tr
-
36
-
ns
td(OFF)
-
60
-
ns
tf
-
56
-
ns
tOFF
-
-
175
ns
-
38
46
nC
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Gate Charge at 5V
Threshold Gate Charge
Qg(TOT)
VGS = 0V to 10V
Qg(5)
VGS = 0V to 5V
Qg(TH)
VGS = 0V to 1V
VDD = 30V,
ID = 20A,
Ig(REF) = 1.0mA
(Figures 14, 19, 20)
-
21
25
nC
-
1.3
1.6
nC
Gate to Source Gate Charge
Qgs
-
3.8
-
nC
Gate to Drain "Miller" Charge
Qgd
-
9.7
-
nC
CAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 13)
-
1480
-
pF
-
440
-
pF
-
90
-
pF
MIN
TYP
MAX
UNITS
V
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
©2001 Fairchild Semiconductor Corporation
SYMBOL
TEST CONDITIONS
ISD = 20A
-
-
1.25
ISD = 10A
-
-
1.00
V
trr
ISD = 20A, dISD/dt = 100A/µs
-
-
80
ns
QRR
ISD = 20A, dISD/dt = 100A/µs
-
-
230
nC
VSD
HUF76429D3, HUF76429D3S Rev. A
HUF76429D3, HUF76429D3S
Typical Performance Curves
25
VGS = 10V
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
20
15
VGS = 4.5V
10
5
0.2
0
0
0
25
50
75
100
150
125
25
175
50
75
100
125
150
175
TC, CASE TEMPERATURE (oC)
TC , CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
IDM, PEAK CURRENT (A)
600
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 10V
175 - TC
I = I25
100
150
VGS = 5V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
10-5
10-4
10-3
10-2
10-1
100
101
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
©2001 Fairchild Semiconductor Corporation
HUF76429D3, HUF76429D3S Rev. A
HUF76429D3, HUF76429D3S
Typical Performance Curves
(Continued)
100
100
100µs
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
10
1ms
SINGLE PULSE
TJ = MAX RATED
TC = 25oC
1
STARTING TJ = 25oC
STARTING TJ = 150oC
10ms
10
0.01
1
10
50
ID, DRAIN CURRENT (A)
VGS = 10V
30
20
TJ= 175oC
TJ= -55oC
10
VGS = 5V
VGS = 4V
40
VGS = 3.5V
30
20
VGS = 3V
10
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
TJ= 25oC
0
0
1.5
2
2.5
3
3.5
VGS, GATE TO SOURCE VOLTAGE (V)
0
4
FIGURE 7. TRANSFER CHARACTERISTICS
1
2
3
VDS, DRAIN TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
30
ID = 10A
20
10
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
2.5
ID = 20A
4
FIGURE 8. SATURATION CHARACTERISTICS
40
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
10
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
40
1
tAV, TIME IN AVALANCHE (ms)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
50
0.1
100
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
300
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 20A
2.0
1.5
1.0
0.5
2
4
6
8
VGS, GATE TO SOURCE VOLTAGE (V)
10
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
©2001 Fairchild Semiconductor Corporation
-80
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
160
200
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
HUF76429D3, HUF76429D3S Rev. A
HUF76429D3, HUF76429D3S
Typical Performance Curves
(Continued)
1.2
1.2
1.0
0.8
0.6
0.4
-80
ID = 250µA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
NORMALIZED GATE
THRESHOLD VOLTAGE
VGS = VDS, ID = 250µA
1.1
1.0
0.9
-40
0
40
80
120
160
200
-80
-40
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
40
80
120
160
200
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
10
3000
VGS , GATE TO SOURCE VOLTAGE (V)
VGS = 0V, f = 1MHz
C, CAPACITANCE (pF)
0
TJ , JUNCTION TEMPERATURE (oC)
CISS = CGS + CGD
1000
COSS ≅ CDS + CGD
100
CRSS = CGD
VDD = 30V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 20A
ID = 10A
2
0
30
0.1
1.0
10
0
60
VDS , DRAIN TO SOURCE VOLTAGE (V)
5
10
15
25
20
Qg, GATE CHARGE (nC)
35
30
40
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
300
400
VGS = 10V, VDD = 30V, ID = 20A
VGS = 4.5V, VDD = 30V, ID = 20A
SWITCHING TIME (ns)
SWITCHING TIME (ns)
250
300
tr
200
tf
td(OFF)
100
200
td(OFF)
tf
150
100
tr
50
td(ON)
td(ON)
0
0
0
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
©2001 Fairchild Semiconductor Corporation
50
0
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
50
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
HUF76429D3, HUF76429D3S Rev. A
HUF76429D3, HUF76429D3S
Test Circuits and Waveforms
VDS
BVDSS
L
tP
VARY tP TO OBTAIN
REQUIRED PEAK IAS
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
tP
0V
IAS
0
0.01Ω
tAV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 10V
VGS
Qg(5)
+
VDD
VGS = 5V
VGS
DUT
VGS = 1V
Ig(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
VDS
tON
tOFF
td(ON)
td(OFF)
tr
RL
VDS
tf
90%
90%
+
VGS
VDD
-
10%
0
10%
DUT
90%
RGS
VGS
VGS
0
FIGURE 21. SWITCHING TIME TEST CIRCUIT
©2001 Fairchild Semiconductor Corporation
10%
50%
50%
PULSE WIDTH
FIGURE 22. SWITCHING TIME WAVEFORM
HUF76429D3, HUF76429D3S Rev. A
HUF76429D3, HUF76429D3S
PSPICE Electrical Model
.SUBCKT HUF76429D3 2 1 3 ;
rev 5 July 1999
CA 12 8 2.03e-9
CB 15 14 2.03e-9
CIN 6 8 1.39e-9
LDRAIN
DPLCAP
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
10
DBREAK
+
RSLC2
5
51
ESLC
11
-
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
LGATE
GATE
1
+
17
EBREAK 18
50
-
IT 8 17 1
EVTEMP
RGATE +
18 22
9
20
21
DBODY
-
16
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
8
SOURCE
3
7
RSOURCE
RLSOURCE
S1A
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 9.1e-3
RGATE 9 20 2.80
RLDRAIN 2 5 10
RLGATE 1 9 54.2
RLSOURCE 3 7 41.6
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 6.5e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
RLDRAIN
RSLC1
51
EBREAK 11 7 17 18 68.10
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
LDRAIN 2 5 1e-9
LGATE 1 9 5.42e-9
LSOURCE 3 7 4.16e-9
DRAIN
2
5
12
S2A
14
13
13
8
S1B
17
18
RVTEMP
S2B
13
CA
RBREAK
15
CB
6
8
EGS
19
-
-
IT
14
+
+
VBAT
5
8
EDS
-
+
8
22
RVTHRES
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*117),3))}
.MODEL DBODYMOD D (IS = 1.25e-12 IKF = 10 RS = 8.40e-3 TRS1 = 2.05e-3 TRS2 = 3.85e-6 CJO = 1.68e-9 TT = 4.90e-8 M = 0.48 XTI = 4.35)
.MODEL DBREAKMOD D (RS = 1.68e-1 TRS1 = 1e-3 TRS2 = -1e-6)
.MODEL DPLCAPMOD D (CJO = 1.28e-9 IS = 1e-30 N = 10 M = 0.8)
.MODEL MMEDMOD NMOS (VTO = 1.98 KP = 3.2 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.80)
.MODEL MSTROMOD NMOS (VTO = 2.30 KP = 52 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.72 KP = 0.08 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 28.0 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.15e-3 TC2 = -5.40e-7)
.MODEL RDRAINMOD RES (TC1 = 7.85e-3 TC2 = 1.95e-5)
.MODEL RSLCMOD RES (TC1 = 4.97e-3 TC2 = 5.05e-6)
.MODEL RSOURCEMOD RES (TC1 = 1.5e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -1.85e-3 TC2 = -4.48e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.92e-3 TC2 = 9.50e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -6.2 VOFF= -2.4)
VON = -2.4 VOFF= -6.2)
VON = -1.1 VOFF= 0.5)
VON = 0.5 VOFF= -1.1)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2001 Fairchild Semiconductor Corporation
HUF76429D3, HUF76429D3S Rev. A
HUF76429D3, HUF76429D3S
SABER Electrical Model
REV 5 July 1999
template huf76429d3 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 1.25e-12, cjo = 1.68e-9, tt = 4.90e-8, xti = 4.35, m = 0.48)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 1.28e-9, is = 1e-30, n = 10, m = 0.8)
m..model mmedmod = (type=_n, vto = 1.98, kp = 3.2, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.30, kp = 52, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.72, kp = 0.08, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.2, voff = -2.4)
DPLCAP
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.4, voff = -6.2)
10
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.1, voff = 0.5)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -1.1)
c.ca n12 n8 = 2.03e-9
c.cb n15 n14 = 2.03e-9
c.cin n6 n8 = 1.39e-9
DRAIN
2
RSLC1
51
RLDRAIN
RDBREAK
RSLC2
72
ISCL
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
i.it n8 n17 = 1
LGATE
GATE
1
EVTEMP
RGATE + 18 22
9
20
MWEAK
MSTRO
CIN
DBODY
EBREAK
+
17
18
MMED
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
71
11
16
6
RLGATE
res.rbreak n17 n18 = 1, tc1 = 1.15e-3, tc2 = -5.40e-7
res.rdbody n71 n5 = 8.40e-3, tc1 = 2.05e-3, tc2 = 3.85e-6
res.rdbreak n72 n5 = 1.68e-1, tc1 = 1.00e-3, tc2 = -1.00e-6
res.rdrain n50 n16 = 9.10e-3, tc1 = 7.85e-3, tc2 = 1.95e-5
res.rgate n9 n20 = 2.80
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 54.2
res.rlsource n3 n7 = 41.6
res.rslc1 n5 n51 = 1e-6, tc1 = 4.97e-3, tc2 = 5.05e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 6.5e-3, tc1 = 1.5e-3, tc2 = 1e-6
res.rvtemp n18 n19 = 1, tc1 = -1.92e-3, tc2 = 9.50e-7
res.rvthres n22 n8 = 1, tc1 = -1.85e-3, tc2 = -4.48e-6
21
RDBODY
DBREAK
50
-
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 5.42e-9
l.lsource n3 n7 = 4.16e-9
LDRAIN
5
-
8
LSOURCE
7
SOURCE
3
RSOURCE
RLSOURCE
S1A
12
S2A
13
8
14
13
S1B
CA
RBREAK
15
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
-
-
IT
14
+
+
VBAT
5
8
EDS
-
+
8
22
RVTHRES
spe.ebreak n11 n7 n17 n18 = 68.10
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/117))** 3))
}
}
©2001 Fairchild Semiconductor Corporation
HUF76429D3, HUF76429D3S Rev. A
HUF76429D3, HUF76429D3S
SPICE Thermal Model
th
JUNCTION
REV 26 July 1999
HUF76429D3
CTHERM1 th 6 2.45e-3
CTHERM2 6 5 8.15e-3
CTHERM3 5 4 7.40e-3
CTHERM4 4 3 7.45e-3
CTHERM5 3 2 1.01e-2
CTHERM6 2 tl 7.49e-2
RTHERM1
CTHERM1
6
CTHERM2
RTHERM2
RTHERM1 th 6 9.00e-3
RTHERM2 6 5 1.80e-2
RTHERM3 5 4 9.15e-2
RTHERM4 4 3 2.43e-1
RTHERM5 3 2 3.50e-1
RTHERM6 2 tl 3.62e-1
5
RTHERM3
CTHERM3
SABER Thermal Model
4
SABER thermal model HUF76429D3
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 2.45e-3
ctherm.ctherm2 6 5 = 8.15e-3
ctherm.ctherm3 5 4 = 7.40e-3
ctherm.ctherm4 4 3 = 7.45e-3
ctherm.ctherm5 3 2 = 1.01e-2
ctherm.ctherm6 2 tl = 7.49e-2
rtherm.rtherm1 th 6 = 9.00e-3
rtherm.rtherm2 6 5 = 1.80e-2
rtherm.rtherm3 5 4 = 9.15e-2
rtherm.rtherm4 4 3 = 2.43e-1
rtherm.rtherm5 3 2 = 3.50e-1
rtherm.rtherm6 2 tl = 3.62e-1
}
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
©2001 Fairchild Semiconductor Corporation
CASE
HUF76429D3, HUF76429D3S Rev. A
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Rev. H