CD4071BMS, CD4072BMS CD4075BMS CMOS OR Gate December 1992 Features Pinout • High-Voltage Types (20V Rating) CD4071BMS TOP VIEW • CD4071BMS Quad 2-Input OR Gate • CD4072BMS Dual 4-Input OR Gate A 1 14 VDD B 2 13 H J=A+B 3 12 G K=C+C 4 11 M = G + H • CD4075BMS Triple 3-Input OR Gate • Medium Speed Operation: - tPHL, tPLH = 60ns (typ) at 10V • 100% Tested for Quiescent Current at 20V • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC • Standardized Symmetrical Output Characteristics C 5 10 L = E + F D 6 9 F VSS 7 8 E • Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • 5V, 10V and 15V Parametric Ratings CD4072BMS TOP VIEW J=A+B+C+D 1 • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Description CD4071BMS, CD4072BMS and CD4075BMS OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates. A 2 13 K = E +F + G + H B 3 12 H C 4 11 G D 5 10 F NC 6 9 E *H4H Frit Seal DIP H1B Ceramic Flatpack H3W *CD4071, CD4072 †CD4075 Only 8 NC VSS 7 NC = NO CONNECTION The CD4071BMS, CD4072BMS and CD4075BMS are supplied in these 14 lead outline packages: Braze Seal DIP 14 VDD CD4075BMS TOP VIEW †H4Q A 1 14 VDD B 2 13 G D 3 12 H E 4 11 I F 5 10 L = G + H + I K=D+E+F 6 VSS 7 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-444 9 J=A+B+C 8 C File Number 3323 CD4071BMS, CD4072BMS, CD4075BMS Functional Diagram VDD 14 1 2 3 5 6 4 8 9 10 12 13 11 B A D C F E H G J K L M 7 VSS CD4071BMS VDD 14 A B C D 2 3 1 4 5 9 E 10 F 11 G 12 H 13 J K 7 VSS CD4072BMS VDD 14 C B A F 1 9 2 4 6 5 D 11 I 12 H 13 G 10 E J 8 3 7 VSS CD4075BMS 7-445 K L Specifications CD4071BMS, CD4072BMS, CD4075BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND Input Leakage Current Input Leakage Current IIL IIH VIN = VDD or GND VIN = VDD or GND LIMITS GROUP A SUBGROUPS TEMPERATURE MIN MAX 1 +25oC - 0.5 µA 2 +125oC - 50 µA 3 -55oC - 0.5 µA UNITS 1 +25o C -100 - nA 2 +125oC -1000 - nA VDD = 18V 3 -55oC -100 - nA VDD = 20 1 +25oC - 100 nA 2 +125oC - 1000 nA 3 -55oC - 100 nA - 50 mV - V VDD = 20 VDD = 18V Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V 0.7 2.8 V P Threshold Voltage Functional VPTH F VSS = 0V, IDD = 10µA 1 +25oC VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 7-446 V -55oC +25oC, NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. VOH > VOL < VDD/2 VDD/2 +125oC, -55oC - 1.5 V +25oC, +125oC, -55oC 3.5 - V 1, 2, 3 +25oC, +125oC, -55oC - 4 V 1, 2, 3 +25oC, +125oC, -55oC 11 - V 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. Specifications CD4071BMS, CD4072BMS, CD4075BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Propagation Delay Transition Time SYMBOL TPHL TPLH CONDITIONS (NOTES 1, 2) GROUP A SUBGROUPS TEMPERATURE VDD = 5V, VIN = VDD or GND 9 10, 11 TTHL TTLH VDD = 5V, VIN = VDD or GND 9 10, 11 +25oC +125oC, -55oC +25oC +125oC, -55oC LIMITS MIN MAX UNITS - 250 ns - 338 ns - 200 ns - 270 ns NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC - 0.25 µA - 7.5 µA -55 C, +25 C - 0.5 µA +125oC - 15 µA - 0.5 µA o +125 C VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND 1, 2 1, 2 o -55oC, o +25oC - 30 µA Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA -55oC 0.64 - mA +125oC 0.9 - mA -55oC 1.6 - mA oC +125 Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VDD = 10V, VOUT = 0.5V 1, 2 VDD = 15V, VOUT = 1.5V 1, 2 VDD = 5V, VOUT = 4.6V 1, 2 VDD = 5V, VOUT = 2.5V 1, 2 VDD = 10V, VOUT = 9.5V 1, 2 VDD =15V, VOUT = 13.5V 1, 2 +125oC 2.4 - mA -55oC 4.2 - mA +125oC - -0.36 mA -55oC - -0.64 mA +125oC - -1.15 mA -55oC - -2.0 mA +125oC - -0.9 mA -55oC - -2.6 mA +125oC - -2.4 mA -55oC - -4.2 mA Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC - 3 V Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC 7 - V Propagation Delay TPHL TPLH 1, 2, 3 +25oC - 120 ns 1, 2, 3 +25oC - 90 ns VDD = 10V VDD = 15V 7-447 Specifications CD4071BMS, CD4072BMS, CD4075BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL Transition Time TTHL TTLH Input Capacitance CONDITIONS VDD = 10V VDD = 15V CIN Any Input NOTES TEMPERATURE MIN MAX UNITS 1, 2, 3 +25oC - 100 ns o 1, 2, 3 +25 C - 80 ns 1, 2 +25oC - 7.5 pF NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER SYMBOL Supply Current IDD N Threshold Voltage VNTH N Threshold Voltage Delta ∆VTN P Threshold Voltage VTP P Threshold Voltage Delta ∆VTP Functional F CONDITIONS NOTES TEMPERATURE UNITS +25 C - 2.5 µA 1, 4 +25oC -2.8 -0.2 V VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V 1, 4 +25oC - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND TPHL TPLH MAX 1, 4 VDD = 20V, VIN = VDD or GND o VDD = 3V, VIN = VDD or GND Propagation Delay Time MIN VDD = 5V 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER SYMBOL DELTA LIMIT Supply Current - SSI IDD ±0.1µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading IOH5A ± 20% x Pre-Test Reading Output Current (Source) TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas 100% 5004 1, 7, 9 100% 5004 1, 7, 9, Deltas 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A 7-448 READ AND RECORD IDD, IOL5, IOH5A Specifications CD4071BMS, CD4072BMS, CD4075BMS TABLE 6. APPLICABLE SUBGROUPS (Continued) MIL-STD-883 METHOD GROUP A SUBGROUPS Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 CONFORMANCE GROUP Group B Group D READ AND RECORD Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD 9V ± -0.5V 50kHz 3, 4, 10, 11 1, 2, 5, 6, 8, 9, 12, 13 1, 13 2 - 5, 9 - 12 6, 9, 10 1 - 5, 8, 11 - 13 25kHz PART NUMBER CD4071BMS Static Burn-In 1 Note 1 3, 4, 10, 11 1, 2, 5 - 9, 12 - 13 14 Static Burn-In 2 Note 1 3, 4, 10, 11 7 1, 2, 5, 6, 8, 9, 12 - 14 Dynamic BurnIn Note 1 - 7 14 3, 4, 10, 11 7 1, 2, 5, 6, 8, 9, 12 - 14 Irradiation Note 2 PART NUMBER CD4072BMS Static Burn-In 1 Note 1 1, 6, 8, 13 2 - 5, 7, 9 - 12 14 Static Burn-In 2 Note 1 1, 6, 8, 13 7 2 - 5, 9 - 12, 14 Dynamic BurnIn Note 1 6, 8 7 14 1, 6, 8, 13 7 2 - 5, 9 - 12, 14 Irradiation Note 2 PART NUMBER CD4075BMS Static Burn-In 1 Note 1 6, 9, 10 1 - 5, 7, 8, 11 - 13 14 Static Burn-In 2 Note 1 6, 9, 10 7 1 - 5, 8, 11 - 14 Dynamic BurnIn Note 1 - 7 14 6, 9, 10 7 1 - 5, 8, 11 - 14 Irradiation Note 2 NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V 7-449 CD4071BMS, CD4072BMS, CD4075BMS VDD 14 p p p p n n n p * 1 (6, 8, 13) n n p * 2 (5,9, 12) VDD 3 (4, 10, 11) VSS * n 7 ALL INPUTS PROTECTED BY CMOS PROTECTION NETWORK VSS FIGURE 1. SCHEMATIC DIAGRAM FOR CD4071BMS (1 OF 4 IDENTICAL GATES) B 1 (6, 8, 13) J A 3 (4, 10, 11) 2 (5, 9, 12) FIGURE 2. LOGIC DIAGRAM FOR CD4071BMS (1 OF 4 IDENTICAL GATES) VDD INV.1** p VDD p p VDD VDD n p p * p 2 (12) 1 (13) n n n n VSS VSS VDD p * 3 (11) n VSS VSS p INV 2** VDD n * INV 3** 5 (9) n * 4 (10) VSS INV 4** VSS ** INVERTERS 2, 3 AND 4 ARE IDENTICAL TO INVERTER 1. * ALL INPUTS PROTECTED BY CMOS PROTECTION NETWORK FIGURE 3. SCHEMATIC DIAGRAM FOR CD4072BMS (1 OF 2 IDENTICAL GATES) A 2 (12) B 3 (11) J D 1 (13) 5 (9) C 4 (10) FIGURE 4. LOGIC DIAGRAM FOR CD4072BMS (1 OF 2 IDENTICAL GATES) 7-450 CD4071BMS, CD4072BMS, CD4075BMS VDD 14 p p p n p p n n p 9 (6, 10) * n 8 (5, 13) n p n * 2 (4, 12) n VDD p n * 1 (3, 11) n VSS * 7 VSS ALL INPUTS PROTECTED BY CMOS PROTECTION NETWORK FIGURE 5. SCHEMATIC DIAGRAM FOR CD4075BMS (1 OF 3 IDENTICAL GATES) A 1 (3, 11) J B 2 (4, 12) 9 (6, 10) C 8 (5, 13) FIGURE 6. LOGIC DIAGRAM FOR CD4075BMS (1 OF 3 IDENTICAL GATES) OUTPUT VOLTAGE (VO) (V) 20 PROPAGATION DELAY TIME (tPHL, tPLH) (ns) Typical Performance Characteristics AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD) = 15V 15 10V 10 5V 5 0 5 10 15 INPUT VOLTAGE (VIN) (V) 200 AMBIENT TEMPERATURE (TA) = +25oC 150 SUPPLY VOLTAGE (VDD) = 5V 100 50 10V 15V 0 20 20 40 60 80 LOAD CAPACITANCE (CL) (pF) FIGURE 7. TYPICAL VOLTAGE TRANSFER CHARACTERISTICS FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE 7-451 CD4071BMS, CD4072BMS, CD4075BMS (Continued) 30 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 AMBIENT TEMPERATURE (TA) = +25oC 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 10V 7.5 5.0 2.5 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 9. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS FIGURE 10. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0 -5 -10 -15 -10V -20 -25 -15V -30 FIGURE 11. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS -5 -10V POWER DISSIPATION PER GATE (PD) (µW) TRANSITION TIME (tTHL, tTLH) (ns) -15 FIGURE 12. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA) = +25 C 200 SUPPLY VOLTAGE (VDD) = 5V 100 10V 0 0 -10 -15V 105 15V 50 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V o 150 0 AMBIENT TEMPERATURE (TA) = +25oC OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) Typical Performance Characteristics 8 6 4 AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD) = 15V 2 104 10V 8 6 4 103 10V 5V 2 8 6 4 2 102 8 6 4 CL = 50pF 2 CL = 15pF 10 20 2 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 13. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE 1 4 68 2 4 6 8 2 4 6 8 103 10 102 INPUT FREQUENCY (fI) (kHz) 2 4 6 8 104 FIGURE 14. TYPICAL DYNAMIC POWER DISSIPATIONAS A FUNCTION OF FREQUENCY 7-452 CD4071BMS, CD4072BMS, CD4075BMS Chip Dimensions and Pad Layouts CD4071BMS CD4072BMS CD4075BMS Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch) METALLIZATION: PASSIVATION: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 453