INTERSIL ISL59482IRZ

ISL59482
®
Data Sheet
December 22, 2006
Dual, 500MHz Triple, Multiplexing
Amplifiers
Features
The ISL59482 contains two independent fixed gain of 2 triple
4:1 MUX amplifiers that feature high slew rate and excellent
bandwidth for RGB video switching. Each RGB 4:1 MUX
contains binary coded, channel select logic inputs (S0, S1),
and separate logic inputs for High Impedance Output (HIZ)
and power-down (EN) modes. The HIZ state presents a high
impedance at the output so that both RGB MUX outputs can
be wired together to form an 8:1 RGB MUX amplifier or, they
can be used in R-R, G-G, and B-B pairs to form a 4:1
differential input/output MUX. Separate power-down mode
controls (EN1, EN2,) are included to turn off unneeded
circuitry in power sensitive applications. With both EN pins
pulled high, the ISL59482 enters a standby power modeconsuming just 34mW.
• 520MHz Bandwidth into 500Ω Load
FN6209.2
• Dual, Triple 4:1 Multiplexers for RGB
• ±1600 V/µs Slew Rate
• Externally Configurable for Various Video MUX Circuits
Including:
- 8:1 RGB MUX
- Two Separate 4:1 RGB MUX
- 4:1 Differential RGB Video MUX
• Internally Fixed Gain-of-2
• High Impedance Outputs (HIZ)
• Power-Down Mode (EN)
• ±5V Operation
• Supply Current 16mA/Ch maximum
TABLE 1. CHANNEL SELECT LOGIC TABLE ISL59482
S1-1, 2
S0-1, 2
EN1, 2
HIZ1, 2
OUTPUT1, 2
• Pb-free Plus Anneal Available (RoHS Compliant)
0
0
0
0
IN0 (A, B, C)
Applications
0
1
0
0
IN1 (A, B, C)
1
0
0
0
IN2 (A, B, C)
1
1
0
0
IN3 (A, B, C)
X
X
1
X
Power-down
X
X
0
1
High Z
• HDTV/DTV analog inputs
• Video projectors, Computer monitors
• Set-top boxes
• Security video
• Broadcast video equipment
Ordering Information
PART NUMBER
(Note)
PART MARKING
TAPE &
REEL
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL59482IRZ
ISL59482 IRZ
-
48 Ld Exposed Pad 7x7 QFN
L48.7x7B
ISL59482IRZ-T13
ISL59482 IRZ
13”
48 Ld Exposed Pad 7x7 QFN
L48.7x7B
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2006. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL59482
Pinout
37 IN1B1
38 INIC1
39 GND
40 IN2A1
41 IN2B1
42 IN2C1
43 GND
44 IN3A1
45 IN3B1
46 IN3C1
47 S1-1
48 S0-1
ISL59482
(48 LD QFN)
TOP VIEW
+2
OUTC1 1
36 IN2A2
0
OUTB1 2
35 GND
+2
V1- 3
34 IN1C2
0
OUTA1 4
33 IN1B2
+2
0
V1+ 5
32 IN1A2
THERMAL
PAD
EN1 6
31 GND
HIZ1 7
30 IN0A2
IN0C1 8
29 IN0B2
IN0B1 9
28 IN0C2
IN0A1 10
27 HIZ2
+2
+2
26 EN2
25 V2+
OUTA2 24
OUTB2 22
OUTC2 21
S0-2 20
S1-2 19
IN3C2 18
IN3B2 17
IN3A2 16
GND 15
IN2C2 14
IN2B2 13
CONNECTED TO VPAD MUST BE TIED TO V-
+2
0
V2- 23
IN1A1 12
THERMAL PAD INTERNALLY
0
0
GND 11
Functional Diagram ISL59482
EN0-1
S0-1
EN1-1
S1-1
DECODE1
IN0(A1, B1, C1)
IN1(A1, B1, C1)
EN2-1
EN3-1
IN2(A1, B1, C1)
+
OUT(A1, B1, C1)
IN3(A1, B1, C1)
AMPLIFIER1 BIAS
HIZ1
EN1
EN0-2
S0-2
EN1-2
S1-2
DECODE2
IN0(A2, B2, C2)
OUT(A2, B2, C2)
IN1(A2, B2, C2)
EN2-2
EN3-2
+
IN2(A2, B2, C2)
IN3(A2, B2, C2)
AMPLIFIER2 BIAS
HIZ2
EN2
2
FN6209.2
December 22, 2006
ISL59482
Absolute Maximum Ratings (TA = +25°C)
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.5V, V+ +0.5V
Supply Turn-on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs
Digital and Analog Input Current (Note 1) . . . . . . . . . . . . . . . . 50mA
Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7). . . .2500V
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . .-40°C to +125°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
V1+ = V2+ = +5V, V1- = V2- = -5V, GND = 0V, TA = +25°C, Input Video = 0.5VP-P and RL = 500Ω to GND,
CL = 5pF unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
GENERAL
+IS Enabled
Enabled Supply Current
No load, VIN = 0V, EN1, EN2 Low
77
88
96
mA
-IS Enabled
Enabled Supply Current
No load, VIN = 0V, EN1, EN2 Low
-90
-82
-70
mA
7.6
mA
+IS Disabled
Disabled Supply Current
No load, VIN = 0V, EN1, EN2 High
4
6.8
-IS Disabled
Disabled Supply Current
No load, VIN = 0V, EN1, EN2 High
-80
-12
VOUT
Positive and Negative Output Swing
VIN = ±2.5V, RL = 500Ω
±3.8
±4.0
±4.2
V
IOUT
Output Current
RL = 10Ω to GND
±80
±135
±180
mA
VOS
Output Offset Voltage
-60
-25
20
mV
µA
Input Bias Current
VIN = 0V
-10
-2
+10
µA
ROUT
HIZ Output Resistance
HIZ = Logic High
700
1000
1300
Ω
ROUT
Enabled Output Resistance
HIZ = Logic Low
0.1
Ω
Input Resistance
VIN = ±1.75V
10
MΩ
Voltage Gain
VIN = ±0.75V, RL= 500Ω
Output Current in Three-state
VOUT = 0V
Ib
RIN
ACL or AV
IHIZ
1.94
1.99
2.04
V/V
15
µA
LOGIC
VIH
Input High Voltage (Logic Inputs)
2
V
VIL
Input Low Voltage (Logic Inputs)
0.8
V
IIH
Input High Current (Logic Inputs)
VH = 5V
200
260
320
µA
IIL
Input Low Current (Logic Inputs)
VL = 0V
-10
-2
+10
µA
PSRR
Power Supply Rejection Ratio
DC, PSRR V+ & V- combined
VOUT = 0dBm
45
53
dB
Xtalk
Channel to Channel Crosstalk
f = 10MHz, ChX-Ch Y-Talk
VIN = 1Vp-p; CL = 1.2pF
65
dB
Off-state Isolation
f = 10MHz, Ch-Ch Off Isolation
VIN = 1Vp-p; CL = 1.2pF
90
dB
dG
Differential Gain Error
NTC-7, RL = 150, CL = 1.2pF
0.008
%
dP
Differential Phase Error
NTC-7, RL = 150, CL = 1.2pF
0.01
°
AC GENERAL
Off - ISO
3
FN6209.2
December 22, 2006
ISL59482
Electrical Specifications
PARAMETER
BW
V1+ = V2+ = +5V, V1- = V2- = -5V, GND = 0V, TA = +25°C, Input Video = 0.5VP-P and RL = 500Ω to GND,
CL = 5pF unless otherwise specified. (Continued)
DESCRIPTION
Small Signal -3dB Bandwidth
SR
MIN
TYP
MAX
UNIT
VOUT = 0.2Vp-p; RL = 500Ω, CL = 1.2pF
520
MHz
VOUT = 0.2Vp-p; RL = 150Ω, CL = 1.2pF
420
MHz
VOUT = 2Vp-p; RL = 500Ω, CL = 1.2pF
250
MHz
VOUT = 2Vp-p; RL = 150Ω, CL = 1.2pF
230
MHz
0.1dB Bandwidth
VOUT = 2Vp-p; RL = 500Ω, CL = 1.2pF
35
MHz
VOUT = 2Vp-p; RL = 150Ω, CL = 1.2pF
90
MHz
Slew Rate
25% to 75%, RL = 150Ω, Input Enabled,
CL = 1.5pF
1600
V/µs
Large Signal -3dB Bandwidth
FBW
CONDITIONS
TRANSIENT RESPONSE
tr, tf Large
Signal
Large Signal Rise, Fall TImes, tr, tf,
10% - 90%
VOUT = 2Vp-p; RL = 500Ω, CL = 1.2pF
1.2
ns
VOUT = 2Vp-p; RL = 150Ω, CL = 1.2pF
1.2
ns
tr, tf, Small
Signal
Small Signal Rise, Fall TImes, tr, tf,
10% - 90%
VOUT = 0.2Vp-p; RL = 500Ω, CL = 1.2pF
0.7
ns
VOUT = 0.2Vp-p; RL = 150Ω, CL = 1.2pF
0.8
ns
Settling TIme to 0.1%
VOUT = 2Vp-p; RL = 500Ω, CL = 1.2pF
22
ns
VOUT = 2Vp-p; RL = 150Ω, CL = 1.2pF
24
ns
VOUT = 2Vp-p; RL = 500Ω, CL = 1.2pF
5
ns
VOUT = 2Vp-p; RL = 150Ω, CL = 1.2pF
7
ns
ts 0.1%
Settling TIme to 1%
ts 1%
SWITCHING CHARACTERISTICS
Channel-to-Channel Switching Glitch
VIN = 0V, CL = 1.2pF
60
mVP-P
EN Switching Glitch
VIN = 0V, CL = 1.2pF
200
mVP-P
HIZ Switching Glitch
VIN = 0V, CL = 1.2pF
300
mVP-P
tSW-L-H
Channel Switching Time Low to High
1.2V logic threshold to 10% movement of
analog output
22
ns
tSW-H-L
Channel Switching Time High to Low
1.2V logic threshold to 10% movement of
analog output
25
ns
Propagation Delay
10% to 10%
0.9
ns
VGLITCH
tpd
Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = +25°C, unless otherwise specified.
10
10
VOUT = 0.2Vp-p
NORMALIZED GAIN (dB)
6
4
CL = 6.8pF
CL = 4.5pF
2
CL = 3.4pF
0
-2
CL = 2.7pF
CL = 2.2pF
-4
CL = 1.2pF
-6
-8
-10
CL INCLUDES 1.2pF
BOARD CAPACITANCE
1M
10M
100M
FIGURE 1. SMALL SIGNAL GAIN vs FREQUENCY vs CL
INTO 500Ω LOAD
4
1G
CL = 16.2pF
6
CL = 11.2pF
4
CL = 6.8pF
2
0
-2
-4
CL= 3.9pF
-6
-8
FREQUENCY (Hz)
VOUT = 0.2Vp-p
8
CL = 11.2pF
NORMALIZED GAIN (dB)
8
CL INCLUDES 1.2pF
BOARD CAPACITANCE
CL= 1.2pF
-10
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 2. SMALL SIGNAL GAIN vs FREQUENCY vs CL
INTO 150Ω LOAD
FN6209.2
December 22, 2006
ISL59482
Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = +25°C, unless otherwise specified.
0.4
2
VOUT = 0.2Vp-p
CL= 1.2pF
1
RL = 1kΩ
-1
RL = 250Ω
-2
RL = 500Ω
-3
-4
RL = 150Ω
-5
-6
CL INCLUDES 1.2pF
BOARD CAPACITANCE
-7
0.1
0
RL = 500Ω
CL = 1.2pF
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-8
1M
10M
100M
1M
1G
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 4. 0.1dB GAIN FLATNESS
FIGURE 3. GAIN vs FREQUENCY vs RL
10k
100
VSOURCE = 2Vp-p
OUTPUT IMPEDANCE (Ω)
VSOURCE = 2Vp-p
OUTPUT IMPEDANCE (Ω)
RL = 150Ω
CL = 1.2pF
0.2
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
VOUT = 0.2Vp-pΩ
0.3
0
10
1
0.1
0.1M
1M
10M
100M
1000
100
10
0.1M
1G
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 6. ZOUT vs FREQUENCY - HIZ
FIGURE 5. ZOUT vs FREQUENCY - ENABLED
1M
10
VSOURCE = 2Vp-p
VSOURCE = 1Vp-p
0
100k
PSRR (V-)
-10
10k
PSRR (dB)
INPUT IMPEDANCE (Ω)
(Continued)
1k
100
-20
-30
-40
PSRR (V+)
10
1
0.3M
-50
1M
10M
100M
FREQUENCY (Hz)
FIGURE 7. ZIN vs FREQUENCY
5
1G
-60
0.3
1
10
100
1k
FREQUENCY (MHz)
FIGURE 8. PSRR vs FREQUENCY
FN6209.2
December 22, 2006
ISL59482
Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = +25°C, unless otherwise specified.
(Continued)
0
VIN=1Vp-p
-10
-20
-40
VOLTAGE NOISE (nV/√Hz)
RL = 500
CROSSTALK
INPUT X TO OUTPUT Y RL = 150
-30
(dB)
60
OFF ISOLATION
INPUT X TO OUTPUT X
-50
-60
RL = 150 RL = 500
-70
-80
-90
50
40
30
20
10
-100
-110
0
-120
0.3M
1M
10M
100M
1G
100
1k
FREQUENCY (Hz)
0
-0.002
-0.004
-0.006
-0.008
-0.01
0.02
0
-0.02
-0.04
-0.06
-0.08
-0.10
-2
-1
0
1
2
3
4
NORMALIZED PHASE (O) NORMALIZED GAIN (dB)
NORMALIZED PHASE (O) NORMALIZED GAIN (dB)
0.002
-3
0.01
0.008
0.006
0.004
0.002
0
-0.002
-0.004
0.04
0.02
0
-0.02
-0.04
-0.06
-0.08
-0.10
-4
VOUT DC (Volts)
-3
-2
-1
0
1
3
4
FIGURE 12. DIFFERENTIAL GAIN AND PHASE: VOUT=0.2Vp-p
FO=3.58MHz; RL=150Ω
VOUT = 0.2Vp-p
VOUT = 0.2Vp-p
RL = 500Ω
CL = 1.2pF
0.2
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
2
Vout DC (Volts)
FIGURE 11. DIFFERENTIAL GAIN AND PHASE; VOUT=0.2Vp-p
FO=3.58MHz; RL=500Ω
0.2
100k
FIGURE 10. INPUT NOISE vs FREQUENCY
FIGURE 9. CROSSTALK AND OFF ISOLATION;
-4
10k
FREQUENCY (Hz)
0.1
0
RL = 150Ω
CL = 1.2pF
0.1
0
TIME (5ns/DIV)
FIGURE 13. SMALL SIGNAL TRANSIENT RESPONSE;
RL=500Ω
6
TIME (5ns/DIV)
FIGURE 14. SMALL SIGNAL TRANSIENT RESPONSE;
RL=150Ω
FN6209.2
December 22, 2006
ISL59482
Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = +25°C, unless otherwise specified.
VOUT = 2Vp-p
VOUT = 2Vp-p
RL = 500Ω
CL = 1.2pF
RL = 150Ω
CL = 1.2pF
2.0
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
2.0
1.0
1.0
0
0
TIME (5ns/DIV)
TIME (5ns/DIV)
FIGURE 15. LARGE SIGLNAL TRANSIENT RESPONSE;
RL=500Ω
FIGURE 16. LARGE SIGNAL TRANSIENT RESPONSE;
RL=150Ω
50
50
INPUT RISE, FALL TIMES
VOUT = 2Vp-p
<175ps
VOUT = 1.4Vp-p
INPUT RISE, FALL TIMES
<175ps
VOUT = 2Vp-p
40
VOUT = 1.4Vp-p
OVERSHOOT (%)
OVERSHOOT (%)
40
(Continued)
30
20
VOUT = 1Vp-p
10
30
20
VOUT = 1Vp-p
10
VOUT = 0.2Vp-p
VOUT = 0.2Vp-p
0
2
4
CL (Pf)
6
8
0
10
FIGURE 17. PULSE OVERSHOOT vs VOUT, CL; RL=500Ω
2
8
10
1V/DIV
1V/DIV
6
VIN = 1V
S0, S1
50Ω
TERM.
0
0
VOUT A, B, C
1V/DIV
20mV/DIV
CL (Pf)
FIGURE 18. PULSE OVERSHOOT vs VOUT, CL; RL=150Ω
VIN = 0V
S0, S1
50Ω
TERM.
4
0
0
20ns/DIV
FIGURE 19. CHANNEL TO CHANNEL SWITCHING GLITCH
VIN = 0V
7
20ns/DIV
VOUT A, B, C
FIGURE 20. CHANNEL TO CHANNEL TRANSIENT RESPONSE
VIN = 1V
FN6209.2
December 22, 2006
ISL59482
Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = +25°C, unless otherwise specified.
VIN = 0V
ENABLE
50Ω
TERM.
VIN = 1V
ENABLE
1V/DIV
1V/DIV
50Ω
TERM.
0
0
VOUT A, B, C
1V/DIV
0.5V/DIV
(Continued)
0
VOUT A, B, C
0
40ns/DIV
40ns/DIV
FIGURE 22. ENABLE TRANSIENT RESPONSE VIN = 1V
FIGURE 21. ENABLE SWITCHING GLITCH VIN = 0V
VIN = 1V
S0, S1
50Ω
TERM.
1V/DIV
1V/DIV
0
0
0
0
VOUT A, B, C
2V/DIV
100mV/DIV
VIN = 0V
S0, S1
50Ω
TERM.
VOUT A, B, C
20ns/DIV
20ns/DIV
FIGURE 23. HIZ SWITCHING GLITCH VIN = 0V
FIGURE 24. HIZ TRANSIENT RESPONSE VIN = 1V
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
1.2
5
4.34W
POWER DISSIPATION (W)
POWER DISSIPATION (W)
6
QFN48
θJA=23°C/W
4
3
2
1
1.0
870mW
QFN48
θJA=115°C/W
0.8
0.6
0.4
0.2
0
0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
8
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN6209.2
December 22, 2006
ISL59482
Pin Description
ISL59482
EQUIVALENT
(48 LD QFN) PIN NAME
CIRCUIT
DESCRIPTION
1
OUTC1
Circuit 3
Output of amplifier C1
2
OUTB1
Circuit 3
Output of amplifier B1
3, 23
V1-, V2-
Circuit 4A
4
OUTA1
Circuit 3
5, 25
V1+, V2+
Circuit 4A
6
EN1
Circuit 2
26
EN2
Device enable (active low) w/internal pull-down resistor. A logic High puts device into power-down mode
leaving the logic circuitry active. This state is not recommended for logic control where more than one
MUX-amp share the same video output line.
7
HIZ1
Circuit 2
27
HIZ2
Output disable (active high) w/internal pull-down resistor. A logic high puts the output in a high
impedance state. Use this state when more than one MUX-amp share the same video output line.
8
IN0C1
Circuit 1
Channel 0 input for amplifier C1
9
IN0B1
Circuit 1
Channel 0 input for amplifier B1
10
IN0A1
Circuit 1
Channel 0 input for amplifier A1
11
GND
Circuit 4A
12
IN1A1
Circuit 1
Channel 1 input for amplifier A1
13
IN2B2
Circuit 1
Channel 2 input for amplifier B2
14
IN2C2
Circuit 1
Channel 2 input for amplifier C2
15
GND
Circuit 4B
16
IN3A2
Circuit 1
Channel 3 input for amplifier A2
17
IN3B2
Circuit 1
Channel 3 input for amplifier B2
18
IN3C2
Circuit 1
Channel 3 input for amplifier C2
19, 47
S1-2, S1-1
Circuit 2
Channel select pin MSB (binary logic code) for amplifiers A2, B2, C2 (S1-2) and A1, B1, C1 (S1-1)
20, 48
S0-2, S0-1
Circuit 2
Channel select pin LSB (binary logic code) for amplifiers A2, B2, C2 (S0-2) and A1, B1, C1 (S0-1)
21
OUTC2
Circuit 2
Output of amplifier C2
22
OUTB2
Circuit 1
Output of amplifier B2
24
OUTA2
Circuit 1
Output of amplifier A2
28
IN0C2
Circuit 1
Channel 0 input for amplifier A2
29
IN0B2
Circuit 1
Channel 0 input for amplifier B2
30
IN0A2
Circuit 1
Channel 0 input for amplifier C2
31
GND
Circuit 4B
32
IN1A2
Circuit 1
Channel 1 input for amplifier A2
33
IN1B2
Circuit 1
Channel 1 input for amplifier B2
34
IN1C2
Circuit 1
Channel 1 input for amplifier C2
35
GND
Circuit 4B
36
IN2A2
Circuit 1
Channel 2 input for amplifier A2
37
IN1B1
Circuit 1
Channel 1 input for amplifier B1
38
IN1C1
Circuit 1
Channel 1 input for amplifier C1
39
GND
Circuit 4A
40
IN2A1
Circuit 1
Channel 2 input for amplifier A1
41
IN2B1
Circuit 1
Channel 2 input for amplifier B1
9
Negative power supply #1 and #2
Output of amplifier A1
Positive Power Supply #1 and #2
Ground pin for amplifier A1
Ground pin for amplifier C2
Ground pin for amplifier A2
Ground pin for amplifier B2
Ground pin for amplifier B1
FN6209.2
December 22, 2006
ISL59482
Pin Description
(Continued)
ISL59482
EQUIVALENT
(48 LD QFN) PIN NAME
CIRCUIT
DESCRIPTION
42
IN2C1
Circuit 1
Channel 2 input for amplifier C1
43
GND
Circuit 4A
44
IN3A1
Circuit 1
Channel 3 input for amplifier A1
45
IN3B1
Circuit 1
Channel 3 input for amplifier B1
46
IN3C1
Circuit 1
Channel 3 input for amplifier C1
Ground pin for amplifier C1
Pin Equivalent Circuits
V+
V+
21k
LOGIC PIN
IN
33k
+
1.2V
-
OUT
GND
V-
V-
VCIRCUIT 2
CIRCUIT 1
V1+
V2+
GNDA1
GNDA2
CAPACITIVELY
COUPLED
ESD CLAMP
GNDB1
V+
GNDC1
CIRCUIT 3
SUBSTRATE 1
CAPACITIVELY
COUPLED
ESD CLAMP
GNDB2
SUBSTRATE 2
V1-
V2~1MΩ
~1MΩ
GNDC2
V1-
V2CIRCUIT 4A
THERMAL HEAT SINK PAD
CIRCUIT 4B
AC Test Circuits (Continued)
AC Test Circuits
ISL59482
VIN
ISL59482
CL
5pF
50Ω
or
75Ω
RL
500Ω
RS
VIN
50Ω
or
75Ω
CL
5pF
50Ω or 75Ω
TEST
EQUIPMENT
50Ω
or
75Ω
FIGURE 27A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD
TEST
EQUIPMENT
ISL59482
RS
VIN
50Ω
or
75Ω
CL
5pF
475Ω
50Ω
or
75Ω
50Ω
or
75Ω
FIGURE 27B. TEST CIRCUIT FOR MEASURING WITH 50Ω OR
75Ω INPUT TERMINATED EQUIPMENT
10
FIGURE 27C. BACKLOADED TEST CIRCUIT FOR VIDEO
CABLE APPLICATION. BANDWIDTH AND
LINEARITY FOR RL LESS THAN 500Ω WILL BE
DEGRADED.
FIGURE 27. TEST CIRCUITS
Figure 27A illustrates the optimum output load for testing AC
performance. Figure 27B illustrates the optimum output load
when connecting to 50Ω input terminated equipment.
FN6209.2
December 22, 2006
ISL59482
Application Information
Therefore, adequate current limiting on the digital and
analog inputs is needed to prevent damage during the time
the voltages on these inputs are more positive than V+.
General
The ISL59482 is ideal as the matrix element of high
performance switchers and routers. Key features include
internal fixed gain of 2, high impedance buffered analog
inputs and excellent AC performance at output loads down
to 150Ω for video cable-driving. The current feedback output
amplifiers are stable operating into capacitive loads.
HIZ State
Each internal 4:1 triple MUX-amp has a three-state output
control pin (HIZ1 and HIZ2). Each has a an internal pulldown resistor to set the output to the enabled state with no
connection to the HIZ pin. The HIZ state is established within
approximately 20ns by placing a logic high (>2V) on the HIZ
pin. If the HIZ state is selected, the output is a high
impedance 1.4MΩ with approximately 1.5pF in parallel with
a 10μA bias current from the output. When more than one
MUX shares a common output, the high impedance state
loading effect is minimized over the maximum output voltage
swing and maintains its high Z even in the presence of high
slew rates. The supply current during this state is the same
as the active state.
Ground Connections
For the best isolation and crosstalk rejection, all GND pins
must connect to the GND plane.
Power-up Considerations
The ESD protection circuits use internal diodes from all pins the
V+ and V- supplies. In addition, a dV/dT- triggered clamp is
connected between the V+ and V- pins, as shown in the
Equivalent Circuits 1 through 4 section of the Pin Description
table. The dV/dT triggered clamp imposes a maximum supply
turn-on slew rate of 1V/µs. Damaging currents can flow for
power supply rates-of-rise in excess of 1V/µs, such as during
hot plugging. Under these conditions, additional methods
should be employed to ensure the rate of rise is not exceeded.
EN and Power-down States
The EN pin is active low. An internal pull-down resistor
ensures the device will be active with no connection to the
EN pin. The Power-down state is established within
approximately 80ns, if a logic high (>2V) is placed on the EN
pin. In the Power-down state, supply current is reduced
significantly by shutting the three amplifiers off. The output
presents a high impedance to the output pin, however, there
is a risk that the disabled amplifier output can be back-driven
at signal voltage levels exceeding 2VP-P. Under this
condition, large incoming slew rates can cause fault currents
of tens of mA. Therefore, the parallel connection of multiple
outputs is not recommended unless the application can
tolerate the limited power-down output impedance.
Consideration must be given to the order in which power is
applied to the V+ and V- pins, as well as analog and logic
input pins. Schottky diodes (Motorola MBR0550T or
equivalent) connected from V+ to ground and V- to ground
(Figure 28) will shunt damaging currents away from the
internal V+ and V- ESD diodes in the event that the V+
supply is applied to the device before the V- supply. One
Schottky can be used to protect both V+ power supply pins,
and a second for the protection of both V- pins.
Limiting the Output Current
If positive voltages are applied to the logic or analog video
input pins before V+ is applied, current will flow through the
internal ESD diodes to the V+ pin. The presence of large
decoupling capacitors and the loading effect of other circuits
connected to V+, can result in damaging currents through
the ESD diodes and other active circuits within the device.
No output short circuit current limit exists on these parts. All
applications need to limit the output current to less than
50mA. Adequate thermal heat sinking of the parts is also
required.
V+ SUPPLY
SCHOTTKY
PROTECTION
LOGIC
V+
LOGIC
CONTROL
S0
POWER
GND
EXTERNAL
CIRCUITS
V+
GND
V-
IN0
V+
V+
V+
SIGNAL
OUT
V-
DE-COUPLING
CAPS
IN1
VV-
V-
V- SUPPLY
FIGURE 28. SCHOTTKY PROTECTION CIRCUIT
11
FN6209.2
December 22, 2006
ISL59482
PC Board Layout
The AC performance of this circuit depends greatly on the
care taken in designing the PC board. The following are
recommendations to achieve optimum high frequency
performance from your PC board.
• The use of low inductance components such as chip
resistors and chip capacitors is strongly recommended.
• Minimize signal trace lengths. Trace inductance and
capacitance can easily limit circuit performance. Avoid
sharp corners, use rounded corners when possible. Vias
in the signal lines add inductance at high frequency and
should be avoided. PCB traces greater than 1" begin to
exhibit transmission line characteristics with signal rise/fall
times of 1ns or less. High frequency performance may be
degraded for traces greater than one inch, unless strip line
are used.
• Match channel-channel analog I/O trace lengths and
layout symmetry. This will minimize propagation delay
mismatches.
• Maximize use of AC de-coupled PCB layers. All signal I/O
lines should be routed over continuous ground planes (i.e.
no split planes or PCB gaps under these lines). Avoid vias
in the signal I/O lines.
• Use proper value and location of termination resistors.
Termination resistors should be as close to the device as
possible.
• When testing use good quality connectors and cables,
matching cable types and keeping cable lengths to a
minimum.
• Minimum of 2 power supply decoupling capacitors are
recommended (1000pF, 0.01µF) as close to the devices
as possible. Avoid vias between the cap and the device
because vias add unwanted inductance. Larger caps can
be farther away. When vias are required in a layout, they
should be routed as far away from the device as possible.
• The NIC pins are placed on both sides of the input pins.
These pins are not internally connected to the die. It is
recommended these pins be tied to ground to minimize
crosstalk.
The QFN Package Requires Additional PCB Layout
Rules for the Thermal Pad
The thermal pad is electrically connected to V- supply
through the high resistance IC substrate. Its primary function
is to provide heat sinking for the IC. However, because of the
connection to the V1- and V2- supply pins through the
substrate, the thermal pad must be tied to the V- supply to
prevent unwanted current flow to the thermal pad. Do not tie
this pin to GND as this could result in large back biased
currents flowing between GND and the V- pins. Maximum
AC performance is achieved if the thermal pad is attached to
a dedicated decoupled layer in a multi-layered PC board. In
cases where a dedicated layer is not possible, AC
performance may be reduced at upper frequencies.
12
The thermal pad requirements are proportional to power
dissipation and ambient temperature. A dedicated layer
eliminates the need for individual thermal pad area. When a
dedicated layer is not possible, an isolated thermal pad on
another layer should be used. Pad area requirements should
be evaluated on a case by case basis.
MUX Application Circuits
Each of the two 4:1 triple MUX amplifiers have their own
binary-coded, TTL compatible channel select logic inputs
(S0-1, 2, and S1-1, 2). All three amplifiers are switched
simultaneously from their respective inputs with S0-1 S1-1
controlling MUX-amp1, and S0-2, S1-2 controlling
MUX-amp2.
The HIZ control inputs (HIZ1, HIZ2) and device enable control
inputs (EN1 and EN2) control MUX-amp1 and MUX-amp2 in a
similar fashion. The individual control for each 4:1 triple MUX
enables external connections to configure the device for
different MUX applications.
8:1 RGB Video MUX
For a triple input RGB 8:1 MUX (Figure 4), the RGB amplifier
outputs of MUX-amp1 are parallel-connected to the RGB
amplifier outputs of MUX-amp2 to produce the single RGB
video output. Input channels CH0 to CH3 are assigned to
MUX-amp1, and channels CH4 through CH7 are assigned to
MUX-amp2. Channels CH0 through CH3 are selected by
setting HIZ1 low, HIZ2 high (enables MUX-amp1 and threestates MUX-amp2) and the appropriate channel select logic
to S0-1, S1-1. Reversing the logic inputs of HIZ1, HIZ2
switches from MUX-amp1 to MUX-amp2 enabling the
selection of channels CH4 through CH7. The channel select
inputs are parallel connected (S0-1 to S0-2) and (S1-1 to
S1-2) to form two logic controls S0, S1. A single S2 control is
split into complimentary logic inputs for HIZ1 and HIZ2 to
produce a chip select function for the MSB. The logic control
truth table is shown in Figure 29.
4:1 RGB Differential Video MUX
Connecting the channel select pins in parallel (S0-1 to S0-2
and S1-1 to S1-2) converts the 8 individual RGB video inputs
into 4 differential RGB input pairs. The amplifier RGB outputs
are similarly paired resulting in a fully differential 4:1 RGB
MUX amp shown in Figure 5. Connecting HIZ1 and HIZ2 to
+5V disables the 4:1 differential MUX, and enables the
connection of additional differential-connected MUX amplifiers
to the same outputs, thus allowing input expansion to 8:1 or
more.
FN6209.2
December 22, 2006
ISL59482
ISL59482
1/3 MUX-Amp1
IN0A1
CH0
IN1A1
CH1
IN2A1
CH2
CHANNEL SELECT TRUTH TABLE
8:1 VIDEO MUX
OUTA1
IN3A1
CH3
S0-1
CH0A - CH7A
S1-1
Channels B & C
Not Shown
Control
Logic
OUTA
HIZ1
IN0A2
CH4
1/3 MUX-Amp2
IN1A2
CH5
IN2A2
CH6
+2
OUTA2
IN3A2
CH7
S0-2
S0
Channel Select
Logic Inputs
+2
S1-2
S1
S2
S1
S0
OUTA, B, C
0
0
0
CH0A, B, C
0
0
1
CH1A, B, C
0
1
0
CH2A, B, C
0
1
1
CH3A, B, C
1
0
0
CH4A, B, C
1
0
1
CH5A, B, C
1
1
0
CH6A, B, C
1
1
1
CH7A, B, C
Control
Logic
HIZ2
S2
FIGURE 29. APPLICATION CIRCUIT FOR 8:1 RGB VIDEO MUX
ISL59482
1/3 MUX-Amp1
IN0A1
+
CH0
-
IN1A1
IN2A1
+2
CHANNEL SELECT TRUTH TABLE
4:1 DIFFERENTIAL VIDEO MUX
OUTA1
IN3A1
CH0A - CH3A
+
CH1
-
S0-1
S1-1
Channels B & C
Not Shown
+
-
IN0A2
OUTA, B, C
0
0
CH0A, B, C
OUTA
0
1
CH1A, B, C
1/3 MUX-Amp2
-
1
0
CH2A, B, C
1
1
CH3A, B, C
IN1A2
IN2A2
+
CH3
-
Channel Select
Logic Inputs
S0
+
Control
Logic
HIZ1
CH2
S1
+2
OUTA2
IN3A2
S0-2
S0
S1-2
S1
HIZ
Control
Logic
HIZ2
FIGURE 30. APPLICATION CIRCUIT FOR 4:1 RGB DIFFERENTIAL VIDEO MUX
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
13
FN6209.2
December 22, 2006
ISL59482
Package Outline Drawing
L48.7x7B
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 12/06
4X 5.5
7.00
A
44X 0.50
B
37
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
48
1
7.00
36
3.70
12
25
(4X)
0.15
13
24
0.10 M C A B
48X 0 . 40
TOP VIEW
4 0.25
BOTTOM VIEW
SEE DETAIL "X"
( 6 . 80 TYP )
(
0.10 C
BASE PLANE
0 . 85 ± 0 . 1
3.70 )
C
SEATING PLANE
0.08 C
SIDE VIEW
( 44X 0 . 5 )
C
0 . 2 REF
5
( 48X 0 . 25 )
( 48X 0 . 60 )
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
14
FN6209.2
December 22, 2006