ISL59451 ® Data Sheet September 24, 2007 Triple 4:1 DC Restored Single Supply Video Multiplexing Amplifier FN6253.0 Features • Complete Video Level DC Restoration System • Capable of Pixel Rate Channel Switching • TTL/CMOS Compatible Keyed Clamp Control • High Impedance Output Setting • 150Ω Output Load Capability for Video Cable Driving • Ideal for RGB/YPbPr/S-Video/Composite Video Signals • Pb-Free (RoHS Compliant) Applications • SDTVs and HDTVs • Set-Top Boxes • Video Overlay • Security Video • Broadcast Video Equipment Pinout The ISL59451 is comes in a 32 Ld QFN package and is specified for operation over the -40°C to +85°C extended temperature range. PART NUMBER (Note) PART MARKING 25 AV2 2/1 R1 1 24 ROUT 23 REF_RB THERMAL PAD B1 2 G1 3 Ordering Information 26 HIZ 27 GND 32 GND 28 V+ ISL59451 (32 LD QFN) TOP VIEW The ISL59451 operates from a single +5V supply and is ideal for +5V systems when used with sync separators such as the EL1883. The red and blue channels share a common reference pin (REF_RB) which can also be used to adjust chroma offsets in YPbPr systems. The green channel has a separate reference pin (REF_G), which can be used to accommodate sync-on-green or luma. 29 R0 The device features a TTL/CMOS logic compatible gain select pin (AV2) of x1 or x2. When HIZ is pulled high, the outputs are put into high-impedance states and the video inputs are disconnected. This is an essential feature for power sensitive applications. The ISL59451 also features channel-switching at pixel rates to allow for video overlays. • +5V Single Supply Operation 30 B0 When logic “0” is applied to CLAMP, the sample-hold amplifier loop is closed and the DC level of the amplifier output is set to the corresponding reference level. This can occur during sync, or at any time that a black level is expected. When logic “1” is applied to CLAMP, the clamp is disabled and the correcting voltage is stored on each video amplifier’s input coupling capacitor. This DC reference condition is maintained during the active video period. The restored DC voltage level can be adjusted over a range of 0V to +3V using external reference voltages applied to the REF_G and REF_RB pins. • 250MHz Bandwidth (GAIN = 1) 31 G0 The ISL59451 is a 4-input, single-supply triple video multiplexer. It features a DC restore function that makes it ideally suited for single-supply AC-coupled component video applications where amplifier headroom is a concern. 22 GND 2/1 21 BOUT GND 4 PACKAGE (Pb-Free) PKG. DWG. # 20 V+ V+ 5 2/1 ISL59451IRZ ISL594 51IRZ 32 Ld 5x5 QFN L32.5x5 GND 6 ISL59451IRZ-T7* ISL594 51IRZ 32 Ld 5x5 QFN L32.5x5 R2 7 18 GOUT B2 8 17 GND 1 CLAMP 16 S0 15 S1 14 G3 13 B3 12 R3 11 GND 10 NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. G2 9 *Please refer to TB347 for details on reel specifications. 19 REF_G Exposed Thermal Pad (Gray Area) must be connected to GND. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2007. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL59451 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage (V+ to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Input Voltage to GND. . . . . . . . . . . . . . . . . .GND - 0.5V to V+ +0.5V Voltage between HIZ, CLAMP, AV2, REF_ and GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.5;V+ +0.5V Supply Turn-on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs Digital and Analog Input Current (Note 1) . . . . . . . . . . . . . . . . 50mA Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7). . . .2500V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V Storage Temperature Range . . . . . . . . . . . . . . . . . . -65°C to +150°C Ambient Operating Temperature . . . . . . . . . . . . . . . . -40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . . -40°C to +125°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Curves Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 1. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values. 2. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER V+ = +5V, GND = 0V, TA = +25°C, RL = 150Ω to GND, REF_G = 0.5V, REF_RB = 1.2V, CLAMP = 2.0V, S1 = S0 = AV2 = HIZ = 0.8V, unless otherwise specified. DESCRIPTION CONDITIONS MIN (Note 2) TYP MAX (Note 2) UNIT 4.5 5.0 5.5 V DC CHARACTERISTICS V+ Supply Voltage +IS Enabled Enabled Supply Current No load, VIN = 2.2V, HIZ = 0.8V 45 75 mA +IS Disabled Disabled Supply Current No load, VIN = 2.2V, HIZ = 2.0V 3 5 mA VSHIFT IB ROUT_DIS AV PSRRDC Input to Output Level Shift (VIN - VOUT) DC-coupled inputs, VIN = 2V, GAIN = 1 1.2 1.6 2 V Input Bias Current VIN = 2.2V, No Load -1 0 1 µA Disabled Output Resistance (DC) HIZ = 2.0V 1.4 2 2.6 kΩ Voltage Gain AV2 = 0.8V, GAIN = 1 0.98 1 1.02 V/V AV2 = 2.0V, GAIN = 2 1.95 2.00 2.05 V/V V+ = 4.5V to 5.5V, CLAMP = 2.0V, VIN = 2.0V 40 50 dB V+ = 4.5V to 5.5V, CLAMP = 0.8V, inputs floating 50 65 dB 3.5 DC Power Supply Rejection Ratio OUTPUT AMPLIFIERS VOUT+ Maximum Output High Level RL = 150Ω, VIN = 4V, GAIN = 2 VOUT- Minimum Output Low Level RL = 150Ω,VIN = 0.8V, GAIN = 2 Short Circuit Current Sourcing, VIN = 4V, RL = 10Ω to GND, GAIN = 2 125 mA Sinking, VIN = 0V, RL = 10Ω to +3V 57 mA ISC V 15 mV DC RESTORE SECTION VCLAMP-OS ICLAMP IB_VREF Output Clamp Accuracy (VOUT VREF_RB) REF_RB = 1.2V, CLAMP = 0.8V -15 -4 +10 mV Output Clamp Accuracy (VOUT - VREF_G) REF_G = 0.5V, CLAMP = 0.8V -15 -3 +10 mV Positive Restore Clamp Current VIN = 0V, CLAMP = 0.8V, Sourcing 500 860 1100 µA Negative Restore Clamp Current VIN = 4V, CLAMP = 0.8V, Sinking 150 290 500 µA Reference Input Bias Current REF_G = 0.5V or 1.2V, VCLAMP = 0.8V -2 -0.4 +0.5 µA REF_RB = 0.5V or 1.2V, VCLAMP = 0.8V -3 -0.9 +0.5 µA 2 FN6253.0 September 24, 2007 ISL59451 Electrical Specifications PARAMETER V+ = +5V, GND = 0V, TA = +25°C, RL = 150Ω to GND, REF_G = 0.5V, REF_RB = 1.2V, CLAMP = 2.0V, S1 = S0 = AV2 = HIZ = 0.8V, unless otherwise specified. (Continued) DESCRIPTION CONDITIONS MIN (Note 2) TYP MAX (Note 2) UNIT LOGIC (CLAMP, AV2, HIZ, S1, S0) VIH Input High Voltage (HIGH) VIL Input Low Voltage (LOW) IIH Input High Current (Logic Inputs) IIL Input Low Current (Logic Inputs) 2 V 0.8 V S1 = S0 = CLAMP = 5V (no pull-up or pull-down) -1 0 +1 µA AV2 = HIZ= 5V (300kΩ internal pull-downs) 8 17 34 µA S1 = S0 = CLAMP = 0V (no pull-up or pull-down) -1 0 +1 µA AV2 = HIZ= 5V (300kΩ internal pull-downs) -1 0 +1 µA AC GENERAL PSRR Power Supply Rejection Ratio VIN = 2.0V, f = 10kHz to 10MHz, V+ = 5VDC + 100mVP-P sine wave 50 dB XTALK Channel-to-Channel Crosstalk (ROUT/BOUT to Green Input) f = 10MHz, VIN = 0.7VP-P; (GAIN = 1) 60 dB f = 10MHz, VIN = 0.7VP-P; (GAIN = 2) 55 dB De-Selected Channel Isolation f = 10MHz, Ch-Ch Off Isolation (any de-selected output to driven input) VIN = 0.7VP-P; (GAIN = 1) 94 dB f = 10MHz, Ch-Ch Off Isolation VIN = 0.7VP-P; (GAIN = 2) 89 dB OFFCH_ISO dG Differential Gain Error RL = 150 0.0025 % dP Differential Phase Error RL = 150 0.08 ° BW Small Signal -3dB Bandwidth VOUT = 0.2VP-P; RL = 150Ω, CL = 0.6pF (GAIN = 1) 240 MHz VOUT = 0.2VP-P; RL = 150Ω, CL = 0.6pF (GAIN = 2) 200 MHz VOUT = 1.4VP-P; RL = 150Ω, CL = 0.6pF (GAIN = 1) 210 MHz VOUT = 1.4VP-P; RL = 150Ω, CL = 0.6pF (GAIN = 2) 200 MHz VOUT = 1.4VP-P; RL = 150Ω, CL = 0.6pF (GAIN = 1) 30 MHz VOUT = 1.4VP-P; RL = 150Ω, CL = 0.6pF (GAIN = 2) 30 MHz VIN = 1.8 to 2.8V, time = 10% to 90%, RL = 150Ω, GAIN = 1 500 V/µs VIN = 1.8 to 2.3V, time = 10% to 90%, RL = 150Ω, GAIN = 2 930 V/µs VIN = 2.8 to 1.8V, time = 90% to 10%, RL = 150Ω, GAIN = 1 300 V/µs VIN = 2.3 to 1.8V, time = 90% to 10%, RL = 150Ω, GAIN = 2 600 V/µs Rise Time 10% to 90% VOUT = 0.7VP-P; RL = 150Ω, CL = 2.1pF, GAIN = 1 1.3 ns VOUT = 1.4VP-P; RL = 150Ω, CL = 2.1pF, GAIN = 2 2 ns Fall Time 90% to 10% VOUT = 0.7VP-P; RL = 150Ω, CL = 2.1pF, GAIN = 1 2.6 ns VOUT = 1.4VP-P; RL = 150Ω, CL = 2.1pF, GAIN = 2 2.3 ns Settling Time to 1% VOUT = 1VP-P; RL = 150Ω, CL = 2.1pF, GAIN = 1, time from 90% crossing to 1% of final value 2 ns VOUT = 1VP-P; RL = 150Ω, CL = 2.1pF, GAIN = 2, time from 90% crossing to 1% of final value 4 ns Large Signal -3dB Bandwidth BW_0.1 SR+ SR- 0.1dB Bandwidth Positive Slew Rate Negative Slew Rate TRANSIENT RESPONSE tR tF tS 1% 3 FN6253.0 September 24, 2007 ISL59451 Electrical Specifications PARAMETER V+ = +5V, GND = 0V, TA = +25°C, RL = 150Ω to GND, REF_G = 0.5V, REF_RB = 1.2V, CLAMP = 2.0V, S1 = S0 = AV2 = HIZ = 0.8V, unless otherwise specified. (Continued) DESCRIPTION MIN (Note 2) CONDITIONS TYP MAX (Note 2) UNIT SWITCHING CHARACTERISTICS VGLITCH HIZ High to Low Switching Glitch VIN = 1V, RL = 150Ω; CL = 2.1pF, GAIN = 1 500 mVP-P VIN = 1V, RL = 150Ω; CL = 2.1pF, GAIN = 2 300 mVP-P tSW-L-H Channel Switching Delay Time Low to High 1.2V logic threshold to 10% movement of analog output 3 ns tSW-H-L Channel Switching Delay Time High to Low 1.2V logic threshold to 10% movement of analog output 4 ns tHIZ-L-H HIZ Switching Delay Time Low to High 1.2V logic threshold to 10% movement of analog output 25 ns tHIZ-H-L HIZ Switching Delay Time High to Low 1.2V logic threshold to 10% movement of analog output 220 ns tpd Propagation Delay 10% input to 10% output 2.5 ns tHE Time to Enable CLAMP CLAMP = LOW to settled output 40 ns tHD Time to Disable CLAMP CLAMP = HIGH to settled output 20 ns Settling Time Diagram ±1% OF FINAL VALUE BAND FINAL VALUE 90% FINAL VALUE 10% FINAL VALUE tR 4 tS 1% FN6253.0 September 24, 2007 ISL59451 Typical Application Circuit +5V 1nF 10nF 1µF µC RED/Pr S1 0.1µF S0 AV2 V+ R0 75Ω GREEN/Y 0.1µF 3 G0 75Ω BLUE/Pb 0.1µF RED/Pr CLAMP 0.1µF R1 VIDEO OUT 3 G1 75Ω BLUE/Pb ROUT 1.6VDC 0.1µF REF_G + 00 0.1µF B1 01 75Ω RED/Pr 3 75Ω BLUE/Pb VIDEO OUT REF_RB + G2 GOUT 1.6VDC GREEN/Y 11 75Ω 0.1µF 75Ω X1/ X2 10 0.1µF R2 GREEN/Y RED/Pr 75Ω X1/ X2 75Ω GREEN/Y REF_RB + - B0 75Ω S1, S0 75Ω X1/ X2 0.1µF B2 BOUT 1.6VDC BLUE/Pb VIDEO OUT 75Ω RED/Pr 0.1µF R3 75Ω GREEN/Y 0.1µF G3 3 75Ω BLUE/Pb ISL59451 0.1µF B3 75Ω REF_G REF_RB CLAMP HIZ GND PULSE 0.5V 5 1.2V FN6253.0 September 24, 2007 ISL59451 VCC = +5V, RL = 150Ω to GND, TA = +25°C, unless otherwise specified. 5 VIN = 100mVP-P CL = 12.6pF 0 CL = 7.4pF -5 CL = 0.6pF CL = 5.3pF -10 CL = 2.1pF -15 -20 0.1k 1M 10M 100M 1G NORMALIZED MAGNITUDE (dB) NORMALIZED MAGNITUDE (dB) Typical Performance Curves 10G 5 VIN = 700mVP-P CL = 7.4pF -5 CL = 0.6pF -10 -20 0.1k 1M 10M 100M 1G 10G FREQUENCY (Hz) FIGURE 2. LARGE SIGNAL GAIN vs FREQUENCY vs CL INTO 150Ω LOAD, GAIN = 1 FIGURE 1. SMALL SIGNAL GAIN vs FREQUENCY vs CL INTO 150Ω LOAD, GAIN = 1 5 5 VIN = 100mVP-P CL = 12.6pF 0 CL = 7.4pF -5 CL = 5.3pF CL = 0.6pF -10 CL = 2.1pF -15 -20 0.1k 1M 10M 100M 1G NORMALIZED MAGNITUDE (dB) NORMALIZED MAGNITUDE (dB) CL = 5.3pF CL = 2.1pF -15 FREQUENCY (Hz) 10G VIN = 700mVP-P CL = 7.4pF -5 -15 CL = 2.1pF -20 0.1k 1M NORMALIZED MAGNITUDE (dB) CL = 7.4pF 0 -0.5 -1.0 -1.5 CL = 2.1pF -2.0 -3.0 0.1k CL = 5.3pF CL = 0.6pF -2.5 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 5. SMALL SIGNAL GAIN FLATNESS, GAIN = 1 6 10M 100M 1G 10G FIGURE 4. LARGE SIGNAL GAIN vs FREQUENCY vs CL INTO 150Ω LOAD, GAIN = 2 1.0 0.5 CL = 5.3pF CL = 0.6pF -10 FREQUENCY (Hz) FIGURE 3. SMALL SIGNAL GAIN vs FREQUENCY vs CL INTO 150Ω LOAD, GAIN = 2 VIN = 100mVP-P CL = 12.6pF 0 FREQUENCY (Hz) NORMALIZED MAGNITUDE (dB) CL = 12.6pF 0 10G 1.0 0.5 VIN = 700mVP-P CL = 7.4pF 0 -0.5 -1.0 -1.5 CL = 2.1pF -2.0 CL = 5.3pF -2.5 -3.0 0.1k CL = 0.6pF 1M 10M 100M 1G 10G FREQUENCY (Hz) FIGURE 6. LARGE SIGNAL GAIN FLATNESS, GAIN = 1 FN6253.0 September 24, 2007 ISL59451 VCC = +5V, RL = 150Ω to GND, TA = +25°C, unless otherwise specified. (Continued) 1.0 0.5 VIN = 100mVP-P NORMALIZED MAGNITUDE (dB) NORMALIZED MAGNITUDE (dB) Typical Performance Curves CL = 7.4pF 0 -0.5 -1.0 -1.5 CL = 2.1pF -2.0 -2.5 CL = 5.3pF CL = 0.6pF -3.0 0.1k 1M 10M 100M 1G 10G 1.0 VIN = 700mVP-P 0.5 CL = 7.4pF 0 -0.5 -1.0 -1.5 CL = 2.1pF -2.0 -2.5 CL = 0.6pF -3.0 0.1k 1M 10M 100M FREQUENCY (MHz) FREQUENCY (MHz) FIGURE 7. SMALL SIGNAL GAIN FLATNESS, GAIN = 2 CURRENT (mA) CURRENT (mA) 46 44 CLAMP = LOW REF_G = REF_RB = 0.5V INPUTS FLOATING, NO LOAD 40 CLAMP = HIGH REF_G = REF_RB = 0.5V INPUTS = 1.6V, NO LOAD 38 36 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 1G 10G FIGURE 8. LARGE SIGNAL GAIN FLATNESS, GAIN = 2 48 42 CL = 5.3pF 5.5 3.00 2.95 2.90 2.85 2.80 2.75 2.70 2.65 2.60 2.55 2.50 2.45 4.5 HIZ = HIGH 4.6 4.7 4.8 4.9 5.0 5.1 VOLTAGE (V) VOLTAGE (V) FIGURE 9. SUPPLY CURRENT vs SUPPLY VOLTAGE 5.2 5.3 5.4 5.5 FIGURE 10. DISABLED SUPPLY CURRENT vs SUPPLY VOLTAGE 23 2500 22 IMPEDANCE (Ω) IMPEDANCE (Ω) 2000 21 20 GAIN 2 19 18 1500 1000 500 17 16 0.1k GAIN 1 1M 10M FREQUENCY (Hz) FIGURE 11. ZOUT vs FREQUENCY - ENABLED 7 100M 0 0.1k 1M 10M 100M FREQUENCY (Hz) FIGURE 12. ZOUT vs FREQUENCY - DISABLED FN6253.0 September 24, 2007 ISL59451 Typical Performance Curves VCC = +5V, RL = 150Ω to GND, TA = +25°C, unless otherwise specified. (Continued) 0 -10 0 -10 VAC = 100mVP-P GREEN INPUT DRIVEN 100mVP-P TO ROUT/GOUT TO CROSSTALK (dB) PSRR (dB) -20 -20 -30 GAIN 2 -40 -30 GAIN 2 -40 -50 -60 GAIN 1 -70 -50 -80 GAIN 1 -60 0.001k 0.01k 0.1k 1M FREQUENCY (Hz) 10M -90 0.1k 100M 10M 100M 1G 10G FREQUENCY (Hz) FIGURE 13. PSRR vs FREQUENCY FIGURE 14. ACTIVE CHANNEL CROSSTALK 0 0 1 INPUT DRIVEN TO 100mVP-P TO -20 ANY DE-SELECTED OUTPUT -40 -10 -20 ISOLATION (dB) ISOLATION (dB) 1M GAIN 1 -60 -80 GAIN 2 HIZ = HIGH 1 INPUT DRIVEN TO 100mVP-P TO ANY OUTPUT -30 -40 -50 -60 -70 -80 -100 -90 -120 0.1k 1M 10M 100M FREQUENCY (MHz) 1G -100 0.1k 10G 450 0.0030 400 0.0025 350 0.0020 300 250 200 150 0.0005 50 -0.0005 10k FIGURE 17. INPUT REFERRED NOISE vs FREQUENCY 8 10G 0.0010 0 100 1k FREQUENCY (Hz) 1G 0.0015 100 0 10 10M 100M FREQUENCY (Hz) FIGURE 16. DISABLED ISOLATION DIFF GAIN (%) VOLTAGE NOISE (nV√Hz) FIGURE 15. DE-SELECTED CHANNEL OFF ISOLATION 1M VAC = 40mVP-P -0.0010 0.30 0.47 0.64 0.81 0.98 1.15 1.32 1.49 1.66 1.83 2.00 OUTPUT DC LEVEL (V) FIGURE 18. DIFFERENTIAL GAIN; fO = 3.58MHz, RL = 150Ω FN6253.0 September 24, 2007 ISL59451 Typical Performance Curves VCC = +5V, RL = 150Ω to GND, TA = +25°C, unless otherwise specified. (Continued) 0.06 REF_G = REF_RB = 180mV INIT CONDITION: CLAMP = LOGIC HIGH (OFF) for 10ms GAIN 1 0.04 PHASE (°) 0.02 OUTPUT 0 -0.02 GAIN 1 CLAMP -0.04 RSOURCE = 25Ω CCOUPLING = 0.1µF -0.06 -0.08 CLAMP = 1V/DIV OUTPUT = 60mV/DIV TIMEBASE = 20µs VAC = 40mVP-P -0.10 0.30 0.47 0.64 0.81 0.98 1.15 1.32 1.49 1.66 1.83 2.00 OUTPUT DC LEVEL (V) FIGURE 19. DIFFERENTIAL PHASE; fO = 3.58MHz, RL = 150Ω INPUT = NTSC VIDEO + SQUARE WAVE FIGURE 20. DC RESTORE SETTLING TIME INPUT = NTSC VIDEO + SQUARE WAVE OUTPUT OUTPUT VERTICAL = 300mV/DIV TIMEBASE = 2ms/DIV CLAMP = NTSC HSYNC FIGURE 21. RESPONSE TO +300mV DC STEP ON INPUT (SEE FIGURE 36) VERTICAL = 300mV/DIV TIMEBASE = 2ms/DIV FIGURE 22. RESPONSE TO -300mV DC STEP ON INPUT (SEE FIGURE 36) INPUT INPUT OUTPUT CLAMP = NTSC HSYNC OUTPUT INPUT = 500mV/DIV OUTPUT = 500mV/DIV TIMEBASE = 5ns/DIV FIGURE 23. PULSE RESPONSE, GAIN = 1 9 INPUT = 500mV/DIV OUTPUT = 1V/DIV TIMEBASE = 5ns/DIV FIGURE 24. PULSE RESPONSE, GAIN = 2 FN6253.0 September 24, 2007 ISL59451 Typical Performance Curves VCC = +5V, RL = 150Ω to GND, TA = +25°C, unless otherwise specified. (Continued) HIZ = 1V/DIV OUTPUT = 200mV/DIV TIMEBASE = 100ns/DIV HIZ HIZ OUTPUT HIZ = 1V/DIV OUTPUT = 200mV/DIV TIMEBASE = 100ns/DIV GAIN = 1 OUTPUT FIGURE 25. HIZ SWITCHING GLITCH, VIN = 0V, GAIN = 1 FIGURE 26. HIZ SWITCHING GLITCH, VIN = 0V, GAIN = 2 S1, S0 = 1V/DIV OUTPUT = 500mV/DIV TIMEBASE = 5ns/DIV HIZ = 1V/DIV OUTPUT = 200mV/DIV TIMEBASE = 100ns/DIV S1, S0 HIZ OUTPUT tHIZ-H-L OUTPUT tHIZ-L-H FIGURE 28. CHANNEL TO CHANNEL SWITCHING TIME, VIN = 1VDC 5 NORMALIZED MAGNITUDE (dB) NORMALIZED MAGNITUDE (dB) FIGURE 27. HIZ SWITCH TIMING, VIN = 1VDC VIN = 100mVP-P 0 CL = 7.4pF -5 CL = 0.6pF -10 -15 -20 0.1k tSW-H-L tSW-L-H 1M 10M 100M FREQUENCY (Hz) 1G FIGURE 29. SMALL SIGNAL GAIN vs FREQUENCY vs CL INTO 75Ω LOAD, GAIN = 1 10 10G 5 VIN = 700mVP-P 0 -5 CL = 7.4pF -10 CL = 0.6pF -15 -20 0.1k 1M 10M 100M FREQUENCY (Hz) 1G 10G FIGURE 30. LARGE SIGNAL GAIN vs FREQUENCY vs CL INTO 75Ω LOAD, GAIN = 2 FN6253.0 September 24, 2007 ISL59451 VCC = +5V, RL = 150Ω to GND, TA = +25°C, unless otherwise specified. (Continued) 5 NORMALIZED MAGNITUDE (dB) NORMALIZED MAGNITUDE (dB) Typical Performance Curves VIN = 100mVP-P 0 CL = 7.4pF -5 CL = 0.6pF -10 -15 -20 0.1k 1M 10M 100M FREQUENCY (Hz) 1G 10G FIGURE 31. SMALL SIGNAL GAIN vs FREQUENCY vs CL INTO 75Ω LOAD, GAIN = 2 5 VIN = 700mVP-P 0 CL = 7.4pF -5 CL = 0.6pF -10 -15 -20 0.1k 1M 10M 100M FREQUENCY (Hz) 1G 10G FIGURE 32. LARGE SIGNAL GAIN vs FREQUENCY vs CL INTO 75Ω LOAD, GAIN = 2 JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD - QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 3.0 1.2 2.5 POWER DISSIPATION (W) POWER DISSIPATION (W) 2.857W QFN32 θJA = 35°C/W 2.0 1.5 1.0 0.5 0 1.0 0.8 758mW 0.6 QFN32 θJA = 125°C/W 0.4 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 33. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 11 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 34. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN6253.0 September 24, 2007 ISL59451 Functional Block Diagram TABLE 1. CHANNEL SELECT LOGIC TABLE S0 AV2 S1 CX1 R0/G0/B0 R1/G1/B1 CX1 R2/G2/B2 HIZ OUTPUT 0 0 0 R0, G0, B0 0 1 0 R1, G1, B1 ROUT 1 0 0 R2, G2, B2 + GOUT 1 1 0 R3, G3, B3 X X 1 High Impedance, Inputs Disconnected A1 BOUT V1 CX1 R3/G3/B3 S0 1.6V - CX1 S1 S1 4kΩ A2 + - 40pF REF_G OR REF_RB CLAMP GND Pin Descriptions ISL59451 (32 LD QFN) PIN NAME EQUIVALENT CIRCUIT 1 R1 Circuit 1 Channel 1 Red/Pr/Chroma Input 2 B1 Circuit 1 Channel 1 Blue/Pb/Chroma Input 3 G1 Circuit 1 Channel 1 Green/Luma Input 4, 6, 10, 17, 22, 27, 32 GND Circuit 4 Ground 5, 20, 28 V+ Circuit 4 Positive Supply. Bypass to GND with 0.01µF and 1nF capacitors. 7 R2 Circuit 1 Channel 2 Red/Pr/Chroma Input DESCRIPTION 8 B2 Circuit 1 Channel 2 Blue/Pb/Chroma Input 9 G2 Circuit 1 Channel 2 Green/Luma Input 11 R3 Circuit 1 Channel 3 Red/Pr/Chroma Input 12 B3 Circuit 1 Channel 3 Blue/Pb/Chroma Input 13 G3 Circuit 1 Channel 3 Green/Luma Input 14 S1 Circuit 2 Channel selection pin MSB (binary logic code). This pin does not have internal pull-up or pull-down resistors. 15 S0 Circuit 2 Channel selection pin. LSB (binary logic code). This pin does not have internal pull-up or pull-down resistors. 16 CLAMP Circuit 2 Clamp/Store Logic Input. Logic ‘0’ selects the clamp DC restore state, logic ‘1’ selects the hold state. This pin does not have internal pull-up or pull-down resistors. 18 GOUT Circuit 3 Green/Luma Output 19 REF_G Green/Luma Reference. Green/Luma channel offset by this voltage during DC restore state. Reference voltage range is 0 to +3.0V. 21 BOUT 23 REF_RB 24 ROUT Circuit 3 Red Output 25 AV2 Circuit 2 Gain Set. Set to logic high for gain of x2 (+6dB), or set to logic low for a gain of x1 (+0dB). If left floating, an internal pull-down resistor pulls this pin low (300kΩ pull-down). 12 Circuit 3 Blue Output Red and Blue Reference. Red and blue channels offset by this voltage during DC restore state. Reference voltage range is 0 to +3.0V. FN6253.0 September 24, 2007 ISL59451 Pin Descriptions (Continued) ISL59451 (32 LD QFN) PIN NAME EQUIVALENT CIRCUIT 26 HIZ Circuit 2 Output disable (active high). Internal pull-down resistor ensures the device will be active with no connection to this pin. A logic high puts the outputs in a high impedance state. Use this state to control logic when more than one MUX-amp share the same video output line. During high impedance state, there is a 2kΩ pull-down present at each output. If left floating, an internal pull-down resistor pulls this pin low (300kΩ pull-down). 29 R0 Circuit 1 Channel 0 Red/Pr/Chroma Input 30 B0 Circuit 1 Channel 0 Blue/Pb/Chroma Input 31 G0 Circuit 1 Channel 0 Green/Luma Input - EP DESCRIPTION Exposed Pad. Connect to GND V+ V+ V+ * OUT LOGIC PIN IN * GND GND GND CIRCUIT 2 *Not Always Present. Refer to “Pin Description” CIRCUIT 1 CIRCUIT 3 V+ CAPACITIVELY COUPLED ESD CLAMP THERMAL HEAT SINK PAD ~1MΩ GND GND SUBSTRATE CIRCUIT 4 13 FN6253.0 September 24, 2007 ISL59451 Application Information ISL59451 VIN VOUT x2 *CL 2.1pF 50Ω OR 75Ω General The ISL59451 triple 4:1 MUX video driver features single +5V supply operation, high bandwidth and TTL/CMOS logic compatible gain select (AV2) of x1 (0dB) or x2 (+6dB). It also includes a DC restore function to set the blanking level of the output signal. RL 150Ω *CL Includes PCB trace capacitance FIGURE 35A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD ISL59451 VIN LCRIT x2 50Ω OR 75Ω CL RS CS RL FIGURE 35B. INTER-STAGE APPLICATION CIRCUIT The ISL59451 implements the video DC-restore function with a high performance gain-adjustable video amplifier and a nulling, sample-hold amplifier to establish a user defined DC reference voltage at the video amplifier output. A detailed description of the DC-restore function implemented in the ISL59451 can be found in application note AN1089, EL4089 and EL4390 DC-Restored Video Amplifier. The ISL59451 performs the same function with the exception that it is designed for single supply operation. Each of the three output channels feature DC restore functionality. Video Amplifier Operation (refer to “Functional Block Diagram” on page 12) ISL59451 VIN LCRIT x2 TEST EQUIPMENT RS 118Ω *CL 2.1pF 50Ω 86.6Ω 50Ω *CL Includes PCB trace capacitance FIGURE 35C. 150Ω TEST CIRCUIT WITH 50Ω LOAD The ISL59451 video amplifier (A1) is a voltage-feed, high performance video amplifier designed for +5V operation. The output stage is capable of swinging to within 15mV of the negative rail. The differential input stage contains an internal voltage reference that positions the non-inverting input DC level (V1) to ~1.6V higher than ground. This offset ensures that the amplifier input DC level is maintained within the common mode input voltage range. The amplifier non-inverting gain is given in Equation 1. RF ⎞ ⎛ V OUT = ( V IN+ – 1.6V ) • ⎜ 1 + --------⎟ R ⎝ G⎠ (EQ. 1) DC-Restore Amplifier ISL59451 VIN 50Ω OR 75Ω LCRIT x2 TEST EQUIPMENT RS 50Ω or 75Ω *CL 2.1pF 50Ω/75Ω *CL Includes PCB trace capacitance FIGURE 35D. BACKLOADED TEST CIRCUIT FOR 50Ω/75Ω VIDEO CABLE APPLICATION FIGURE 35. AC TEST CIRCUITS AC Test Circuits Figures 35A and 35B illustrate the optimum output load for testing AC performance at 150Ω loads. Figure 35C illustrates how to use the optimal 150Ω load for a 50Ω cable. Figure 35D illustrates the optimum output load for 50Ω and 75Ω cable-driving. 14 (refer to “Functional Block Diagram” on page 12) The DC-restore circuit contains a voltage reference amplifier and an analog switch function that closes the DC-restore loop under control of the CLAMP logic input. The A2 amplifier output stage operates in a current-feedback mode with a source capability of 860µA (Typ). A logic “0” at the CLAMP input closes switch S1, which closes the DC-restore loop. The video input AC coupling capacitor, CX1, acts as a DC hold capacitor (through the 75Ω termination resistor) to average the current-source output of amplifier A2. When the DC-restore loop has reached equilibrium, the DC voltage stored on CX1 will be the value required to set the voltages at A1 (VOUT) and A2 (VIN+) according to Equations 2 and 3: V OUT (DC) = V REF (EQ. 2) V IN+ = V OUT (DC) + 1.6V (EQ. 3) FN6253.0 September 24, 2007 ISL59451 Therefore, if VREF is set to 0V (GND); VOUT = 15mV, and the DC voltage stored on CX1 is ~1.6V. The CX1 capacitor value is chosen from the system requirements. A typical DC-restore application using an NTSC video horizontal sync to drive the CLAMP pin will result in a 62µs hold time. The typical input bias current to the video amplifier is 1.2µA, so for a 62µs hold time, and a 0.01µF capacitor, the output voltage drift is 7.5mV in one line. The restore amplifier can provide a typical source current of 860µA to charge capacitor CX1, so with a 1.2µs sampling time, the output can be corrected by 36mV in each line. Using a smaller value of CX1 increases both the voltage that can be corrected, as well as the droop while being held. Likewise, using a larger value of CX1, reduces the correction and droop voltages. A sample of charging and droop rates are shown in Table 2. TABLE 2. TABLE OF CHARGE STORAGE CAPACITOR VS DROOP CHARGING RATES (NOTE) AC Design Considerations High speed current-feed amplifiers are sensitive to capacitance at the inverting input and output terminals. Capacitance at the output terminal increases gain peaking and overshoot. The AC response of the ISL59451 is optimized for a total output capacitance of 2.1pF with a load of 150Ω (Figure 35A). When PCB trace capacitance and component capacitance exceed 2pF, overshoot becomes strongly dependent on the input pulse amplitude and slew rate. Increasing levels of output capacitance reduce stability, resulting in increased overshoot and settling time. PC board trace length (LCRIT) should be kept to a minimum in order to minimize output capacitance. At 500MHz, trace lengths approaching 1” begin exhibiting transmission line behavior and may cause excessive ringing if controlled impedance traces are not used. Figure 35B shows the optimum inter-stage circuit when the total output trace length is less than the critical length of the highest signal frequency. As a general rule of thumb the trace lengths should be less than one-tenth of the wavelength of the highest frequency component in the signal. Equation 6 shows an approximate way to calculate LCRIT in meters. CAP VALUE (nF) DROOP IN 62µs (mV) CHARGE IN 1.2µs (mV) CHARGE IN 4µs (mV) 10 7.5 103 344 33 2.3 32.5 103 c L CRIT ≤ -------------------------------------------10 × f MAX × ε R 100 0.75 10.3 34 c = speed of light (3 x 10^8 m/s) (EQ. 6) fMAX = maximum frequency component IB V DROOP = ----------------------------- × ( Line Time – Sample Time ) CAP Value I CLAMP V CHARGE = ----------------------------- × ( Sample Time ) CAP Value (EQ. 4) (EQ. 5) Figure 36 shows the test setup for measuring the DC Restore’s response to an input DC step shown in Figures 21 and 22. 1Hz SQUARE WAVE 500Ω NTSC VIDEO 75Ω 0.1µF ISL59451 CLAMP 75Ω NTSC HSYNC TIMING FIGURE 36. DC STEP RESPONSE 15 OUTPUT 150Ω εR = relative dielectric of board material (e.g. FR4 = 4.2) For applications where inter-stage distances are long but pulse response is not critical, capacitor CS can be added to low values of RS to form a low-pass filter to dampen pulse overshoot. This approach avoids the need for the large gain correction required by the -6dB attenuation of the back-loaded controlled impedance interconnect. Load resistor RL is still required but can be 500Ω or greater, resulting in a much smaller attenuation factor. For applications where pulse response is critical and where inter-stage distances exceed LCRIT, the circuit shown in Figure 35C is recommended. Resistor RS constrains the capacitance seen by the amplifier output to the trace capacitance betweeen the output pin and the resistor. Therefore, RS should be placed as close to the ISL59451 output pin as possible. For inter-stage distances much greater than LCRIT, the back-loaded circuit shown in Figure 35D should be used with controlled impedance PCB lines, with RS and RL equal to the controlled impedance. Control Signals S0, S1, HIZ, CLAMP, and AV2 are binary coded, TTL/CMOS compatible control inputs. The S0, S1 pins select the inputs. All three amplifiers are switched simultaneously from their respective inputs. When HIZ is pulled high, it puts the outputs in a high-impedance state and disconnects the video inputs. FN6253.0 September 24, 2007 ISL59451 CLAMP enables and disables the DC restore circuitry. For control signal rise and fall times less than 10ns, the use of termination resistors on the control lines close to the part may be necessary to prevent reflections and to minimize transients coupled to the output. See Table 1 for the S1, S0 selection states. • Match channel-to-channel analog I/O trace lengths and layout symmetry. This will minimize propagation delay mismatches. High-Impedance State • Put the proper termination resistors in their optimum location as close to the device as possible. An internal pull-down resistor ensures the device will be active with no connection to the HIZ pin. The HIZ state is established within approximately 25ns by placing a logic high (>2V) on the HIZ pin. If the HIZ state is selected, the output impedance is ~2000Ω (Figure 6). The supply current during this state is reduced to ~3mA. Limiting the Output Current No output short circuit current limit exists on these parts. All applications need to limit the output current to less than 50mA. Adequate thermal heat sinking of the parts is also required. PC Board Layout The AC performance of this circuit depends greatly on the care taken in designing the PC board. The following are recommendations to achieve optimum high frequency performance from your PC board. • Use low inductance components, such as chip resistors and chip capacitors whenever possible. • Minimize signal trace lengths. Trace inductance and capacitance can easily limit circuit performance. Avoid sharp corners; use rounded corners when possible. Vias in the signal lines add inductance at high frequency and should be avoided. PCB traces longer than 1" begin to exhibit transmission line characteristics with signal rise/fall times of 1ns or less. To maintain frequency performance with longer traces, use striplines. • All signal I/O lines should be routed over continuous ground planes (i.e. no split planes or PCB gaps under these lines). • When testing, use good quality connectors and cables, matching cable types and keeping cable lengths to a minimum. • Decouple well, using aminimum of 2 power supply decoupling capacitors (1000pF, 0.01µF), placed as close to the devices as possible. Avoid vias between the capacitor and the device because vias adds unwanted inductance. Larger caps can be farther away. When vias are required in a layout, they should be routed as far away from the device as possible. The QFN Package Requires Additional PCB Layout Rules for the Thermal Pad The thermal pad is electrically connected to GND through the high resistance IC substrate. Its primary function is to provide heat sinking for the IC. Maximum AC performance is achieved if the thermal pad is attached to a dedicated decoupled layer in a multi-layered PC board. In cases where a dedicated layer is not possible, AC performance may be reduced at upper frequencies. • The thermal pad requirements are proportional to power dissipation and ambient temperature. A dedicated layer (oftern the ground plane) eliminates the need for individual thermal pad area. When a dedicated layer is not possible, a 1”x1” pad area is sufficient for an ISL59451 dissipating 0.5W at +50°C ambient. Pad area requirements should be evaluated according to the maximum ambient temperature, the maximum supply current (including worst case signals + loads), and the thermal characteristic of the PCB. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 16 FN6253.0 September 24, 2007 ISL59451 Package Outline Drawing L32.5x5 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 02/07 4X 3.5 5.00 28X 0.50 A B 6 PIN 1 INDEX AREA 6 PIN #1 INDEX AREA 32 25 1 5.00 24 3 .10 ± 0 . 15 17 (4X) 8 0.15 9 16 TOP VIEW 0.10 M C A B + 0.07 32X 0.40 ± 0.10 4 32X 0.23 - 0.05 BOTTOM VIEW SEE DETAIL "X" 0.10 C 0 . 90 ± 0.1 C BASE PLANE SEATING PLANE 0.08 C ( 4. 80 TYP ) ( ( 28X 0 . 5 ) SIDE VIEW 3. 10 ) (32X 0 . 23 ) C 0 . 2 REF 5 ( 32X 0 . 60) 0 . 00 MIN. 0 . 05 MAX. DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature. 17 FN6253.0 September 24, 2007