HFA1145 ® Data Sheet June 1, 2006 330MHz, Low Power, Current Feedback Video Operational Amplifier with Output Disable The HFA1145 is a high speed, low power current feedback amplifier built with Intersil’s proprietary complementary bipolar UHF-1 process. FN3955.5 Features • Low Supply Current . . . . . . . . . . . . . . . . . . . . . . . . 5.8mA • High Input Impedance . . . . . . . . . . . . . . . . . . . . . . . 1MΩ • Wide -3dB Bandwidth. . . . . . . . . . . . . . . . . . . . . . 330MHz • Very Fast Slew Rate. . . . . . . . . . . . . . . . . . . . . . 1000V/μs This amplifier features a TTL/CMOS compatible disable control, pin 8, which when pulled low reduces the supply current and forces the output into a high impedance state. This allows easy implementation of simple, low power video switching and routing systems. Component and composite video systems also benefit from this op amp’s excellent gain flatness, and good differential gain and phase specifications. • Gain Flatness (to 75MHz) . . . . . . . . . . . . . . . . . . ±0.1dB Multiplexed A/D applications will also find the HFA1145 useful as the A/D driver/multiplexer. • Pb-Free Plus Anneal Available (RoHS Compliant) The HFA1145 is a low power, high performance upgrade for the CLC410. For Military grade product, please refer to the HFA1145/883 data sheet. PART MARKING TEMP. RANGE (°C) • Differential Phase . . . . . . . . . . . . . . . . . . . . . 0.03 Degrees • Output Enable/Disable Time . . . . . . . . . . . . . 180ns/35ns • Pin Compatible Upgrade for CLC410 Applications • Flash A/D Drivers • Video Switching and Routing • Professional Video Processing • Video Digitizing Boards/Systems Ordering Information PART NUMBER (BRAND) • Differential Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.02% • Multimedia Systems PACKAGE PKG. DWG. # HFA1145IB 1145IB -40 to 85 8 Ld SOIC M8.15 HFA1145IBZ (Note) 1145IBZ -40 to 85 8 Ld SOIC (Pb-free) M8.15 HFA1145IP HFA1145IP -40 to 85 8 Ld PDIP E8.3 HFA1145IPZ (Note) HFA1145IPZ -40 to 85 8 Ld PDIP* (Pb-free) E8.3 HFA11XXEVAL DIP Evaluation Board for High Speed Op Amps Note: Requires a SOIC-to-DIP adapter. See “Evaluation Board” section inside. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. • RGB Preamps • Medical Imaging • Hand Held and Miniaturized RF Equipment • Battery Powered Communications Pinout HFA1145 (SOIC) TOP VIEW NC 1 8 DISABLE -IN 2 - 7 V+ +IN 3 + 6 OUT V- 4 5 NC *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1999, 2004, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HFA1145 Absolute Maximum Ratings Thermal Information Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V Output Current (Note 1) . . . . . . . . . . . . . . . . . Short Circuit Protected 30mA Continuous 60mA ≤ 50% Duty Cycle ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>600V Thermal Resistance (Typical, Note 2) θJA (°C/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Maximum Junction Temperature (Die Only) . . . . . . . . . . . . . . . . 175°C Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C (Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Output is short circuit protected to ground. Brief short circuits to ground will not degrade reliability, however continuous (100% duty cycle) output current must not exceed 30mA for maximum reliability. 2. θJA is measured with the component mounted on an evaluation PC board in free air. VSUPPLY = ±5V, AV = +1, RF = 510Ω, RL = 100Ω, Unless Otherwise Specified Electrical Specifications PARAMETER (NOTE 3) TEST LEVEL TEMP. (°C) MIN TYP MAX UNITS A 25 - 2 5 mV A Full - 3 8 mV B Full - 1 10 μV/°C ΔVCM = ±1.8V A 25 47 50 - dB ΔVCM = ±1.8V A 85 45 48 - dB ΔVCM = ±1.2V A -40 45 48 - dB TEST CONDITIONS INPUT CHARACTERISTICS Input Offset Voltage Average Input Offset Voltage Drift Input Offset Voltage Common-Mode Rejection Ratio Input Offset Voltage Power Supply Rejection Ratio ΔVPS = ±1.8V A 25 50 54 - dB ΔVPS = ±1.8V A 85 47 50 - dB ΔVPS = ±1.2V A -40 47 50 - dB A 25 - 6 15 μA A Full - 10 25 μA B Full - 5 60 nA/°C ΔVPS = ±1.8V A 25 - 0.5 1 μA/V ΔVPS = ±1.8V A 85 - 0.8 3 μA/V ΔVPS = ±1.2V A -40 - 0.8 3 μA/V ΔVCM = ±1.8V A 25 0.8 1.2 - MΩ ΔVCM = ±1.8V A 85 0.5 0.8 - MΩ ΔVCM = ±1.2V A -40 0.5 0.8 - MΩ A 25 - 2 7.5 μA A Full - 5 15 μA B Full - 60 200 nA/°C A 25 - 3 6 μA/V Non-Inverting Input Bias Current Non-Inverting Input Bias Current Drift Non-Inverting Input Bias Current Power Supply Sensitivity Non-Inverting Input Resistance Inverting Input Bias Current Inverting Input Bias Current Drift ΔVCM = ±1.8V Inverting Input Bias Current Common-Mode Sensitivity 2 ΔVCM = ±1.8V A 85 - 4 8 μA/V ΔVCM = ±1.2V A -40 - 4 8 μA/V FN3955.5 June 1, 2006 HFA1145 VSUPPLY = ±5V, AV = +1, RF = 510Ω, RL = 100Ω, Unless Otherwise Specified (Continued) Electrical Specifications (NOTE 3) TEST LEVEL TEMP. (°C) MIN TYP MAX UNITS ΔVPS = ±1.8V A 25 - 2 5 μA/V ΔVPS = ±1.8V A 85 - 4 8 μA/V ΔVPS = ±1.2V A -40 - 4 8 μA/V Inverting Input Resistance C 25 - 60 - Ω Input Capacitance C 25 - 1.6 - pF Input Voltage Common Mode Range (Implied by VIO CMRR, +RIN, and -IBIAS CMS tests) A 25, 85 ±1.8 ±2.4 - V A -40 ±1.2 ±1.7 - V PARAMETER TEST CONDITIONS Inverting Input Bias Current Power Supply Sensitivity Input Noise Voltage Density (Note 6) f = 100kHz B 25 - 3.5 - nV/√Hz Non-Inverting Input Noise Current Density (Note 6) f = 100kHz B 25 - 2.5 - pA/√Hz Inverting Input Noise Current Density (Note 6) f = 100kHz B 25 - 20 - pA/√Hz AV = -1 C 25 - 500 - kΩ B 25 - 270 - MHz B Full - 240 - MHz AV = -1, RF = 425Ω B 25 - 300 - MHz AV = +2 B 25 - 330 - MHz B Full - 260 - MHz B 25 - 130 - MHz B Full - 90 - MHz TRANSFER CHARACTERISTICS Open Loop Transimpedance Gain AC CHARACTERISTICS RF = 510Ω, Unless Otherwise Specified -3dB Bandwidth (VOUT = 0.2VP-P, Note 6) AV = +1, +RS = 510Ω AV = +10, RF = 180Ω Full Power Bandwidth (VOUT = 5VP-P at AV = +2/-1, 4VP-P at AV = +1, Note 6) AV = +1, +RS = 510Ω B 25 - 135 - MHz AV = -1 B 25 - 140 - MHz AV = +2 B 25 - 115 - MHz To 25MHz B 25 - ±0.03 - dB B Full - ±0.04 - dB B 25 - ±0.11 - dB B Full - ±0.22 - dB Gain Flatness To 25MHz (AV = +1, +RS = 510Ω, VOUT = 0.2VP-P, Note 6) To 75MHz B 25 - ±0.03 - dB B 25 - ±0.09 - dB Minimum Stable gain A Full - 1 - V/V A 25 ±3 ±3.4 - V A Full ±2.8 ±3 - V A 25, 85 50 60 - mA A -40 28 42 - mA B 25 - 90 - mA B 25 - 0.08 - Ω Gain Flatness (AV = +2, VOUT = 0.2VP-P, Note 6) To 75MHz OUTPUT CHARACTERISTICS AV = +2, RF = 510Ω, Unless Otherwise Specified Output Voltage Swing (Note 6) AV = -1, RL = 100Ω Output Current (Note 6) AV = -1, RL = 50Ω Output Short Circuit Current Closed Loop Output Impedance (Note 6) 3 DC FN3955.5 June 1, 2006 HFA1145 VSUPPLY = ±5V, AV = +1, RF = 510Ω, RL = 100Ω, Unless Otherwise Specified (Continued) Electrical Specifications PARAMETER TEST CONDITIONS (NOTE 3) TEST LEVEL TEMP. (°C) MIN TYP MAX UNITS Second Harmonic Distortion (VOUT = 2VP-P, Note 6) 10MHz B 25 - -48 - dBc 20MHz B 25 - -44 - dBc Third Harmonic Distortion (VOUT = 2VP-P, Note 6) 10MHz B 25 - -50 - dBc 20MHz B 25 - -45 - dBc Reverse Isolation (S12, Note 6) 30MHz B 25 - -55 - dB B 25 - 1.1 - ns B Full - 1.4 - ns TRANSIENT CHARACTERISTICS AV = +2, RF = 510Ω, Unless Otherwise Specified Rise and Fall Times VOUT = 0.5VP-P Overshoot (Note 4) (VOUT = 0 to 0.5V, VIN tRISE = 1ns) +OS B 25 - 3 - % -OS B 25 - 5 - % Overshoot (Note 4) (VOUT = 0.5VP-P, VIN tRISE = 1ns) +OS B 25 - 3 - % -OS B 25 - 11 - % Slew Rate (VOUT = 4VP-P, AV = +1, +RS = 510Ω) +SR B 25 - 1000 - V/μs B Full - 975 - V/μs B 25 - 650 - V/μs B Full - 580 - V/μs B 25 - 1400 - V/μs B Full - 1200 - V/μs B 25 - 800 - V/μs B Full - 700 - V/μs B 25 - 2100 - V/μs B Full - 1900 - V/μs B 25 - 1000 - V/μs B Full - 900 - V/μs To 0.1% B 25 - 15 - ns To 0.05% B 25 - 23 - ns To 0.02% B 25 - 30 - ns VIN = ±2V B 25 - 8.5 - ns -SR (Note 5) +SR Slew Rate (VOUT = 5VP-P, AV = +2) -SR (Note 5) +SR Slew Rate (VOUT = 5VP-P, AV = -1) -SR (Note 5) Settling Time (VOUT = +2V to 0V step, Note 6) Overdrive Recovery Time VIDEO CHARACTERISTICS AV = +2, RF = 510Ω, Unless Otherwise Specified Differential Gain (f = 3.58MHz) RL = 150Ω B 25 - 0.02 - % RL = 75Ω B 25 - 0.03 - % Differential Phase (f = 3.58MHz) RL = 150Ω B 25 - 0.03 - Degrees RL = 75Ω B 25 - 0.05 - Degrees VDISABLE = 0V A Full - 3 4 mA DISABLE CHARACTERISTICS Disabled Supply Current DISABLE Input Logic Low A Full - - 0.8 V DISABLE Input Logic High A 25, 85 2.0 - - V A -40 2.4 - - V A Full - 100 200 μA DISABLE Input Logic Low Current 4 VDISABLE = 0V FN3955.5 June 1, 2006 HFA1145 VSUPPLY = ±5V, AV = +1, RF = 510Ω, RL = 100Ω, Unless Otherwise Specified (Continued) Electrical Specifications PARAMETER TEST CONDITIONS (NOTE 3) TEST LEVEL TEMP. (°C) MIN TYP MAX UNITS DISABLE Input Logic High Current VDISABLE = 5V A Full - 1 15 μA Output Disable Time (Note 6) VIN = ±1V, VDISABLE = 2.4V to 0V B 25 - 35 - ns Output Enable Time (Note 6) VIN = ±1V, VDISABLE = 0V to 2.4V B 25 - 180 - ns B 25 - 2.5 - pF A Full - 3 10 μA Disabled Output Capacitance VDISABLE = 0V Disabled Output Leakage VDISABLE = 0V, VIN = VOUT = ±3V Off Isolation (VDISABLE = 0V, VIN = 1VP-P, Note 6) At 5MHz B 25 - -75 - dB At 25MHz B 25 - -60 - dB Power Supply Range C 25 ±4.5 - ±5.5 V Power Supply Current (Note 6) A 25 - 5.8 6.1 mA A Full - 5.9 6.3 mA 2V, ± POWER SUPPLY CHARACTERISTICS NOTES: 3. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only. 4. Undershoot dominates for output signal swings below GND (e.g. 0.5VP-P), yielding a higher overshoot limit compared to the VOUT = 0 to 0.5V condition. See the “Application Information” section for details. 5. Slew rates are asymmetrical if the output swings below GND (e.g. a bipolar signal). Positive unipolar output signals have symmetric positive and negative slew rates comparable to the +SR specification. See the “Application Information” section, and the pulse response graphs for details. 6. See Typical Performance Curves for more information. Application Information Optimum Feedback Resistor Although a current feedback amplifier’s bandwidth dependency on closed loop gain isn’t as severe as that of a voltage feedback amplifier, there can be an appreciable decrease in bandwidth at higher gains. This decrease may be minimized by taking advantage of the current feedback amplifier’s unique relationship between bandwidth and RF. All current feedback amplifiers require a feedback resistor, even for unity gain applications, and RF, in conjunction with the internal compensation capacitor, sets the dominant pole of the frequency response. Thus, the amplifier’s bandwidth is inversely proportional to RF. The HFA1145 design is optimized for RF = 510Ω at a gain of +2. Decreasing RF decreases stability, resulting in excessive peaking and overshoot (Note: Capacitive feedback will cause the same problems due to the feedback impedance decrease at higher frequencies). At higher gains, however, the amplifier is more stable so RF can be decreased in a trade-off of stability for bandwidth. The table below lists recommended RF values for various gains, and the expected bandwidth. For a gain of +1, a resistor (+RS) in series with +IN is required to reduce gain peaking and increase stability. GAIN (ACL) RF (Ω) BANDWIDTH (MHz) -1 425 300 +1 510 (+RS = 510Ω) 270 +2 510 330 +5 200 300 +10 180 130 Non-inverting Input Source Impedance For best operation, the DC source impedance seen by the non-inverting input should be ≥50Ω. This is especially important in inverting gain configurations where the noninverting input would normally be connected directly to GND. DISABLE Input TTL Compatibility The HFA1145 derives an internal GND reference for the digital circuitry as long as the power supplies are symmetrical about GND. With symmetrical supplies the digital switching threshold (VTH = (VIH + VIL)/2 = (2.0 + 0.8)/2) is 1.4V, which ensures the TTL compatibility of the DISABLE input. If asymmetrical supplies (e.g. +10V, 0V) are utilized, the switching threshold becomes: V+ + VV TH = ------------------- + 1.4V 2 and the VIH and VIL levels will be VTH ± 0.6V, respectively. 5 FN3955.5 June 1, 2006 HFA1145 The die version of the HFA1145 provides the user with a GND pad for setting the disable circuitry GND reference. With symmetrical supplies the GND pad may be left unconnected, or tied directly to GND. If asymmetrical supplies (e.g. +10V, 0V) are utilized, and TTL compatibility is desired, die users must connect the GND pad to GND. With an external GND, the DISABLE input is TTL compatible regardless of supply voltage utilized. Pulse Undershoot and Asymmetrical Slew Rates The HFA1145 utilizes a quasi-complementary output stage to achieve high output current while minimizing quiescent supply current. In this approach, a composite device replaces the traditional PNP pulldown transistor. The composite device switches modes after crossing 0V, resulting in added distortion for signals swinging below ground, and an increased undershoot on the negative portion of the output waveform (See Figures 5, 8, and 11). This undershoot isn’t present for small bipolar signals, or large positive signals. Another artifact of the composite device is asymmetrical slew rates for output signals with a negative voltage component. The slew rate degrades as the output signal crosses through 0V (See Figures 5, 8, and 11), resulting in a slower overall negative slew rate. Positive only signals have symmetrical slew rates as illustrated in the large signal positive pulse response graphs (See Figures 4, 7, and 10). PC Board Layout This amplifier’s frequency response depends greatly on the care taken in designing the PC board. The use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must! Attention should be given to decoupling the power supplies. A large value (10μF) tantalum in parallel with a small value (0.1μF) chip capacitor works well in most cases. Terminated microstrip signal lines are recommended at the device’s input and output connections. Capacitance, parasitic or planned, connected to the output must be minimized, or isolated as discussed in the next section. Care must also be taken to minimize the capacitance to ground at the amplifier’s inverting input (-IN), as this capacitance causes gain peaking, pulse overshoot, and if large enough, instability. To reduce this capacitance, the designer should remove the ground plane under traces connected to -IN, and keep connections to -IN as short as possible. An example of a good high frequency layout is the Evaluation Board shown in Figure 2. 6 Driving Capacitive Loads Capacitive loads, such as an A/D input, or an improperly terminated transmission line will degrade the amplifier’s phase margin resulting in frequency response peaking and possible oscillations. In most cases, the oscillation can be avoided by placing a resistor (RS) in series with the output prior to the capacitance. Figure 1 details starting points for the selection of this resistor. The points on the curve indicate the RS and CL combinations for the optimum bandwidth, stability, and settling time, but experimental fine tuning is recommended. Picking a point above or to the right of the curve yields an overdamped response, while points below or left of the curve indicate areas of underdamped performance. RS and CL form a low pass network at the output, thus limiting system bandwidth well below the amplifier bandwidth of 270MHz (for AV = +1). By decreasing RS as CL increases (as illustrated in the curves), the maximum bandwidth is obtained without sacrificing stability. In spite of this, the bandwidth decreases as the load capacitance increases. For example, at AV = +1, RS = 62Ω, CL = 40pF, the overall bandwidth is limited to 180MHz, and bandwidth drops to 75MHz at AV = +1, RS = 8Ω, CL = 400pF. 50 SERIES OUTPUT RESISTANCE (Ω) Optional GND Pad (Die Use Only) for TTL Compatibility 40 30 20 AV = +1 AV = +2 10 0 0 50 100 200 300 150 250 LOAD CAPACITANCE (pF) 350 400 FIGURE 1. RECOMMENDED SERIES OUTPUT RESISTOR vs LOAD CAPACITANCE Evaluation Board The performance of the HFA1145 may be evaluated using the HFA11XX Evaluation Board and a SOIC to DIP adaptor like the Aries Electronics Part Number 14-350000-10. The layout and schematic of the board are shown in Figure 2. The VH connection may be used to exercise the DISABLE pin, but note that this connection has no 50Ω termination. To order evaluation boards (part number HFA11XXEVAL), please contact your local sales office. FN3955.5 June 1, 2006 HFA1145 VH 1 +IN OUT VL V+ VGND FIGURE 2A. TOP LAYOUT FIGURE 2B. TOP LAYOUT 510 510 VH R1 50Ω IN 10μF 0.1μF 1 8 2 7 3 6 4 5 +5V 50Ω OUT GND -5V 10μF 0.1μF VL GND FIGURE 2. EVALUATION BOARD SCHEMATIC AND LAYOUT Typical Performance Curves 200 3.0 AV = +1 +RS = 510Ω 2.5 100 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (mV) 150 VSUPPLY = ±5V, RF = 510Ω, TA = 25°C, RL = 100Ω, Unless Otherwise Specified 50 0 -50 -100 AV = +1 +RS = 510Ω 2.0 1.5 1.0 0.5 0 -0.5 -150 -1.0 -200 TIME (5ns/DIV.) FIGURE 3. SMALL SIGNAL PULSE RESPONSE 7 TIME (5ns/DIV.) FIGURE 4. LARGE SIGNAL POSITIVE PULSE RESPONSE FN3955.5 June 1, 2006 HFA1145 Typical Performance Curves 2.0 200 AV = +1 +RS = 510Ω AV = +2 150 1.0 OUTPUT VOLTAGE (mV) OUTPUT VOLTAGE (V) 1.5 VSUPPLY = ±5V, RF = 510Ω, TA = 25°C, RL = 100Ω, Unless Otherwise Specified (Continued) 0.5 0 -0.5 -1.0 -1.5 100 50 0 -50 -100 -150 -2.0 -200 TIME (5ns/DIV.) TIME (5ns/DIV.) FIGURE 5. LARGE SIGNAL BIPOLAR PULSE RESPONSE FIGURE 6. SMALL SIGNAL PULSE RESPONSE 3.0 2.0 AV = +2 2.5 1.5 2.0 1.0 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) AV = +2 1.5 1.0 0.5 0 -0.5 0.5 0 -0.5 -1.0 -1.5 -1.0 -2.0 TIME (5ns/DIV.) TIME (5ns/DIV.) FIGURE 7. LARGE SIGNAL POSITIVE PULSE RESPONSE FIGURE 8. LARGE SIGNAL BIPOLAR PULSE RESPONSE 200 2.5 100 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (mV) 150 3.0 AV = +10 RF = 180Ω 50 0 -50 -100 AV = +10 RF = 180Ω 2.0 1.5 1.0 0.5 0 -0.5 -150 -1.0 -200 TIME (5ns/DIV.) FIGURE 9. SMALL SIGNAL PULSE RESPONSE 8 TIME (5ns/DIV.) FIGURE 10. LARGE SIGNAL POSITIVE PULSE RESPONSE FN3955.5 June 1, 2006 HFA1145 Typical Performance Curves VSUPPLY = ±5V, RF = 510Ω, TA = 25°C, RL = 100Ω, Unless Otherwise Specified (Continued) 2.0 AV = +10 RF = 180Ω DISABLE 800mV/DIV. (0.4V to 2.4V) 1.0 0.5 0 OUT 400mV/DIV. -0.5 -1.0 0V -1.5 AV = +1, VIN = 1V -2.0 TIME (5ns/DIV.) TIME (50ns/DIV.) 0 VOUT = 200mVP-P +RS = 510Ω (+1) +RS = 0Ω (-1) AV = +1 AV = -1 -3 0 AV = -1 90 180 AV = +1 0.3 1 10 FREQUENCY (MHz) 100 270 NORMALIZED GAIN (dB) 3 FIGURE 12. OUTPUT ENABLE AND DISABLE RESPONSE NORMALIZED PHASE (DEGREES) GAIN (dB) FIGURE 11. LARGE SIGNAL BIPOLAR PULSE RESPONSE AV = +2 3 0 AV = +10 -3 AV = +5 AV = +2 0.3 VOUT = 200mVP-P 0 VOUT = 1.5VP-P -3 VOUT = 5VP-P VOUT = 200mVP-P 0 90 VOUT = 1.5VP-P 180 270 VOUT = 5VP-P 0.3 1 10 FREQUENCY (MHz) 100 500 FIGURE 15. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES 9 NORMALIZED GAIN (dB) AV = +2 3 180 AV = +10 10 FREQUENCY (MHz) 100 270 500 FIGURE 14. FREQUENCY RESPONSE PHASE (DEGREES) NORMALIZED GAIN (dB) FIGURE 13. FREQUENCY RESPONSE 1 90 AV = +5 VOUT = 200mVP-P RF = 510Ω (+2) RF = 200Ω (+5) RF = 180Ω (+10) 500 0 PHASE (DEGREES) OUTPUT VOLTAGE (V) 1.5 3 AV = -1 0 VOUT = 4VP-P (+1) VOUT = 5VP-P (-1, +2) +RS = 510Ω (+1) -3 AV = +1 AV = +2 1 10 100 200 FREQUENCY (MHz) FIGURE 16. FULL POWER BANDWIDTH FN3955.5 June 1, 2006 HFA1145 VOUT = 200mVP-P 3 VSUPPLY = ±5V, RF = 510Ω, TA = 25°C, RL = 100Ω, Unless Otherwise Specified (Continued) RL = 500Ω AV = +2 RL = 1kΩ 500 AV = +2 0 RL = 100Ω RL = 50Ω RL = 100Ω 0 90 RL = 1kΩ RL = 500Ω 180 270 0.3 1 10 FREQUENCY (MHz) 100 BANDWIDTH (MHz) -3 RF = 180Ω (+10) +RS = 510Ω (+1) AV = +1 300 200 AV = +10 100 0 -100 500 -50 0 50 100 150 TEMPERATURE (°C) FIGURE 17. FREQUENCY RESPONSE FOR VARIOUS LOAD RESISTORS FIGURE 18. -3dB BANDWIDTH vs TEMPERATURE -30 OFF ISOLATION (dB) VOUT = 200mVP-P +RS = 510Ω (+1) 0.25 NORMALIZED GAIN (dB) VOUT = 200mVP-P 400 RL = 50Ω PHASE (DEGREES) NORMALIZED GAIN (dB) Typical Performance Curves 0.20 0.15 0.10 AV = +2 0.05 AV = +2 VIN = 1VP-P -40 -50 -60 -70 -80 -90 0 AV = +1 -0.05 -0.10 1 10 FREQUENCY (MHz) 0.3 75 1 FIGURE 19. GAIN FLATNESS 100 FIGURE 20. OFF ISOLATION -40 -50 VOUT = 2VP-P AV = +2 AV = +1, +2 OUTPUT IMPEDANCE (Ω) REVERSE ISOLATION (dB) 10 FREQUENCY (MHz) -60 AV = -1 -70 -80 -90 0.3 1 10 FREQUENCY (MHz) FIGURE 21. REVERSE ISOLATION (S12) 10 100 1K 100 10 1 0.1 0.01 0.3 1 10 100 FREQUENCY (MHz) 1000 FIGURE 22. ENABLED OUTPUT IMPEDANCE FN3955.5 June 1, 2006 HFA1145 Typical Performance Curves VSUPPLY = ±5V, RF = 510Ω, TA = 25°C, RL = 100Ω, Unless Otherwise Specified (Continued) -30 AV = +2 0.8 AV = +2 VOUT = 2V -40 DISTORTION (dBc) SETTLING ERROR (%) 0.6 0.4 0.2 0.1 0 -0.2 -0.4 20MHz -50 10MHz -60 -0.6 -0.8 -70 3 8 13 18 23 28 TIME (ns) 33 38 43 -5 48 5 3.6 AV = +2 OUTPUT VOLTAGE (V) 3.5 -40 20MHz -50 10MHz -60 |-VOUT| (RL= 100Ω) AV = -1 +VOUT (RL= 100Ω) 3.4 3.3 3.2 3.1 +VOUT (RL= 50Ω) 3.0 2.9 2.8 |-VOUT| (RL= 50Ω) 2.7 2.6 -50 -70 0 5 OUTPUT POWER (dBm) 10 15 -25 0 25 50 75 100 125 TEMPERATURE (°C) FIGURE 25. THIRD HARMONIC DISTORTION vs POUT FIGURE 26. OUTPUT VOLTAGE vs TEMPERATURE 100 10 10 ENI INI+ POWER SUPPLY CURRENT (mA) INI- 6.1 NOISE CURRENT (pA/√Hz) 100 NOISE VOLTAGE (nV/√Hz) 15 FIGURE 24. SECOND HARMONIC DISTORTION vs POUT -30 -5 10 OUTPUT POWER (dBm) FIGURE 23. SETTLING RESPONSE DISTORTION (dBc) 0 6.0 5.9 5.8 5.7 5.6 1 0.1 1 1 10 100 FREQUENCY (kHz) FIGURE 27. INPUT NOISE CHARACTERISTICS 11 3.5 4 4.5 5 5.5 6 6.5 7 7.5 POWER SUPPLY VOLTAGE (±V) FIGURE 28. SUPPLY CURRENT vs SUPPLY VOLTAGE FN3955.5 June 1, 2006 HFA1145 Die Characteristics PASSIVATION: DIE DIMENSIONS: Type: Nitride Thickness: 4kÅ ±0.5kÅ 59 mils x 59 mils x 19 mils 1500μm x 1500μm x 483μm TRANSISTOR COUNT: METALLIZATION: 75 Type: Metal 1: AICu(2%)/TiW Thickness: Metal 1: 8kÅ ±0.4kÅ Type: Metal 2: AICu(2%) Thickness: Metal 2: 16kÅ ±0.8kÅ SUBSTRATE POTENTIAL (Powered Up): Floating (Recommend Connection to V-) Metallization Mask Layout HFA1145 DISABLE -IN V+ OUT +IN V- OPTIONAL GND (NOTE) NOTE: This pad is not bonded out on packaged units. Die users may set a GND reference, via this pad, to ensure the TTL compatibility of the DIS input when using asymmetrical supplies (e.g. V+ = 10V, V- = 0V). See the “Application Information” section for details. 12 FN3955.5 June 1, 2006 HFA1145 Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) N 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES E SYMBOL -B- 1 2 3 L SEATING PLANE -A- A D h x 45° -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e α B S 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N α NOTES: MILLIMETERS 8 0° 8 8° 0° 7 8° 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. Rev. 1 6/05 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13 FN3955.5 June 1, 2006