IRF130 Data Sheet March 1999 14A, 100V, 0.160 Ohm, N-Channel Power MOSFET 1566.4 Features • 14A, 100V This N-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA17411. Ordering Information PART NUMBER File Number • rDS(ON) = 0.160Ω • Single Pulse Avalanche Energy Rated • SOA is Power Dissipation Limited • Nanosecond Switching Speeds • Linear Transfer Characteristics • High Input Impedance • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol PACKAGE BRAND D IRF130 TO-204AA IRF130 NOTE: When ordering, use the entire part number. G S Packaging JEDEC TO-204AA DRAIN (FLANGE) SOURCE (PIN 2) GATE (PIN 1) 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 IRF130 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg IRF130 100 100 14 9.9 56 ±20 79 0.53 50 -55 to 175 UNITS V V A A A V W W/oC mJ oC 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. TC = 25oC, Unless Otherwise Specified Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 10) 100 - - V Gate Threshold Voltage VGS(TH) VDS = VGS, ID = 250µA 2.0 - 4.0 V VDS = Rated BVDSS, VGS = 0V - - 25 µA VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 150oC - - 250 µA Zero Gate Voltage Drain Current IDSS On-State Drain Current (Note 2) ID(ON) Gate to Source Leakage Current IGSS Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time rDS(ON) gts td(ON) Rise Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) VDS ≥ 50V, ID = 8.3A (Figure 12) VDD = 50V, ID ≈ 14A, RG = 12Ω, RL = 3.5Ω (Figures 17, 18) MOSFET Switching Times are Essentially Independent of Operating Temperature - - A - - ±100 nA - 0.12 0.16 Ω 4.6 6.9 - S - 30 ns - 75 ns td(OFF) - - 40 ns tf - - 45 ns - 18 26 nC - 5.5 - nC - 11 - nC Gate to Source Charge Qgs Gate to Drain “Miller” Charge Qgd Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS LD Internal Source Inductance ID = 8.3A, VGS = 10V (Figures 8, 9) 14 - Qg(TOT) Internal Drain Inductance VGS = ±20V - tr Turn-Off Delay Time VDS > ID(ON) x rDS(ON)MAX, VGS = 10V LS VGS = 10V, ID = 14A, VDS = 0.8 x Rated BVDSS , Ig(REF) = 1.5mA (Figures 14, 19, 20) Gate Charge is Essentially Independent of Operating Temperature VDS = 25V, VGS = 0V, f = 1MHz (Figure 11) Measured between the Contact Screw on the Flange that is Closer to Source and Gate Pins and the Center of Die Measured from the Source Lead, 6mm (0.25in) from the Flange and the Source Bonding Pad Modified MOSFET Symbol Showing the Internal Device Inductances - 600 - pF - 300 - pF - 100 - pF - 5.0 - nH - 12.5 - nH - - 1.9 oC/W - - 30 oC/W D LD G LS S Thermal Resistance, Junction to Case RθJC Thermal Resistance, Junction to Ambient RθJA 2 Free Air Operation IRF130 Source to Drain Diode Specifications PARAMETER SYMBOL Continuous Source to Drain Current ISD Pulse Source to Drain Current (Note 3) ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode D MIN TYP MAX UNITS - - 14 A - - 56 A - - 2.5 V 55 120 250 ns 0.26 0.58 1.3 µC G S Source to Drain Diode Voltage (Note 2) VSD Reverse Recovery Time trr Reverse Recovery Charge QRR TJ = 25oC, ISD = 14A, VGS = 0V (Figure 13) TJ = 25oC, ISD = 14A, dISD/dt = 100A/µs TJ = 25oC, ISD = 5.5A, dISD/dt = 100A/µs NOTES: 2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%. 3. Repetitive rating: Pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 50V, starting TJ = 25oC, L = 380µH, RG = 25Ω, peak IAS = 14A. See Figures 15, 16. Typical Performance Curves Unless Otherwise Specified 15 ID, DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 12 9 6 3 0.2 0 0 25 50 75 100 125 150 175 0 25 50 TC , CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE 75 100 125 TC, CASE TEMPERATURE (oC) 150 175 FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 10 ZθJC, THERMAL IMPEDANCE (oC) POWER DISSIPATION MULTIPLIER 1.2 1.0 0.5 0.2 0.1 0.1 PDM 0.05 0.02 0.01 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC + TC SINGLE PULSE 10-2 10-5 10-4 0.1 10-3 10-2 t1 , RECTANGULAR PULSE DURATION (s) FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE 3 1 10 IRF130 Typical Performance Curves 25 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 102 10µs 100µs 10 1ms 10ms RATED 1 TJ = MAX TC = 25oC DC VGS = 7V 8V 10V 20 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 103 Unless Otherwise Specified (Continued) 80µs PULSE TEST 15 6V 10 5V 5 4V 0 0.1 1 102 10 0 103 10 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA 102 80µs PULSE TEST ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) VGS = 7V 15 40 50 VDS ≥ 50V 80µs PULSE TEST VGS = 8V VGS = 10V 30 FIGURE 5. OUTPUT CHARACTERISTICS 25 20 20 VDS, DRAIN TO SOURCE VOLTAGE (V) VGS = 6V 10 VGS = 5V 10 1 TJ = 175oC TJ = 25oC 5 VGS = 4V 0 0.0 1.0 2.0 3.0 4.0 VDS, DRAIN TO SOURCE VOLTAGE (V) 5.0 0.1 0 FIGURE 6. SATURATION CHARACTERISTICS 10 FIGURE 7. TRANSFER CHARACTERISTICS 1.5 3.0 ID = 14A VGS = 10V 80µs PULSE TEST NORMALIZED DRAIN TO SOURCE ON RESISTANCE DRAIN TO SOURCE ON RESISTANCE 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 1.2 0.9 VGS = 10V 0.6 VGS = 20V 0.3 0.0 0 12 24 36 ID, DRAIN CURRENT (A) 48 60 FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 4 2.4 1.8 1.2 0.6 0.0 -60 0 60 120 TJ, JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 180 IRF130 Typical Performance Curves 1500 ID = 250µA 1.15 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD 1200 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.25 Unless Otherwise Specified (Continued) 1.05 0.95 0.85 0.75 -60 0 60 120 900 600 CISS COSS 300 0 180 CRSS 1 2 TJ, JUNCTION TEMPERATURE (oC) 10 2 5 102 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 103 10 VDS 50V 80µs PULSE TEST 8 ISD, DRAIN CURRENT (A) gfs, TRANSCONDUCTANCE (S) 5 TJ = 25oC 6 TJ = 175oC 4 2 102 10 TJ = 175oC 1 TJ = 25oC 0 0 5 10 15 ID, DRAIN CURRENT (A) 20 0.1 0 25 FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT VGS, GATE TO SOURCE VOLTAGE (V) 20 ID = 14A FOR TEST CIRCUIT SEE FIGURE 18 16 0.8 1.2 1.6 0.4 VSD, SOURCE TO DRAIN VOLTAGE (V) VDS = 80V VDS = 50V VDS = 20V 12 8 4 0 0 6 12 18 24 30 Qg(TOT), TOTAL GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 5 2.0 IRF130 Test Circuits and Waveforms VDS BVDSS tP L VARY tP TO OBTAIN + RG REQUIRED PEAK IAS - VGS VDS IAS VDD VDD DUT tP 0V IAS 0 0.01Ω tAV FIGURE 16. UNCLAMPED ENERGY WAVEFORMS FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT tON tOFF td(ON) td(OFF) tf tr RL VDS 90% 90% + RG - VDD 10% 10% 0 DUT 90% VGS VGS 0 FIGURE 17. SWITCHING TIME TEST CIRCUIT 0.2µF 50% PULSE WIDTH FIGURE 18. RESISTIVE SWITCHING WAVEFORMS VDS (ISOLATED SUPPLY) CURRENT REGULATOR 12V BATTERY 50% 10% VDD Qg(TOT) SAME TYPE AS DUT 50kΩ Qgd 0.3µF VGS Qgs D VDS DUT G 0 Ig(REF) S 0 IG CURRENT SAMPLING RESISTOR VDS ID CURRENT SAMPLING RESISTOR FIGURE 19. GATE CHARGE TEST CIRCUIT 6 IG(REF) 0 FIGURE 20. GATE CHARGE WAVEFORMS IRF130 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. 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