IRF450 Data Sheet March 1999 13A, 500V, 0.400 Ohm, N-Channel Power MOSFET • 13A, 500V Formerly developmental type TA17435. Ordering Information IRF450 PACKAGE TO-204AA 1827.3 Features This N-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. PART NUMBER File Number • rDS(ON) = 0.400Ω • Single Pulse Avalanche Energy Rated • SOA is Power Dissipation Limited • Nanosecond Switching Speeds • Linear Transfer Characteristics • High Input Impedance • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol BRAND D IRF450 NOTE: When ordering, include the entire part number. G S Packaging JEDEC TO-204AA DRAIN (FLANGE) SOURCE (PIN 2) GATE (PIN 1) 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 IRF450 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg IRF450 500 500 13 8.1 52 ±20 125 1.2 860 -55 to 150 UNITS V V A A A V W W/oC mJ oC 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. TC = 25oC, Unless Otherwise Specified Electrical Specifications MIN TYP MAX UNITS Drain to Source Breakdown Voltage PARAMETER SYMBOL BVDSS VGS = 0V, ID = 250µA (Figure 10) 500 - - V Gate to Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA 2.0 - 4.0 V - - ±100 nA Gate to Source Leakage IGSS Zero Gate Voltage Drain Current IDSS On-State Drain Current (Note 2) ID(ON) Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time rDS(ON) gfs td(ON) Rise Time tr Turn-Off Delay Time td(OFF) Fall Time TEST CONDITIONS VGS = ±20V VDS = Rated BVDSS, VGS = 0V - - 25 µA VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 125oC - - 250 µA VDS > ID(ON) x rDS(ON)MAX, VGS = 10V (Figure 7) 13 - - A - 0.3 0.400 Ω VGS = 10V, ID = 7.2A (Figures 8, 9) VDS ≥ 50V, ID = 7.2A (Figure 12) VDD = 250V, ID ≈ 13A, RG = 6.2Ω, RL = 19Ω (Figures 17, 18) MOSFET SwitchingTimes are Essentially Independent of Operating Temperature tf Total Gate Charge (Gate to Source + Gate to Drain) Qg(TOT) Gate to Source Charge Qgs VGS = 10V, ID = 13A, VDS = 0.8 x Rated BVDSS , Ig(REF) = 1.5mA (Figures 14, 19, 20) Gate Charge is Essentially Independent of Operating Temperature 6.0 11 - S - 20 27 ns - 40 66 ns - 72 100 ns - 35 60 ns - 85 130 nC - 12 - nC - 42 - nC - 1800 - pF Gate to Drain “Miller” Charge Qgd Input Capacitance CISS Output Capacitance COSS - 400 - pF Reverse Transfer Capacitance CRSS - 100 - pF - 5.0 - nH - 12.5 - nH - - 0.83 oC/W - - 30 oC/W Internal Drain Inductance LD Internal Source Inductance LS VGS = 0V, VDS = 25V, f = 1.0MHz (Figure 11) Measured between the Contact Screw on the Flange that is Closer to Source and Gate Pins and the Center of Die Measured from the Source Lead, 6mm (0.25in) from the Flange to Source Bonding Pad Modified MOSFET Symbol Showing the Internal Devices Inductances D LD G LS S Thermal Resistance Junction to Case RθJC Thermal Resistance Junction to Ambient RθJA 2 Free Air Operation IRF450 Source to Drain Diode Specifications PARAMETER SYMBOL Continuous Source to Drain Current ISD Pulse Source to Drain Current (Note 3) ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode MIN TYP MAX UNITS - - 13 A - - 52 A D G S Source to Drain Diode Voltage (Note 2) VSD TJ trr TJ QRR TJ Reverse Recovery Time Reverse Recovered Charge = 25oC, ISD = 13A, VGS = 0V (Figure 13) = 25oC, ISD = 13A, dISD/dt = 100A/µs = 25oC, ISD = 13A, dISD/dt = 100A/µs - - 1.4 V 280 600 1200 ns 3.2 7.5 14 µC NOTES: 2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%. 3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 25V, starting TJ = 25oC, L = 9.2mH, RG = 25Ω, peak IAS = 13A. See Figures 14, 15. Typical Performance Curves Unless Otherwise Specified 15 ID, DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 0.2 0 12 9 6 3 0 0 50 100 150 25 50 TC , CASE TEMPERATURE (oC) 75 125 100 150 TC , CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 10 ZθJC, TRANSIENT THERMAL IMPEDANCE (oC/W) POWER DISSIPATION MULTIPLIER 1.2 1 0.5 0.1 0.001 0.2 PDM 0.1 0.05 0.02 0.01 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC + TC SINGLE PULSE 0.0001 10-5 10-4 10-2 10-3 0.1 t1, RECTANGULAR PULSE DURATION (s) FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE 3 1 10 IRF450 Typical Performance Curves Unless Otherwise Specified (Continued) 20 102 10µs 100µs 10 1ms 10ms 1 TC = 25oC TJ = MAX RATED SINGLE PULSE 0.1 1 16 VGS = 5.5V 12 8 VGS = 5.0V 4 VGS = 4.5V DC VGS = 4.0V 0 102 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 103 0 50 250 VDS ≥ 50V 5 80µs PULSE TEST VGS = 6.0V 16 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 200 102 VGS = 10V VGS = 5.5V 12 8 VGS = 5.0V 4 2 10 5 2 1 5 5 VGS = 4.0V 0 3 6 9 12 VDS , DRAIN TO SOURCE VOLTAGE (V) TJ = 25oC TJ = 150oC 2 0.1 VGS = 4.5V 15 2 10-2 0 FIGURE 6. SATURATION CHARACTERISTICS 2 4 6 8 VGS , GATE TO SOURCE VOLTAGE (V) 10 FIGURE 7. TRANSFER CHARACTERISTICS 3.0 2.0 80µs PULSE TEST NORMALIZED DRAIN TO SOURCE ON RESISTANCE DRAIN TO SOURCE ON RESISTANCE 150 FIGURE 5. OUTPUT CHARACTERISTICS 80µs PULSE TEST 0 100 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA 20 80µs PULSE TEST VGS = 6.0V OPERATION IN THIS REGION IS LIMITED BY rDS(ON) ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 103 1.6 VGS = 10V 1.2 0.8 VGS = 20V 0.4 0 0 12 24 36 ID , DRAIN CURRENT (A) 48 60 FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 4 ID = 13A VGS = 10V 2.4 1.8 1.2 0.6 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 TJ , JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE IRF450 Typical Performance Curves (Continued) 10000 ID = 250µA 1.15 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD 8000 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.25 Unless Otherwise Specified 1.05 0.95 0.85 6000 CISS 4000 COSS 2000 CRSS 0.75 -60 -40 -20 0 20 40 60 80 0 100 120 140 160 0 2 TJ , JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE ISD, SOURCE TO DRAIN CURRENT (A) TJ = 25oC 16 12 TJ = 150oC 8 4 0 0 4 102 102 VDS ≥ 50V 80µs PULSE TEST 8 12 ID , DRAIN CURRENT (A) 16 5 2 10 5 TJ = 150oC TJ = 25oC 2 1 5 2 0.1 0 20 FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT 0.5 1.0 1.5 2.0 VSD , SOURCE TO DRAIN VOLTAGE (V) FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE 20 VGS, GATE TO SOURCE VOLTAGE (V) gfs, TRANSCONDUCTANCE (S) 20 5 10 2 5 VDS , DRAIN TO SOURCE VOLTAGE (V) ID = 13A FOR TEST CIRCUIT, SEE FIGURE 18 16 VDS = 100V VDS = 250V 12 VDS = 400V 8 4 0 0 25 50 75 100 Qg(TOT) , TOTAL GATE CHARGE (nC) 125 FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 5 2.5 IRF450 Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN IAS + RG REQUIRED PEAK IAS - VGS VDS VDD VDD DUT tP 0V IAS 0 0.01Ω tAV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) td(OFF) tf tr RL VDS 90% 90% + RG - VDD 10% 10% 0 DUT 90% VGS VGS 0 FIGURE 17. SWITCHING TIME TEST CIRCUIT 0.2µF 50% PULSE WIDTH 10% FIGURE 18. RESISTIVE SWITCHING WAVEFORMS VDS (ISOLATED SUPPLY) CURRENT REGULATOR 12V BATTERY 50% VDD Qg(TOT) SAME TYPE AS DUT 50kΩ Qgd 0.3µF VGS Qgs D VDS DUT G 0 Ig(REF) S 0 IG CURRENT SAMPLING RESISTOR VDS ID CURRENT SAMPLING RESISTOR FIGURE 19. GATE CHARGE TEST CIRCUIT 6 IG(REF) 0 FIGURE 20. GATE CHARGE WAVEFORMS IRF450 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. 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