SiP4282, SiP4282A Datasheet

SiP4282, SiP4282A
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1.2 A Slew Rate Controlled Load Switch
DESCRIPTION
FEATURES
The SiP4282 series is a slew rate controlled high side
switch. The switch is of a low ON resistance P-Channel
MOSFET that supports continuous current up to 1.2 A.
• 1.8 V to 5.5 V input voltage range for SiP4282
• 1.5 V to 5.5 V input voltage range for SiP4282A
• Very low RDS(on), typically 105 mW at 5 V and
175 mW at 3 V
The SiP4282 series operates with an input voltage from
1.8 V to 5.5 V. It offers under voltage lock out that turns the
switch off when an input under voltage condition exists. The
“A” option without UVLO extends the minimum operation
voltage from 1.8 V down to 1.5 V. The SiP4282 is available
in two different versions of slew rates, 100 μs and 1 ms. The
SiP4282 series integrates load discharge circuit to ensure
the discharge of capacitive load when the switch is
disabled.
• Slew rate controlled turn-on time options:
100 μs and 1 ms
• Fast shutdown load discharge
• Low quiescent current, 4 μA for SiP4282
• Low quiescent current, 1 μA for SiP4282A
• Low shutdown current < 1 μA
• UVLO of 1.4 V for SiP4282
The SiP4282 features low input logic level to interface with
low control voltage from microprocessors. This device has a
very low operating current (typically 2.5 μA for SiP4282 and
50 pA for SiP4282A).
• PowerPAK SC-75 1.6 mm x 1.6 mm and TDFN4 1.2 mm x
1.6 mm packages
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
The SiP4282 is available in lead (Pb)-free package options
including 6 pin PPAK SC75-6, and 4 pin TDFN4 1.2 mm x
1.6 mm DFN4 packages. The operation temperature range
is specified from -40 °C to +85 °C.
APPLICATIONS
• Cellular telephones
The SiP4282 compact package options, operation voltage
range, and low operating current make it a good fit for
battery power applications.
• Digital still cameras
• Personal digital assistants (PDA)
• Hot swap supplies
• Notebook computers
• Personal communication devices
• Portable Instruments
TYPICAL APPLICATION CIRCUIT
VIN
IN
OUT
VOUT
SiP4282
C OUT
0.1 µF
C IN
1 µF
ON/OFF
ON/OFF
GND
GND
GND
Fig. 1 - SiP4282 Typical Application Circuit
S16-0792-Rev. F, 25-Apr-16
Document Number: 65740
1
For technical questions, contact: [email protected]
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ORDERING INFORMATION
TEMPERATURE RANGE
PACKAGE
SLEW RATE (TYP.)
UNDER VOLTAGE LOCKOUT
MARKING
PART NUMBER
100 μs
No
LExxx
SiP4282ADVP3-T1GE3
100 μs
Yes
LFxxx
SiP4282DVP3-T1GE3
100 μs
No
ABx
SiP4282ADNP3-T1GE4
100 μs
Yes
ACx
SiP4282DNP3-T1GE4
PPAK SC75-6
-40 °C to +85 °C
TDFN4 1.2 x 1.6
Note
• xxx = lot code
ABSOLUTE MAXIMUM RATINGS
PARAMETER
LIMIT
Supply Input Voltage (VIN)
Enable Input Voltage (VON / OFF)
-0.3 to +6
Output Voltage (VOUT)
1.4
Maximum Pulsed Current (IDM) VIN
VIN  2.5 V
3
VIN < 2.5 V
1.6
ESD Rating (HBM)
Junction Temperature (TJ)
Power Dissipation (PD) a
V
-0.3 to VIN + 0.3
Maximum Continuous Switch Current (Imax.)
Thermal Resistance (JA) a
UNIT
-0.3 to +6
A
4000
V
-40 to +125
°C
6 pin PPAK SC75 b
90
4 pin TDFN4 1.2 mm x 1.6 mm c
170
6 pin PPAK SC75 b
610
4 pin TDFN4 1.2 mm x 1.6 mm c
324
°C/W
mW
Notes
• Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
a. Device mounted with all leads and power pad soldered or welded to PC board.
b. Derate 11.1 mW/°C above TA = 70 °C.
c. Derate 5.9 mW/°C above TA = 70 °C, see PCB layout.
RECOMMENDED OPERATING RANGE
PARAMETER
LIMIT
UNIT
Input Voltage Range (VIN) for SiP4282 Version
1.8 to 5.5
V
Input Voltage Range (VIN) for SiP4282A Version
1.5 to 5.5
V
Operating Temperature Range
-40 to +85
°C
S16-0792-Rev. F, 25-Apr-16
Document Number: 65740
2
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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SPECIFICATIONS
PARAMETER
Operating Voltage c
Operating Voltage
Under Voltage Voltage
Under Voltage Lockout Hysteresis
Quiescent Current
On-Resistance
On-Resistance Temp-Coefficient
SYMBOL
VIN
VUVLO
VUVLO(hyh)
IQ
RDS(on)
MIN. a
TYP. b
MAX. a
For SiP4282xxx
1.8
-
5.5
For SiP4282Axxx
1.5
-
5.5
For SiP4282xxx, VIN falling
1
1.4
1.8
For SiP4282xxx
-
250
-
-
2.5
4
For SiP4282Axxx, On / Off = active
-
0.00005
1
VIN = 5 V, IL = 500 mA, TA = 25 °C
-
105
230
VIN = 4.2 V, IL = 500 mA, TA = 25 °C
-
110
250
VIN = 3 V, IL = 500 mA, TA = 25 °C
-
135
290
VIN = 1.8 V, IL = 500 mA, TA = 25 °C
-
230
480
For SiP4282Axxx, VIN = 1.5 V,
IL = 500 mA, TA = 25 °C
-
350
520
-
2800
-
-
-
0.3
TCRDS
On / Off Input High Voltage d
VIL
VIH
UNIT
For SiP4282xxx, On / Off = active
For SiP4282Axxx,
VIN  1.5 V to < 1.8 V
On / Off Input Low Voltage d
LIMITS
-40 °C to +85 °C
TEST CONDITIONS
UNLESS OTHERWISE SPECIFIED
VIN = 5, TA = -40 °C to +85 °C
(typical values are at TA = 25 °C)
VIN  1.8 V to < 2.7 V
-
-
0.4
VIN  2.7 V to  5.5 V
-
-
0.6
VIN  1.5 V to < 2.7 V
1.3
-
-
VIN  2.7 V to < 4.2 V
1.5
-
-
VIN  4.2 V to  5.5 V
1.8
-
-
V
mV
μA
m
ppm/°C
V
On / Off Input Leakage
ISINK
VOn / Off = 5.5 V
-
-
1
μA
Output Pull-Down Resistance
RPD
On / Off = Inactive, TA = 25 °C
-
180
250

SiP4282XXX3 AND SiP4282AXXX3 VERSIONS
Output Turn-On Delay Time
td(on)
VIN = 5 V, Rload = 10 , TA = 25 °C
-
20
40
Output Turn-On Rise Time
t(on)
VIN = 5 V, Rload = 10 , TA = 25 °C
-
140
180
Output Turn-Off Delay Time
td(off)
VIN = 5 V, Rload = 10 , TA = 25 °C
-
4
10
μs
Notes
a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
c. Part requires minimum start-up of VIN  2 V to ensure operation down to 1.8 V.
d. For VIN outside this range consult typical ON / OFF threshold curve.
S16-0792-Rev. F, 25-Apr-16
Document Number: 65740
3
For technical questions, contact: [email protected]
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PIN CONFIGURATION
IN
1
6
OUT
ON/OFF
5
OUT
4
3
IN
3
4
ON/OFF
OUT
2
GND
GND
IN
2
1
GND
Bottom View
Bottom View
Fig. 2 - PPAK SC75-6 Package
Fig. 3 - TDFN4 1.2 mm x 1.6 mm Package
PIN DESCRIPTION
PIN NUMBER
PPAK
TDFN4
1, 2
3
3
2
4
4
5, 6
1
NAME
FUNCTION
IN
GND
ON/OFF
OUT
This pin is the p-channel MOSFET source connection. Bypass to ground through a 1 μF capacitor.
Ground connection
Enable input
This pin is the p-channel MOSFET drain connection. Bypass to ground through a 0.1 μF capacitor.
TYPICAL CHARACTERISTICS (internally regulated, 25 °C, unless otherwise noted)
0.12
3.0
SiP4282A
SiP4282
2.5
IQ - Quiescent Current (μA)
IQ - Quiescent Current (nA)
0.10
0.08
0.06
0.04
0.02
2.0
1.5
1.0
0.5
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
1.0
5.5
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VIN (V)
VIN (V)
Fig. 4 - Quiescent Current vs. Input Voltage
Fig. 5 - Quiescent Current vs. Input Voltage
10
3.5
SiP4282
SiP4282A
IQ - Quiescent Current (μA)
IQ - Quiescent Current (nA)
3.0
1
0.1
VIN = 5 V
0.01
VIN = 3 V
0.001
- 40
- 20
0
20
40
VIN = 5 V
2.5
2.0
1.5
VIN = 3 V
1.0
0.5
60
80
100
0
- 40
- 20
0
20
40
60
80
100
Temperature (°C)
Temperature (°C)
Fig. 6 - Quiescent Current vs. Temperature
Fig. 7 - Quiescent Current vs. Temperature
S16-0792-Rev. F, 25-Apr-16
Document Number: 65740
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For technical questions, contact: [email protected]
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TYPICAL CHARACTERISTICS (internally regulated, 25 °C, unless otherwise noted)
350
300
VIN = 5 V
ISD(OFF) - Off Switch Current (nA)
ISD(OFF) - Off Switch Current (nA)
300
250
200
150
100
50
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
250
200
150
100
50
0
- 40
6.0
- 20
0
20
Fig. 8 - Off Switch Current vs. Input Voltage
80
100
180
ILOAD = 500 mA
500
160
RDS - On-Resistance (mΩ)
450
RDS - On-Resistance (mΩ)
60
Fig. 9 - Off Switch Current vs. Temperature
550
400
40
Temperature (°C)
VIN (V)
IL = 1.2 A
350
300
IL = 500 mA
250
200
150
140
VIN = 3 V
120
100
VIN = 5 V
80
IL = 100 mA
100
50
1.5
2.0
2.5
3.0
3.5
VIN (V)
4.0
4.5
5.0
60
- 40
5.5
- 20
40
60
80
100
Fig. 11 - RDS(on) vs. Temperature
1.6
220
210
1.4
On/Off Threshold Voltage (V)
RPD - Output Pull-Down (Ω)
20
Temperature (°C)
Fig. 10 - RDS(on) vs. Input Voltage
200
190
180
170
1.2
VIH
1.0
VIL
0.8
0.6
160
150
- 40
0
- 20
0
20
40
60
80
100
Temperature (°C)
Fig. 12 - Output Pull-Down Resistance vs. Temperature
S16-0792-Rev. F, 25-Apr-16
0.4
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VIN (V)
Fig. 13 - ON / OFF Threshold vs. Input Voltage
Document Number: 65740
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TYPICAL WAVEFORMS
SiP4282xxx3 and SiP4282Axxx3 Switching
(VIN = 3 V)
SiP4282xxx3 and SiP4282Axxx3 Switching
(VIN = 5 V)
SiP4282xxx3 and SiP4282Axxx3 Turn-Off
(VIN = 3 V)
SiP4282xxx3 and SiP4282Axxx3 Turn-Off
(VIN = 5 V)
S16-0792-Rev. F, 25-Apr-16
Document Number: 65740
6
For technical questions, contact: [email protected]
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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BLOCK DIAGRAM
OUT
IN
Under
Voltage
Lockout
SiP4282xxx3
only
Turn-On
Slew Rate
Control
Level
Shift
ON/OFF
GND
Fig. 14 - SiP4282 Functional Block Diagram
PCB LAYOUT
Fig. 15 - TDFN4 1.2 mm x 1.6 mm PCB Layout
S16-0792-Rev. F, 25-Apr-16
Document Number: 65740
7
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DETAILED DESCRIPTION
The SiP4282 is a P-Channel MOSFET power switches
designed for high-side slew rate controlled load-switching
applications. Once turned on, the slew-rate control circuitry
is activated and current is ramped in a linear fashion until it
reaches the level required for the output load condition. This
is accomplished by first elevating the gate voltage of the
MOSFET up to its threshold voltage and then by linearly
increasing the gate voltage until the MOSFET becomes fully
enhanced. At this point, the gate voltage is then quickly
increased to the full input voltage to reduce RDS(on) of the
MOSFET switch and minimize any associated power losses.
Thermal Considerations
All versions features a shutdown output discharge circuit
which is activated at shutdown (when the part is disabled
through the On / Off pin) and discharges the output pin
through a small internal resistor hence, turning off the load.
For SiP4282-3, in instances where the input voltage falls
below 1.4 V (typically) the under voltage lock-out circuitry
protects the MOSFET switch from entering the saturation
region or operation by shutting down the chip.
The maximum power dissipation in any application is
dependent on the maximum junction temperature,
TJ (max.) = 125 °C, the junction-to-ambient thermal
resistance for the SC-75 PPAK package, J-A = 90 °C/W,
and the ambient temperature, TA, which may be
formulaically expressed as:
APPLICATION INFORMATION
Input Capacitor
While a bypass capacitor on the input is not required, a 1 μF
or larger capacitor for CIN is recommended in almost all
applications. The bypass capacitor should be placed as
physically close as possible to the SiP4282 to be effective in
minimizing transients on the input. Ceramic capacitors are
recommended over tantalum because of their ability to
withstand input current surges from low impedance sources
such as batteries in portable devices.
Output Capacitor
A 0.1 μF capacitor or larger across VOUT and GND is
recommended to insure proper slew operation. COUT may
be increased without limit to accommodate any load
transient condition with only minimal affect on the SiP4282
turn on slew rate time. There are no ESR or capacitor type
requirement.
Enable
The On / Off pin is compatible with both TTL and CMOS
logic voltage levels.
Protection Against Reverse Voltage Condition
The P-channel MOSFET pass transistor has an intrinsic
diode that is reversed biased when the input voltage is
greater than the output voltage. Should VOUT exceed VIN,
this intrinsic diode will become forward biased and allow
excessive current to flow into the IC thru the VOUT pin and
potentially damage the IC device. Therefore extreme care
should be taken to prevent VOUT from exceeding VIN.
The SiP4282 is designed to maintain a constant output load
current. Due to physical limitations of the layout and
assembly of the device the maximum switch current is
1.2 A, as stated in the Absolute Maximum Ratings table.
However, another limiting characteristic for the safe
operating load current is the thermal power dissipation of
the package. To obtain the highest power dissipation (and a
thermal resistance of 90 °C/W) the power pad of the device
should be connected to a heat sink on the printed circuit
board.
125 - T A
T J (max.) - T A
P (max.) = ------------------------------------- = ---------------------- J-A
90
It then follows that, assuming an ambient temperature of
70 °C, the maximum power dissipation will be limited to
about 610 mW.
So long as the load current is below the 1.2 A limit, the
maximum continuous switch current becomes a function
two things: the package power dissipation and the RDS(on) at
the ambient temperature.
As an example let us calculate the worst case maximum
load current at TA = 70 °C. The worst case RDS(on) at 25 °C
occurs at an input voltage of 1.8 V and is equal to 480 m.
The RDS(on) at 70 °C can be extrapolated from this data using
the following formula
RDS(on) (at 70 °C) = RDS(on) (at 25 °C) x (1 + TC x T)
Where TC is 3300 ppm/°C. Continuing with the calculation
we have
RDS(on) (at 70 °C) = 480 m x (1 + 0.0033 x (70 °C - 25 °C)) =
551 m
The maximum current limit is then determined by
P (max.)
I LOAD (max.)  ----------------------R DS(ON)
which in case is 1.05 A. Under the stated input voltage
condition, if the 1.05 A current limit is exceeded the internal
die temperature will rise and eventually, possibly damage
the device.
In conditions where VOUT exceeds VIN a Schottky diode in
parallel with the internal intrinsic diode is recommended to
protect the SiP4282.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?65740.
S16-0792-Rev. F, 25-Apr-16
Document Number: 65740
8
For technical questions, contact: [email protected]
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Package Information
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TDFN4 1.2 x 1.6 Case Outline
D
D2
4
b
3
Pin #1 ID
(Optional)
4
K
E
E2
3
1
2
e
Index Area
(D/2 x E/2)
Bottom View
A
A1
Top View
A3
1
L
2
Side View
DIM.
MILLIMETERS
INCHES
MIN.
NOM.
MAX.
MIN.
NOM.
MAX.
A
0.45
0.55
0.60
0.017
0.022
0.024
A1
0.00
-
0.05
0.00
-
A3
0.15 REF. or 0.127 REF.
(1)
0.006 or 0.005
0.002
(1)
b
0.20
0.25
0.30
0.008
0.010
0.012
D
1.15
1.20
1.25
0.045
0.047
0.049
D2
0.81
0.86
0.91
0.032
0.034
0.036
e
0.50 BSC
0.020
E
1.55
1.60
1.65
0.061
0.063
0.065
E2
0.45
0.50
0.55
0.018
0.020
0.022
K
L
0.25 typ.
0.25
0.30
0.010 typ.
0.35
0.010
0.012
0.014
ECN: T16-0143-Rev. C, 18-Apr-16
DWG: 5995
Note
(1) The dimension depends on the leadframe that assembly house used.
Revision: 18-Apr-16
Document Number: 65734
1
For technical questions, contact: [email protected]
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PAD Pattern
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR TDFN4 1.2 x 1.6
0.86
0.50
3
1
2
2.0
0.55
0.20
0.50
0.20
4
0.55
0.30
Recommended Minimum Pads
Dimensions in mm
Document Number: 66558
Revision: 05-Mar-10
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Revision: 02-Oct-12
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Document Number: 91000