SIP32472DN-T1-GE3

SiP32472
www.vishay.com
Vishay Siliconix
46 m, Slew Rate Controlled Load Switch
in uDFN4 1.1 mm x 1.1 mm
DESCRIPTION
FEATURES
The SiP32472 is a slew rate controlled integrated high side
load switch that operates in the input voltage range from
1.2 V to 5.5 V.
• Low input voltage, 1.2 V to 5.5 V
• Low Ron, 46 m/typ. at 5 V
• Slew rate control
This design features slew rate control, reverse blocking,
output discharge, and control logic pull down. The device is
logic high enabled.
• Low logic control
• Reverse current blocking when disabled
Available
• Integrated output discharge switch
The SiP32472 is available in uDFN4 1.1 mm x 1.1 mm
package.
• Integrated pull down resistor at “EN”
• uDFN4 1.1 mm x 1.1 mm package
• Material categorization: For definitions of compliance
please see www.vishay.com/doc?99912
APPLICATIONS
• Smart phones
• GPS and portable media players
• Tablet computer
• Medical and healthcare equipment
• Industrial and instrument
• Game console
DEVICE OPTIONS
PART NUMBER
SiP32472DN-T1-GE3
Ron
(m)
ton
(μs)
td(off)
REVERSE
BLOCKING
RDISCHARGE
ENLOGIC
EN/PULL
DOWN
RESISTOR
()
46
200
2
Y
Y
High enable
2M
TYPICAL APPLICATION CIRCUIT
VIN
IN
OUT
VOUT
SiP32472
CIN
COUT
EN
EN
GND
GND
GND
Fig. 1 - Typical Application Circuit
S13-1349-Rev. B, 03-Jun-13
Document Number: 62512
1
For technical questions, contact: [email protected]
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SiP32472
www.vishay.com
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
PARAMETER
CONDITIONS
LIMIT
Reference to GND
- 0.3 to 6.5
Output Voltage VOUT
Reference to GND
- 0.3 to 6.5
Output Voltage VOUT
Pulse at 1 ms reference to GND (1)
- 1.6
Reference to GND
- 0.3 to 6.5
Supply Input Voltage VIN
Enable Input Voltage EN
Maximum Continuous Switch Current
UNIT
V
1.2
Maximum Pulse Switch Current
Pulse at 1 ms, 10 % duty cycle
A
2
ESD Rating (HBM)
4000
V
Thermal Resistance
280
°C/W
TEMPERATURE
Operating Temperature
- 40 to 85
Operating Junction Temperature
125
Storage Temperature
°C
- 65 to 150
Note
(1) Negative current injection up to 300 mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE
ELECTRICAL PARAMETER
Input Voltage (VIN)
MINIMUM
TYPICAL
MAXIMUM
UNIT
1.2
-
5.5
V
SPECIFICATIONS
PARAMETER
SYMBOL
TEST CONDITION UNLESS SPECIFIED
VIN = 1.2 V to 5.5 V, TA = - 40 °C to 85 °C
(Typical values are at 25 °C)
LIMITS
UNIT
MIN.
TYP.
MAX.
7
POWER SUPPLY
Quiescent Current
IQ
VIN = 3.3 V, IOUT = 0 mA
-
4.5
Shutdown Current
ISD
OUT = GND
-
0.01
2
Off Switch Current
IDS(off)
EN = GND, OUT = GND
-
0.01
2
Out = 5 V, IN = 1.2 V, EN = 0 V, (Measured at IN pin)
-
0.01
1
Out = 5 V, IN = 0 V, EN = 0 V, (Measured at IN pin)
-
0.01
1
Reverse Blocking Current
I(in)RB
μA
SWITCH RESISTANCE
On Resistance
RDS(on)
Discharge Switch On
Resistance
RPD
EN Pin Pull Down Resistor
REN
On Resistance Temperature
Coefficient
IOUT = 500 mA, VIN = 1.2 V, TA = 25 °C
-
86
130
IOUT = 500 mA, VIN = 1.5 V, TA = 25 °C
-
72
100
IOUT = 500 mA, VIN = 1.8 V, TA = 25 °C
-
62
90
IOUT = 500 mA, VIN = 3 V, TA = 25 °C
-
48
60
IOUT = 500 mA, VIN = 5 V, TA = 25 °C
-
46
60
When VIN = 3 V at 25 °C
-
80
-
When VIN = 1.8 V at 25 °C
-
< 200
-
EN = 1.2 V
1
2.6
5
-
2800
TCRDS
m

M
ppm/°C
ON/OFF LOGIC
EN Input Low Voltage
VIL
VIN = 1.5 V
0.4
-
-
EN Input High Voltage
VIH
VIN = 5.5 V
-
-
1
S13-1349-Rev. B, 03-Jun-13
V
Document Number: 62512
2
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiP32472
www.vishay.com
Vishay Siliconix
SPECIFICATIONS
PARAMETER
TEST CONDITION UNLESS SPECIFIED
VIN = 1.2 V to 5.5 V, TA = - 40 °C to 85 °C
(Typical values are at 25 °C)
SYMBOL
LIMITS
UNIT
MIN.
TYP.
MAX.
SWITCHING SPEED
Switch Turn-ON Delay Time
ton_DLY
RLOAD = 500  , CL = 0.1 μF
VIN = 5 V
-
130
-
Switch Turn-ON Rise Time
tr
RLOAD = 500  , CL = 0.1 μF
VIN = 5 V
-
170
-
toff
RLOAD = 500 , CL = 0.1 μF,
(50 % VIN to 90 % VOUT)
-
2
-
Switch Turn-OFF Delay Time
μs
PIN CONFIGURATION
Bottom View
IN
2
3
OUT
EN
1
4
GND
Pin 1 Indicator
Fig. 2 - uDFN 1.1 mm x 1.1 mm Package
PIN DESCRIPTION (uDFN PACKAGE)
PIN#
NAME
FUNCTION
1
EN
Switch on/off control. A pull down resistor is integrated
2
IN
Switch input
3
OUT
Switch output
4
GND
Ground connection
DEVICE MARKING
Row 1
C+W
: W = week code
Row 2
Dot
: Dot is Pin 1 locator
SiP32472 = C
TRUTH TABLE
EN
S13-1349-Rev. B, 03-Jun-13
SWITCH
1
ON
0
OFF
Document Number: 62512
3
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SiP32472
www.vishay.com
Vishay Siliconix
BLOCK DIAGRAM
Reverse
Blocking
IN
OUT
Control
Logic
EN
Charge
Pump
Turn On
Slew Rate
Control
GND
Fig. 3 - Functional Block Diagram
7
7
6
6
IQ - Quiescent Current (μA)
IQ - Quiescent Current (μA)
TYPICAL CHARACTERISTICS (internally regulated, 25 °C, unless otherwise noted)
5
4
3
2
VIN = 5.5 V
VIN = 5.0 V
5
VIN = 3.3 V
4
VIN = 2.5 V
3
2
VIN = 1.2 V
1
1
0
0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
- 40
5.5
0
20
40
60
80
Temperature (°C)
Fig. 4 - Quiescent Current vs. Input Voltage
Fig. 6 - Quiescent Current vs. Temperature
250
100
10 000
1000
200
IIQ(OFF) - Off Supply Current (nA)
IQ(OFF) - Off Supply Current (nA)
- 20
VIN (V)
150
100
50
0
VIN = 5.5 V
100
VIN = 5.0 V
10
VIN = 3.3 V
1
0.1
VIN = 2.5 V
0.01
VIN = 1.2 V
0.001
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
- 40
- 20
0
20
40
60
80
VIN (V)
Temperature (°C)
Fig. 5 - Off Supply Current vs. Input Voltage
Fig. 7 - Off Supply Current vs. Temperature
S13-1349-Rev. B, 03-Jun-13
100
Document Number: 62512
4
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SiP32472
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Vishay Siliconix
TYPICAL CHARACTERISTICS (internally regulated, 25 °C, unless otherwise noted)
10 000
250
IDS(off) - Off Switch Current (nA)
IDS(off) - Off Switch Current (nA)
1000
200
150
100
50
VIN = 5.5 V
100
VIN = 5.0 V
10
VIN = 3.3 V
1
VIN = 2.5 V
0.1
0.01
VIN = 1.2 V
0.001
0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
- 40
5.5
20
40
60
80
100
Temperature (°C)
Fig. 8 - Off Switch Current vs. Input Voltage
Fig. 11 - Off Switch Current vs. Temperature
58
170
IO = 0.2 A
VIN = 3.3 V
56
160
54
RDS - On-Resistance (mΩ)
150
RDS - On-Resistance (mΩ)
0
VIN (V)
180
140
IO = 1.0 A
130
120
110
IO = 0.2 A
100
IO = 0.5 A
90
80
IO = 1.5 A
70
52
50
48
46
44
42
60
50
- 20
40
IO = 0.1 A
38
40
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
- 40
5.5
- 20
0
20
40
60
80
100
Temperature (°C)
VIN (V)
Fig. 12 - RDS(on) vs. Temperature
Fig. 9 - RDS(on) vs. Input Voltage
0
0
- 50
VIN = 1.2 V
-200
- 100
VIN = 1.2 V
-400
IIN - Input Current (nA)
IIN - Input Current (nA)
- 150
- 200
- 250
VIN = 0 V
- 300
- 350
- 400
- 450
- 500
VIN = 0 V
-600
-800
-1000
-1200
VOUT = 5 V
-1400
- 550
-1600
- 600
-1800
- 650
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VOUT (V)
Fig. 10 - Reverse Blocking Current vs. Output Voltage
S13-1349-Rev. B, 03-Jun-13
- 40
- 20
0
20
40
60
80
100
Temperature (°C)
Fig. 13 - Reverse Blocking Current vs. Temperature
Document Number: 62512
5
For technical questions, contact: [email protected]
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SiP32472
www.vishay.com
Vishay Siliconix
TYPICAL CHARACTERISTICS (internally regulated, 25 °C, unless otherwise noted)
85
180
VIN = 5 V
CL = 0.1 μF
R L = 500 Ω
160
RPD - Output Pulldown Resistance (Ω)
td(on) - Turn-On Delay Time (μs)
170
150
140
130
120
110
100
- 40
- 20
0
20
40
60
80
80
VIN = 3.3 V
IOUT = 5 mA
75
70
65
60
55
100
- 40
- 20
Temperature (°C)
20
40
60
80
100
Temperature (°C)
Fig. 17 - Output Pulldown Resistance vs. Temperature
Fig. 14 - Turn-On Delay Time vs. Temperature
5.00
0.9
VIN = 5 V
CL = 0.1 μF
RL = 500 Ω
0.85
td(off) - Turn-Off Delay Time (μs)
0.8
EN Threshold Voltage (V)
0
VIH
0.75
VIL
0.7
0.65
0.6
0.55
0.5
4.00
3.00
2.00
1.00
0.45
0.4
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VIN (V)
0.00
- 40
- 20
0
20
40
60
80
100
Temperature (°C)
Fig. 15 - EN Threshold Voltage vs. Input Voltage
Fig. 18 - Turn-Off Delay Time vs. Temperature
220
VIN = 5 V
CL = 0.1 μF
RL = 500 Ω
210
tr - Rise Time (μs)
200
190
180
170
160
150
140
- 40
- 20
0
20
40
60
80
100
Temperature (°C)
Fig. 16 - Rise Time vs. Temperature
S13-1349-Rev. B, 03-Jun-13
Document Number: 62512
6
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiP32472
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TYPICAL WAVEFORMS
VEN (2V/div)
VEN (500mV/div)
VOUT (500mV/div)
VOUT (2V/div)
IOUT (10mA/div)
IOUT (20mA/div)
VIN = 1.2V
RL = 500Ω
CL = 0.1μF
Time (100μs/div)
Fig. 19 - Turn-On Time
VIN = 5.0V
RL = 500Ω
CL = 0.1μF
Time (100μs/div)
Fig. 22 - Turn-On Time
VEN (500mV/div)
VEN (2V/div)
VOUT (500mV/div)
VOUT (2V/div)
IOUT (10mA/div)
VIN = 1.8V
RL = 500Ω
CL = 0.1μF
Time (100μs/div)
Fig. 20 - Turn-On Time
IOUT (20mA/div)
Time (100μs/div)
VIN = 5.5V
RL = 500Ω
CL = 0.1μF
Fig. 23 - Turn-On Time
VEN (2V/div)
VOUT (2V/div)
IOUT (20mA/div)
Time (100μs/div)
VIN = 3.3V
RL = 500Ω
CL = 0.1μF
Fig. 21 - Turn-On Time
S13-1349-Rev. B, 03-Jun-13
Document Number: 62512
7
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiP32472
www.vishay.com
Vishay Siliconix
TYPICAL WAVEFORMS
VEN (500mV/div)
VEN (2V/div)
VOUT (500mV/div)
VOUT (2V/div)
IOUT (10mA/div)
VIN = 1.2V
RL = 500Ω
CL = 0.1μF
Time (100μs/div)
IOUT (20mA/div)
VIN = 5.0V
RL = 500Ω
CL = 0.1μF
Time (20μs/div)
Fig. 24 - Turn-Off Time
Fig. 27 - Turn-Off Time
VEN (500mV/div)
VEN (2V/div)
VOUT (500mV/div)
VOUT (2V/div)
IOUT (10mA/div)
VIN = 1.8V
RL = 500Ω
CL = 0.1μF
Time (20μs/div)
Fig. 25 - Turn-Off Time
IOUT (20mA/div)
Time (20μs/div)
VIN = 5.5V
RL = 500Ω
CL = 0.1μF
Fig. 28 - Turn-Off Time
VEN (2V/div)
VOUT (2V/div)
IOUT (20mA/div)
Time (20μs/div)
VIN = 3.3V
RL = 500Ω
CL = 0.1μF
Fig. 26 - Turn-Off Time
S13-1349-Rev. B, 03-Jun-13
Document Number: 62512
8
For technical questions, contact: [email protected]
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SiP32472
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Vishay Siliconix
DETAILED DESCRIPTION
SiP32472 has a P-channel power MOSFET designed as a
high side load switch. It incorporates a negative charge
pump at the gate to keep the gate to source voltage high
when turned on therefore keep the on resistance low at
lower input voltage range. SiP32472 is designed with slow
slew rate to minimize the inrush current during turn on. This
device has a reverse blocking circuit to prevent the current
from going back to the input in case the output voltage is
higher than the input voltage. The SiP32472 has an output
pulldown resistor to discharge the output capacitance when
the device is off.
APPLICATION INFORMATION
Input Capacitor
While a bypass capacitor on the input is not required, a
4.7 μF or larger capacitor for CIN is recommended in almost
all applications. The bypass capacitor should be placed as
physically close as possible to the input pin to be effective
in minimizing transients on the input. Ceramic capacitors are
recommended over tantalum because of their ability to
withstand input current surges from low impedance sources
such as batteries in portable devices.
Output Capacitor
A 0.1 μF capacitor across VOUT and GND is recommended
to insure proper slew operation. There is inrush current
through the output MOSFET and the magnitude of the
inrush current depends on the output capacitor, the bigger
the COUT the higher the inrush current. There are no ESR or
capacitor type requirement.
Enable
The EN pin is compatible with CMOS logic voltage levels. It
requires at least 0.4 V or below to fully shut down the device
and 1 V or above to fully turn on the device. There is a
2.8 M resistor connected between EN pin and GND pin.
P (max.)
=
T J (max.) - T A
θJ- A
=
125 - TA
280
It then follows that, assuming an ambient temperature of
70 °C, the maximum power dissipation will be limited to
about 196 mW.
So long as the load current is below the 1.2 A limit, the
maximum continuous switch current becomes a function
two things: the package power dissipation and the RDS(ON)
at the ambient temperature.
As an example let us calculate the worst case maximum
load current at TA = 70 °C. The worst case RDS(ON) at 25 °C
is 65 m at VIN = 1.5 V. The RDS(ON) at 70 °C can be
extrapolated from this data using the following formula:
RDS(ON) (at 70 °C) = RDS(ON) (at 25 °C) x (1 + TC x T)
Where TC is 2820 ppm/°C. Continuing with the calculation
we have
RDS(ON) (at 70 °C) = 65 m x (1 + 0.00282 x (70 °C - 25 °C))
= 73.2 m
The maximum current limit is then determined by
P (max.)
I LOAD (max.) <
R DS(ON )
which in this case is 1.6 A. Under the stated input voltage
condition, if the 1.6 A current limit is exceeded the internal
die temperature will rise and eventually, possibly damage
the device.
To avoid possible permanent damage to the device and
keep a reasonable design margin, it is recommended to
operate the device maximum up to 1.2 A only as listed in the
Absolute Maximum Ratings table.
Protection Against Reverse Voltage Condition
This device contains a reverse blocking circuit to keep the
output current from flowing back to the input in case the
output voltage is higher than the input voltage.
Thermal Considerations
This device is designed to maintain a constant output load
current. Due to physical limitations of the layout and
assembly of the device the maximum switch current is 1.2 A
as stated in the Absolute Maximum Ratings table. However,
another limiting characteristic for the safe operating load
current is the thermal power dissipation of the package. To
obtain the highest power dissipation (and a thermal
resistance of 280 °C/W) the device should be connected to
a heat sink on the printed circuit board.
The maximum power dissipation in any application
is dependant on the maximum junction temperature,
TJ(max.) = 125 °C, the junction-to-ambient thermal
resistance, J-A = 280 °C/W, and the ambient temperature,
TA, which may be formulaically expressed as:
S13-1349-Rev. B, 03-Jun-13
Document Number: 62512
9
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
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SiP32472
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Vishay Siliconix
PACKAGE OUTLINE
uDFN4L - 1.1 mm x 1.1 mm Case Outline
(4)
(5)
(5)
MILLIMETERS (1)
INCHES
DIMENSION
MIN.
NOM.
MAX.
MIN.
NOM.
MAX.
A
0.50
0.55
0.60
0.020
0.022
0.024
A1
0
-
0.05
0
-
0.002
0.30
0.007
A3
b
0.15 REF
0.18
0.25
0.006 REF
0.010
D
1.10 BSC
0.043 BSC
e
0.65 BSC
0.026 BSC
E
1.10 BSC
L
0.30

0°
0.012
0.043 BSC
0.40
0.50
0.012
-
12°
0°
0.016
0.020
-
12°
N (3)
4
4
Ne (3)
2
2
Notes
(1) Use millimeters as the primary measurement.
(2) Dimensioning and tolerances conform to ASME Y14.5M. - 1994.
(3) N is the number of terminals. Ne is the number of terminals in E site.
(4) Dimensions b applies to plated terminal and is measured between 0.15 mm and 0.30 mm from terminal tip.
(5) The pin 1 identifier must be existed on the top surface of the package by using identification mark or other feature of package body.
(6) Package warpage max. 0.05 mm.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?62512
S13-1349-Rev. B, 03-Jun-13
Document Number: 62512
10
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
uDFN4L - 1.1 mm x 1.1 mm Case Outline
D
A
NxL
B
Nxb
2
3
2
3
1
4
(4)
b
e
1
4
(5)
PIN 1 dot area
Top view
Bottom view
C
A
Seating plane
(5)
PIN 1 identifier
A1
A3
Side view
MILLIMETERS (1)
INCHES
DIMENSION
MIN.
NOM.
MAX.
MIN.
NOM.
MAX.
A
0.50
0.55
0.60
0.020
0.022
0.024
A1
0
-
0.05
0
-
0.002
0.30
0.007
A3
b
0.15 REF
0.18
0.25
0.006 REF
0.010
D
1.10 BSC
0.043 BSC
e
0.65 BSC
0.026 BSC
E
1.10 BSC
L
0.30

0°
0.012
0.043 BSC
0.40
0.50
0.012
-
12°
0°
0.016
0.020
-
12°
N (3)
4
4
Ne (3)
2
2
Notes
(1) Use millimeters as the primary measurement.
(2) Dimensioning and tolerances conform to ASME Y14.5M. - 1994.
(3) N is the number of terminals. Ne is the number of terminals in E site.
(4) Dimensions b applies to plated terminal and is measured between 0.15 mm and 0.30 mm from terminal tip.
(5) The pin 1 identifier must be existed on the top surface of the package by using identification mark or other feature of package body.
(6) Package warpage max. 0.05 mm.
ECN: S13-1370-Rev. A, 24-Jun-13
DWG: 6015
Revision: 24-Jun-13
Document Number: 65634
1
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
PAD Pattern
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR TDFN4 1.2 x 1.6
0.86
0.50
3
1
2
2.0
0.55
0.20
0.50
0.20
4
0.55
0.30
Recommended Minimum Pads
Dimensions in mm
Document Number: 66558
Revision: 05-Mar-10
www.vishay.com
1
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Vishay
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Material Category Policy
Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
(EEE) - recast, unless otherwise specified as non-compliant.
Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.
Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free
requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
conform to JEDEC JS709A standards.
Revision: 02-Oct-12
1
Document Number: 91000