T NT DU C PRO LACEME r at E T ente O LE R EP OBS ENDED upport C om/tsc lS MM sil.c ECO Technica ww.inter Data Sheet November 1994, Rev A NO R t o u r w IL or ac S t n R o E c 8-INT 1-88 EL4390 ® Triple 80MHz Video Amplifier with DC Restore The EL4390 is three wideband current-mode feedback amplifiers optimized for video performance, each with a DC restore amplifier. The DC restore function is activated by a common TTL/CMOS compatible control signal while each channel has a separate restore reference. Each amplifier can drive a load of 150Ω at video signal levels. The EL4390 operates on supplies as low as ±4V up to ±15V. Being a current-mode feedback design, the bandwidth stays relatively constant at approximately 80MHz over the ±1 to ±10 gain range. The EL4390 has been optimized for use with 1300Ω feedback resistors. Pinout FN7164 Features • 80MHz -3dB bandwidth for gains of 1 to 10 • 800V/µs slew rate • 15MHz bandwidth flat to 0.1dB • Excellent differential gain and phase • TTL/CMOS compatible DC restore function • Available in 16-pin PDIP, 16-pin SOL Applications • RGB drivers requiring DC restoration • RGB multiplexers requiring DC restoration • RGB building blocks • Video gain blocks requiring DC restoration • Sync and color burst processing Ordering Information EL4390 (16-PIN PDIP, SO) TOP VIEW 1 PART NUMBER TEMP. RANGE PACKAGE PKG. NO. EL4390CN -40°C to +85°C 16-Pin PDIP MDP0031 EL4390CM -40°C to +85°C 16-Pin SOL MDP0027 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners. EL4390 Absolute Maximum Ratings (TA = 25°C) Supply Voltage between VS+ and GND. . . . . . . . . . . . . . . . . +12.6V Input Voltage (IN+, IN-, ENABLE, CLAMP) . . . GND -0.3V, VS +0.3V VS Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . ±18V or 36V VIN Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±15V or VS ∆VIN Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .±6V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Open-Loop DC Electrical Specifications PARAMETER DESCRIPTION Supplies at ±15V, Load = 1kΩ TEMP MIN TYP MAX UNITS AMPLIFIER SECTION (NOT RESTORED) VOS Input Offset Voltage +25°C 2 15 mV IB+ IIN+ Input Bias Current +25°C 0.2 5 µA IB- IIN- Input Bias Current +25°C 10 65 µA ROL Transimpedance (Note 1) +25°C RIN- IN- Resistance +25°C CMRR Common-Mode Rejection Ratio (Note 2) +25°C PSRR Power Supply Rejection Ratio (Note 3) VO 100 220 kΩ 50 Ω 50 56 dB +25°C 50 70 dB Output Voltage Swing; RL = 1kΩ +25°C ±12 ±13 V ISC Short-Circuit Current +25°C 45 70 100 mA ISY Supply Current (Quiescent) +25°C 10 20 32 mA RESTORING SECTION VOS, COMP Composite Input Offset Voltage (Note 4) +25°C 8 35 mV IB+, R Restore IN+ Input Bias Current +25°C 0.2 5 µA IOUT Restoring Current Available +25°C 2 4 mA PSRR Power Supply Rejection Ratio (Note 3) +25°C 50 70 dB GOUT Conductance +25°C 8 mA/V ISY, RES Supply Current, Restoring +25°C VIL, RES RES Logic Low Threshold +25°C VIH, RES RES Logic High Threshold +25°C IIL, RES RES Input Current, Logic Low +25°C 2 10 µA IIH, RES RES Input Current, Logic High +25°C 0.5 3 µA NOTES: 1. For current feedback amplifiers, AVOL = ROL/RIN2. VCM = ±10V for VS = ±15V. 3. VOS is measured at VS = ±4.5V and VS = ±16V, both supplies are changed simultaneously. 4. Measured from VCL to amplifier output, while restoring. 2 10 1.4 23 37 mA 1.0 1.4 V 1.8 V EL4390 Closed-Loop AC Electrical Specifications PARAMETER Supplies at ±15V, Load = 150Ω and 15pF, TA = 25°C (Note 1) DESCRIPTION MIN TYP MAX UNITS AMPLIFIER SECTION SR Slew Rate (Note 1) 800 V/µs SR Slew Rate w/ ±5V Supplies (Note 2) 550 V/µs BW Bandwidth, -3dB, AV = 1 ±5V Supplies, -3dB 95 72 MHz MHz BW Bandwidth, -0.1dB ±5V Supplies, -0.1dB 20 14 MHz MHz dG Differential Gain at 3.58MHz at ±5V Supplies (Note 3) 0.02 0.02 % % dθ Differential Phase at 3.58MHz at ±5V Supplies (Note 3) 0.03 0.06 (°) (°) RESTORING SECTION TRE Time to Enable Restore 35 ns TRD Time to Disable Restore 35 ns NOTES: 1. Test fixture was designed to minimize capacitance at the IN- input. A “good” fixture should have less than 2pF of stray capacitance to ground at this very sensitive pin. See application notes for further details. 2. SR is measured at 20% to 80% of 4Vpk-pk square wave, with AV = 5, RF = 820Ω, RG = 200Ω. 3. DC offset from -0.714V to +0.714V, AC amplitude is 286mVP-P, equivalent to 40 ire. TABLE 1. CHARGE STORAGE CAPACITOR VALUE VS. DROOP AND CHARGING RATES CAP VALUE (NF) DROOP IN 60µS (MV) CHARGE IN 2µS (MV) CHARGE IN 4µS (MV) 10 30 400 800 22 13.6 182 364 47 6.4 85 170 100 3.0 40 80 220 1.36 18 36 These numbers represent the worst case bias current, and the worst case charging current. Note that to get the full (2mA+) charging current, the clamp input must have >250mV of error voltage. Note that the magnitude of the bias current will decrease as temperature increases. The basic droop formula is: V (droop) = IB+ × (Line time - Charge time) / capacitor value and the basic charging formula is: V (charge) = IOUT × Charge time / capacitor value Where IOUT is: IOUT = (Clamp voltage - IN+ voltage) / 120 3 EL4390 Typical Performance Curves Gain Flatness for Various RF VS = ±15V, AV = 0dB Gain Flatness for Various RF and RG Values VS = ±5V, AV = 6dB Gain Flatness VS = ±15V, AV = 14dB, RF/RG as Shown 4 Gain Flatness for Various RF VS = ±5V, AV = 0dB Gain Flatness for Various RF and RG Values VS = ±15V, AV = 6dB Phase Shift for AV = 2, RF = RG = 1300Ω Phase Shift for AV = 2, RF = RG = 1000Ω at VS = ±5V and VS = ±15V Gain Flatness VS = ±5V, AV = 14dB, RF/RG as Shown Phase Shift for AV = 5dB, RF = 820Ω, RG = 200Ω, VS = ±5V EL4390 Typical Performance Curves Gain Flatness VS = ±5V, AV = 20dB, RF/RG as Shown Differential Phase at VS = ±15V Frequency Response for Various CLOAD, VS = ±15V, RF = RG = 1300Ω 5 (Continued) Gain Flatness VS = ±5V, AV = 26dB, RF = 680Ω, RG = 36Ω Differential Gain at VS = ±15V Differential Gain at VS = ±5V Differential Phase at VS = ±5V Frequency Response for Various CLOAD, VS = ±5V, RF = RG = 1300Ω Crosstalk, Channel R and B to Channel G, VS = ±5V, RF = 1300Ω EL4390 Typical Performance Curves (Continued) Crosstalk, Channel R and G to Channel B, VS = ±5V, RF = 1300Ω IN+ Input Impedance during HOLD, VS = ±5V Phase Shift at IN+ Pin during Restore, RS = 75Ω and 150Ω, VS = ±5V IOUT Restoring vs Clamp, Voltage at VS = ±5V Output during DC-Restoration, Showing DC Droop RF = RG = 1300Ω, VS = ±5V 6 Output during DC-Restoration, RF = RG = 1300Ω, VS = ±5V IN+ Input Impedance during SAMPLE, VS = ±5V Pulse Response with AV = 2, RF = RG = 1300Ω at VS = ±5V Pulse Response with AV = 5, RF = 820Ω and RG = 200Ω at VS = ±15V EL4390 Typical Performance Curves (Continued) Maximum Power Dissipation vs Ambient Temperature— 16-Pin PDIP Maximum Power Dissipation vs Ambient Temperature— 16-Pin PDIP Simplified Schematic of One Channel of EL4390 Applications Information Circuit Operation Each channel of the EL4390 contains a current feedback amplifier and a TTL/CMOS compatible clamp circuit. The current that the clamp can source or sink into the noninverting input is approximately: I = (VCLAMP - VIN+) / 120 So, when the non-inverting input is at the same voltage as the clamp reference, no current will flow, and hence no charge is added to the capacitor. When there is a difference in voltage, current will flow, in an attempt to cancel the error AT THE NON-INVERTING input. The amplifier’s offset voltage and (IB- × RF) DC errors are not cancelled with this 7 loop. It is purely a method of adding a controlled DC offset to the signal. As well as the offset voltage error, which goes up with gain, and the IB- × RF error which drops with gain, there is also the IB+ error term. Since the amplifier is capacitively coupled, this small current is slowly integrated and shows up as a very slow ramp voltage. Table below shows the output EL4390 voltage drift in 60µS for various values of coupling capacitor, all assuming the very worst IB+ current. TABLE 2. CHARGE STORAGE CAPACITOR VALUE VS. DROOP AND CHARGING RATES CAP VALUE (NF) DROOP IN 60µS (MV) CHARGE IN 2µS (MV) CHARGE IN 4µS (MV) 10 30 400 800 22 13.6 182 364 47 6.4 85 170 100 3.0 40 80 220 1.36 18 36 In normal circuit operation, the picture content will also cause a slow change in voltage across the capacitor, so at every back porch time period, these error terms can be corrected. When a signal source is being switched, e.g., from two different surveillance cameras, it is recommended to synchronize the switching with the vertical blanking period, and to drive the HOLD pin (pin 6) low, during these lines. This will ensure that the system has been completely restored, regardless of the average intensity of the two pictures. Application Hints Figures 1 & 2 shows a three channel DC-restoring system, suitable for R-G-B or Y-U-V component video, or three synchronous composite signals. Figure 1 shows the amplifiers configured for non-inverting gain, and Figure 2 shows the amplifiers configured for inverting gains. Note that since the DC-restoring function is accomplished by clamping the amplifier’s non-inverting input, during the back porch period, any signal on the noninverting input will be distorted. For this reason, it is recommended to use the inverting configuration for composite video, since this avoids the color burst being altered during the clamp time period. Since all three amplifiers are monolithic, they run at the same temperature, and will have very similar input bias currents. This can be used to advantage, in situations where the droop voltage needs to be compensated, since a single trim circuit can be used for all three channels. A 560kΩ or similar value resistor helps to isolate each signal. See Figure 2. The advantage of compensating for the droop voltage, is that a smaller capacitor can be used, which allows a larger level restoration within one line. See Table 1 for values of capacitor and charge/droop rates. 8 EL4390 FIGURE 1. 9 EL4390 FIGURE 2. 10 EL4390 FIGURE 3. In Figure 3, one of the three channels is used, together with a low-offset op-amp, to automatically trim the bias current of the other two channels. The two remaining channels are shown in the non-inverting configuration, but could equally well be set to provide inverting gains. Two DC-restored channels are typically needed in fader applications. See the EL4094 and EL4095 for suitable, monolithic video faders. Layout and Dissipation Considerations As with all high frequency circuits, the supplies should be bypassed with a 0.1µF ceramic capacitor very close to the supply pins, and a 4.7µF tantalum capacitor fairly close, to handle the high current surges. While a ground plane is recommended, the amplifier will work well with a “star” grounding scheme. The pin 3 ground is only used for the 11 internal bias generator and the reference for the TTL compatible “HOLD” input. As with all current feedback capacitors, all stray capacitance to the inverting inputs should be kept as low as possible, to avoid unwanted peaking at the output. This is especially true if the value of RF has already been reduced to raise the bandwidth of the part, while tolerating some peaking. In this situation, additional capacitance on the inverting input can lead to an unstable amplifier. Since there are three amplifiers all in one package, and each amplifier can sink or source typically more than 70mA, some care is needed to avoid excessive die temperatures. Sustained, DC currents, of over 30mA, are not recommended, due to the limited current handling capability of the metal traces inside the IC. Also, the short circuit EL4390 protection can be tripped with currents as low as 45mA, which is seen as excessive distortion in the output waveform. As a quick rule of thumb, both the SOL and DIP 16 pin packages can dissipate about 1.4 watts at 25°C, and with ±15V supplies and a worst case quiescent current of 32mA, yields 0.96 watts, before any load is driven. Dissipation of the EL4390 can be reduced by lowering the supply voltage. Although some performance is degraded at lower supplies, as seen in the characteristic curves, it is often found to be a useful compromise. The bandwidth can be recovered, by reducing the value of RF, and RG as appropriate. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12