Single, Dual, and Quad Micropower, Low Drift, RRIO Operational Amplifiers ISL28130, ISL28230, ISL28430 Features The ISL28130, ISL28230 and ISL28430 are single, dual and quad micropower, low offset drift operational amplifiers that are optimized for single and dual supply operation from 1.65V to 5.5V and ±0.825V to ±2.75V. Their low supply current of 20µA and rail-to-rail input range enable the ISL28130, ISL28230, ISL28430 to be an excellent general purpose op amp for a range of applications. The ISL28130, ISL28230 and ISL28430 are ideal for handheld devices that operate off 2 AA or single Li-ion batteries. • Low Input Offset Voltage . . . . . . . . . . . . . . . . . . . . . 40µV, Max. The ISL28130 is available in industry standard pinouts for 5 Ld SOT-23, 5 Ld SC70 and 8 Ld SOIC packages. The ISL28230 is available in industry standard pinouts for 8 Ld MSOP, 8Ld SOIC and 8 Ld DFN packages. The ISL28430 is available in 14 Ld TSSOP and 14 Ld SOIC packages. All devices operate over the temperature range of -40°C to +125°C. • Rail-to-Rail Inputs and Output • Low Offset Drift . . . . . . . . . . . . . . . . . . . . . . . . 150nV/°C, Max • Input Bias Current . . . . . . . . . . . . . . . . . . . . . . . . 250 pA, Max. • Quiescent Current (Per Amplifier) . . . . . . . . . . . . . .20µA, Typ. • Single Supply Range . . . . . . . . . . . . . . . . . . . +1.65V to +5.5V • Dual Supply Range. . . . . . . . . . . . . . . . . . . ±0.825V to ±2.75V • Low Noise (0.01Hz to 10Hz) . . . . . . . . . . . . . . . . . 1.1µVP-P, Typ. Applications • Bi-Directional Current Sense • Temperature Measurement • Medical Equipment • Electronic Weigh Scales • Precision/Strain Gauge Sensor • Precision Regulation • Low Ohmic Current Sense • High Gain Analog Front Ends 400 VREF 499k 4.99k + V+ 0.1 - VSENSE OUT V499k 4.99k GND I-SENSE- INPUT BIAS CURRENT (pA) V+ +1.65V TO +5.5V I-SENSE+ 300 200 VS = ±2.5V 100 0 -100 -50 BI-DIRECTIONAL CURRENT SENSE AMPLIFIER FIGURE 1. TYPICAL APPLICATION DIAGRAM December 16, 2010 FN7623.1 1 VS = ±0.825V -25 0 25 50 75 TEMPERATURE (°C) 100 125 FIGURE 2. IB vs TEMPERATURE CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2010. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL28130, ISL28230, ISL28430 Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING TEMP RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # ISL28130CHZ-T7 BDPA (Note 4) 0 to +70 5 Ld SOT-23 P5.064A ISL28130CHZ-T7A BDPA (Note 4) 0 to +70 5 Ld SOT-23 P5.064A Coming Soon ISL28130FHZ TBD -40 to +125 5 Ld SOT-23 P5.064A ISL28130CEZ-T7 BLA (Note 4) 0 to +70 5 Ld SC70 P5.049 ISL28130CEZ-T7A BLA (Note 4) 0 to +70 5 Ld SC70 P5.049 Coming Soon ISL28130FEZ TBD -40 to +125 5 Ld SC70 P5.049 Coming Soon ISL28130CBZ 28130 CBZ 0 to +70 8 Ld SOIC M8.15E Coming Soon ISL28130FBZ TBD -40 to +125 8 Ld SOIC M8.15E ISL28230CUZ 8230Z 0 to +70 8 Ld MSOP M8.118A Coming Soon ISL28230FUZ TBD -40 to +125 8 Ld MSOP M8.118A ISL28230CBZ 28230 CBZ 0 to +70 8 Ld SOIC M8.15E Coming Soon ISL28230FBZ TBD -40 to +125 8 Ld SOIC M8.15E ISL28230CRZ 230Z 0 to +70 8 Ld 3x3mm DFN L8.3x3J Coming Soon ISL28230FRZ TBD -40 to +125 8 Ld 3x3mm DFN L8.3x3J ISL28430CBZ 28430 CBZ 0 to +70 14 Ld SOIC MDP0027 Coming Soon ISL28430FBZ TBD -40 to +125 14 Ld SOIC MDP0027 ISL28430CVZ 28430 CVZ 0 to +70 14 Ld TSSOP MDP0044 Coming Soon ISL28430FVZ TBD -40 to +125 14 Ld TSSOP MDP0044 NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28130, ISL28230, ISL28430. For more information on MSL please see techbrief TB363. 4. The part marking is located on the bottom of the part. 2 FN7623.1 December 16, 2010 ISL28130, ISL28230, ISL28430 Pin Configurations ISL28130 (8 LD SOIC) TOP VIEW ISL28130 (5 LD SOT-23) TOP VIEW OUT 1 5 + - IN+ 3 4 NC 1 8 NC IN- 2 7 V+ - + V- 2 V+ IN+ 3 IN- 6 OUT V- 4 ISL28230 (8 LD MSOP, SOIC) TOP VIEW ISL28130 (5 LD SC70) TOP VIEW IN+ 1 5 V+ OUT_A 1 + - V- 2 IN- 3 5 NC IN-_A 2 4 8 V+ IN+_A 3 OUT 7 OUT_B - + + - V- 4 6 IN-_B 5 IN+_B ISL28430 (14 LD TSSOP, SOIC) TOP VIEW ISL28230 (8 LD DFN) TOP VIEW OUT_A 1 OUT_A 1 8 V+ IN-_A 2 IN-_A 2 7 OUT_B IN+_A 3 IN+_A 3 6 IN-_B V- 4 5 IN+_B 14 OUT_D - + + - 12 IN+_D V+ 4 11 V- IN+_B 5 10 IN+_C + - OUT_B 7 - + IN-_B 6 13 IN-_D 9 IN-_C 8 OUT_C Pin Descriptions ISL28130 (5 Ld SOT23) ISL28130 (8 Ld SOIC) ISL28130 (5 LD SC70) PIN NAME 3 3 1 IN+ FUNCTION EQUIVALENT CIRCUIT Non-inverting input V+ - IN- + IN+ VCircuit 1 2 4 2 V- Negative supply 4 2 3 IN- Inverting input 3 (See “Circuit 1”) FN7623.1 December 16, 2010 ISL28130, ISL28230, ISL28430 Pin Descriptions (Continued) ISL28130 (5 Ld SOT23) ISL28130 (8 Ld SOIC) ISL28130 (5 LD SC70) PIN NAME 1 6 4 OUT FUNCTION EQUIVALENT CIRCUIT Output V+ OUT VCircuit 2 5 7 5 1, 5, 8 V+ Positive supply NC Not Connected – This pin is not electrically connected internally. Pin Descriptions ISL28230 (8 Ld MSOP, SOIC, ISL28430 DFN) (14 Ld TSSOP, SOIC) PIN NAME FUNCTION Non-inverting input 3 3 IN+_A 5 5 IN+_B - 10 IN+_C - 12 EQUIVALENT CIRCUIT V+ - IN- + IN+_D IN+ VCircuit 1 4 11 V- Negative supply 2 2 IN-_A Inverting input 6 6 IN-_B - 9 IN-_C - 13 IN-_D 1 1 OUT_A 7 7 OUT_B - 8 OUT_C - 14 OUT_D (See Circuit 1) Output V+ OUT VCircuit 2 8 4 V+ Positive supply PD - Paddle Thermal Pad. Connect to most negative supply. DFN packages only. 4 FN7623.1 December 16, 2010 ISL28130, ISL28230, ISL28430 Absolute Maximum Ratings Thermal Information Max Supply Voltage V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.5V Max Voltage VIN to GND . . . . . . . . . . . . . . . . . . . . (V- - 0.3V) to (V+ + 0.3V)V Max Input Differential Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V Max Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Max Voltage VOUT to GND (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±3.0V ESD Tolerance (ISL28130) Human Body Model (Tested at JESD22-A114F) . . . . . . . . . . . . . . . 3000V Machine Model (Tested at JESD22-A115B) . . . . . . . . . . . . . . . . . . . 200V Charged Device Model (Tested at JESD22-C110D) . . . . . . . . . . . . 1500V ESD Tolerance (ISL28230, ISL28430) Human Body Model (Tested at JESD22-A114F) . . . . . . . . . . . . . . . 4000V Machine Model (Tested at JESD22-A115B) . . . . . . . . . . . . . . . . . . . 400V Charged Device Model (Tested at JESD22-C110D) . . . . . . . . . . . . 2000V Latch-Up Passed Per JESD78B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 5 Ld SOT-23 (Notes 5, 7) . . . . . . . . . . . . . . . . . 225 110 5 Ld SC70 (Notes 5, 7). . . . . . . . . . . . . . . . . . . 206 146 8 Ld SOIC (ISL28130) (Notes 5, 7) . . . . . . . . . 135 95 8 Ld MSOP (Notes 5, 7) . . . . . . . . . . . . . . . . . . 180 65 8 Ld SOIC (ISL28230) (Notes 5, 7) . . . . . . . . . 125 90 8 Ld DFN (Notes 6, 8). . . . . . . . . . . . . . . . . . . . 53 12 14 Ld TSSOP (Notes 5, 7) . . . . . . . . . . . . . . . . 110 40 14 Ld SOIC (Notes 5, 7) . . . . . . . . . . . . . . . . . . 75 47 Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range: Full Grade Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C Commercial Grade Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 6. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 7. For θJC, the “case temp” location is taken at the package top center. 8. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications V+ = 5V, V- = 0V, VCM = 2.5V, TA = +25°C, RL = 10kΩ, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. MIN PARAMETER DESCRIPTION CONDITIONS (Note 9) TYP MAX (Note 9) UNIT -40 ±5 40 µV -46.8 - 46.8 µV -150 20 150 nV/°C DC SPECIFICATIONS VOS Input Offset Voltage Vs = 1.65V to 5.5V TCVOS Input Offset Voltage Temperature Coefficient IOS Input Offset Current - -60 - pA TCIOS Input Offset Current Temperature Coefficient - 0.11 - pA/°C IB Input Bias Current -250 - 250 pA -700 - 700 pA Guaranteed by CMRR -0.1 - 5.1 V VCM = -0.1V to 5.1V 110 125 - dB 105 - - dB 105 138 - dB 105 - - dB Common Mode Input Voltage Range CMRR PSRR Common Mode Rejection Ratio Power Supply Rejection Ratio T = 0°C to +70°C Vs = 2.0V to 5.5V VOH Output Voltage Swing, High 4.950 4.981 - V VOL Output Voltage Swing, Low - 18 50 mV AOL Open Loop Gain RL = 1MΩ - 150 - dB V+ Supply Voltage Guaranteed by VOS 1.65 - 5.5 V 5 FN7623.1 December 16, 2010 ISL28130, ISL28230, ISL28430 Electrical Specifications V+ = 5V, V- = 0V, VCM = 2.5V, TA = +25°C, RL = 10kΩ, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) MIN PARAMETER IS DESCRIPTION Supply Current, Per Amplifier CONDITIONS RL = OPEN (Note 9) TYP MAX (Note 9) UNIT - 20 25 µA - - 35 µA ISC+ Output Source Short Circuit Current RL = Short V- - 15 - mA ISC- Output Sink Short Circuit Current RL = Short V+ - -15 - mA GBWP Gain Bandwidth Product AV = 100, RF = 100kΩ, RG = 1kΩ, RL = 10kΩ to VCM - 400 - kHz eN VP-P Peak-to-Peak Input Noise Voltage f = 0.01Hz to 10Hz - 1.1 - µVP-P eN Input Noise Voltage Density f = 1kHz - 65 - nV/√(Hz) iN Input Noise Current Density f = 1kHz - 72 - fA/√(Hz) f = 10Hz - 80 - fA/√(Hz) f = 1MHz - 1.6 - pF - 1.12 - pF - 0.2 - V/µs - 0.1 - V/µs - 1.1 - µs - 1.1 - µs AC SPECIFICATIONS Cin Differential Input Capacitance Common Mode Input Capacitance TRANSIENT RESPONSE SR Positive Slew Rate VOUT = 1V to 4V, RL = 10kΩ Negative Slew Rate tr, tf, Small Signal Rise Time, tr 10% to 90% Fall Time, tf 10% to 90% tr, tf Large Signal Rise Time, tr 10% to 90% Fall Time, tf 10% to 90% AV = +1, VOUT = 0.1VP-P, RF = 0Ω, RL = 10kΩ, CL = 1.2pF AV = +1, VOUT = 2VP-P, RF = 0Ω, RL = 10kΩ, CL = 1.2pF - 20 - µs - 30 - µs ts Settling Time to 0.1%, 2VP-P Step AV = +1, RF = 0Ω, RL = 10kΩ, CL - 35 - µs trecover Output Overload Recovery Time, Recovery to 90% of Output Saturation AV = +2, RF = 10kΩ, RL = Open, CL = 3.7pF - 10.5 - µs = 1.2pF NOTE: 9. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 6 FN7623.1 December 16, 2010 ISL28130, ISL28230, ISL28430 Typical Performance Curves n V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, T = +25°C, unless otherwise specified. 400 INPUT BIAS CURRENT (pA) INPUT BIAS CURRENT (pA) 400 300 200 VS = ±2.5V 100 VS = ±0.825V 0 -100 -50 -25 0 25 50 75 100 300 200 VS = ±2.5V VS = ±0.825V 100 0 -100 -50 125 -25 0 TEMPERATURE (°C) 75 100 125 40 PER AMPLIFIER SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) 40 30 25 20 15 10 -50 -25 0 25 50 75 100 35 PER AMPLIFIER 30 25 20 15 10 -50 125 -25 0 TEMPERATURE (°C) 20 19 18 VIN = 0V RL = OPEN 16 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) FIGURE 7. SUPPLY CURRENT vs SUPPLY VOLTAGE 7 50 75 100 125 FIGURE 6. SUPPLY CURRENT vs TEMPERATURE, Vs = ±2.5V OPEN LOOP GAIN (dB)/PHASE (°) 21 17 25 TEMPERATURE (°C) FIGURE 5. SUPPLY CURRENT vs TEMPERATURE, Vs = ±0.825V SUPPLY CURRENT (µA) 50 FIGURE 4. IB- vs TEMPERATURE FIGURE 3. IB+ vs TEMPERATURE 35 25 TEMPERATURE (°C) 6.0 200 150 PHASE 100 50 GAIN 0 -50 RL = 10M CL = 100pF SIMULATION -100 0.1m 1m 10m 100m 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 8. FREQUENCY RESPONSE vs OPEN LOOP GAIN, RL = 10MΩ FN7623.1 December 16, 2010 ISL28130, ISL28230, ISL28430 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, T = +25°C, unless otherwise specified. (Continued) 1 1 RL = 100k -1 RL = 1k -2 -3 RL = 10k -4 RL = 49.9k RL = OPEN -5 VS = ±0.8V CL = 3.7pF AV = +1 VOUT = 10mVP-P -6 -7 -8 -9 100 1k NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 0 -2 -4 -7 1M -9 100 10M Rf = Rg = 1k 7 GAIN (dB) NORMALIZED GAIN (dB) 8 6 Rf = Rg = 10k 5 4 Rf = Rg = 100k VS = ±2.5V RL = 100k CL = 3.7pF AV = +2 VOUT = 10mVP-P 1M 10M VOUT = 500mV -4 -5 VOUT = 250mV -6 -7 VOUT = 100mV VOUT = 10mV 1M 10M 0 NORMALIZED GAIN (dB) GAIN (dB) 10k 100k FREQUENCY (Hz) FIGURE 12. GAIN vs FREQUENCY vs VOUT Rg = 100, Rf = 100k Rg = 1k, Rf = 100k AV = 100 V+ = 5V CL = 3.7pF RL = 100k VOUT = 10mVP-P 30 AV = 10 Rg = 10k, Rf = 100k 10 0 1k VS = ±2.5V RL = OPEN CL = 3.7pF AV = 1 1 AV = 1000 50 20 10M -3 -9 100 70 40 1M VOUT = 1V -2 -8 10k 100k FREQUENCY (Hz) 10k 100k FREQUENCY (Hz) -1 FIGURE 11. GAIN vs FREQUENCY vs FEEDBACK RESISTOR VALUES Rf/Rg 60 1k FIGURE 10. GAIN vs FREQUENCY vs RL, VS = ±2.5V 0 1k VS = ±2.5V CL = 3.7pF AV = +1 VOUT = 10mVP-P -6 1 0 100 RL = 49.9k -8 10k 100k FREQUENCY (Hz) RL = OPEN -5 9 1 RL = 10k -3 10 2 RL = 1k -1 FIGURE 9. GAIN vs FREQUENCY vs RL, VS = ±0.8V 3 RL = 100k 0 AV = 1 -10 10 1k 10k 100k FREQUENCY (Hz) 1M 10M FIGURE 13. FREQUENCY RESPONSE vs CLOSED LOOP GAIN 8 VS = ±0.7V -2 VS = ±0.8V -3 -4 VS= ±1.5V -5 -6 -7 -8 Rg = OPEN, Rf = 0 100 -1 VS = ±2.75V RL = 100k CL = 3.7pF AV = +1 VOUT = 10mVP-P -9 100 1k 10k 100k FREQUENCY (Hz) 1M 10M FIGURE 14. GAIN vs FREQUENCY vs SUPPLY VOLTAGE FN7623.1 December 16, 2010 ISL28130, ISL28230, ISL28430 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, T = +25°C, unless otherwise specified. (Continued) 5.0 CL = 824pF 6 4.5 CL = 474pF 4 4.0 CL = 224pF 2 3.5 SIGNAL (V) NORMALIZED GAIN (dB) 8 0 -2 CL = 104pF -4 CL = 51pF VS = ±2.5V -6 R = 100k L -8 AV = +1 VOUT = 10mVP-P -10 100 1k 2.5 2.0 RL = 100k CL = 3.7pF AV = 1 VOUT = 4VP-P 1.5 1.0 CL = 3.7pF 10k 3.0 0.5 100k 1M 0 10M 0 50 100 150 200 250 TIME (µs) FREQUENCY (Hz) FIGURE 15. GAIN vs FREQUENCY vs CL 0.12 0.10 0.8 0.6 SIGNAL (V) SIGNAL (V) 400 0.14 1.0 RL = 100k CL = 3.7pF AV = 1 VOUT = 1VP-P 0.4 0.08 RL = 100k CL = 3.7pF AV = 1 VOUT = 100mVP-P 0.06 0.04 0.2 0.02 0 10 20 30 40 50 60 TIME (µs) 70 80 90 0 0 100 4.995 40 VS = 5V RL = 10kΩ 35 VOL (mV) 5.000 4.990 4.985 4.980 4.975 -50 5 10 15 20 25 TIME (µs) 30 35 40 FIGURE 18. SMALL SIGNAL STEP RESPONSE (100mV) FIGURE 17. LARGE SIGNAL STEP RESPONSE (1V) VOH (V) 350 FIGURE 16. LARGE SIGNAL STEP RESPONSE (4V) 1.2 0 300 VS = 5V RL = 10kΩ 30 25 20 -25 0 25 50 75 TEMPERATURE (°C) FIGURE 19. VOH vs TEMPERATURE 9 100 125 15 -50 -25 0 25 50 75 100 125 TEMPERATURE (°C) FIGURE 20. VOL vs TEMPERATURE FN7623.1 December 16, 2010 ISL28130, ISL28230, ISL28430 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, T = +25°C, unless otherwise specified. (Continued) -20 -20 Vs = ±0.8V RL = OPEN CL = 3.7pF AV = 1 VOUT = 1VP-P -60 Vs = ±2.5V RL = OPEN CL = 3.7pF AV = 1 VOUT = 1VP-P -40 CROSSTALK (dB) CROSSTALK (dB) -40 -80 -100 -120 -60 -80 -100 -120 -140 1k 10k 100k FREQUENCY (Hz) FIGURE 21. CROSSTALK vs FREQUENCY, V S = ±0.8V 10 1M -140 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 22. CROSSTALK vs FREQUENCY, VS = ±2.5V FN7623.1 December 16, 2010 ISL28130, ISL28230, ISL28430 Applications Information Layout Guidelines for High Impedance Inputs Functional Description To achieve the maximum performance of the high input impedance and low offset voltage of the ISL28130, ISL28230 and ISL28430 amplifiers, care should be taken in the circuit board layout. The PC board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. Surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. The ISL28130, ISL28230 and ISL28430 are low offset low drift operational amplifiers with a very high open loop gain (150dB) and rail-to-rail input/output. The ISL28130, ISL28230 and ISL28430 operate on a single supply range of 1.65V to 5.5V or dual supply range of ±0.825V to ±2.75V while consuming only 20µA of supply current per channel. The ISL28130, ISL28230 and ISL28430 has a 400kHz gain-bandwidth. The high open loop gain, low offset voltage, high bandwidth and low 1/f noise make the ISL28130, ISL28230 and ISL28430 ideal for precision applications. Rail-to-rail Input and Output (RRIO) The RRIO CMOS amplifier uses parallel input PMOS and NMOS that enable the inputs to swing 100mV beyond either supply rail. The inverting and non-inverting inputs do not have back-to-back input clamp diodes and are capable of maintaining high input impedance at high differential input voltages. This is effective in eliminating output distortion caused by high slew-rate input signals. The output stage uses common source connected PMOS and NMOS devices to achieve rail-to-rail output drive capability with 15mA current limit and the capability to swing to within 50mV of either rail while driving a 10kΩ load. IN+ and IN- Protection High Gain, Precision DC-Coupled Amplifier The circuit in Figure 24 implements a single-stage DC-coupled amplifier with an input DC sensitivity of under 100nV that is only possible using a low VOS amplifier with high open loop gain. High gain DC amplifiers operating from low voltage supplies are not practical using typical low offset precision op amps. For example, a typical precision amplifier in a gain of 10kV/V with a ±100µV VOS and offset drift 0.5µV/°C of a low offset op amp would produce a DC error of >1V with an additional 5mV/°C of temperature dependent error making it difficult to resolve DC input voltage changes in the mV range. The ±40µV max VOS and 150nV/°C of temperature drift of the ISL28130, ISL28230, ISL28430 produces a temperature stable maximum DC output error of only ±400mV with a maximum output temperature drift of 1.5mV/°C. The additional benefit of a very low 1/f noise corner frequency and some feedback filtering enables DC voltages and voltage fluctuations well below 10µV to be easily detected with a simple single stage amplifier. All input terminals have internal ESD protection diodes to both positive and negative supply rails, limiting the input voltage to within one diode beyond the supply rails. For applications where either input is expected to exceed the rails by 0.5V, an external series resistor must be used to ensure the input currents never exceed 20mA (see Figure 23). CF 0.018µF 1MΩ, +2.5V VIN VIN RIN VOUT RL + 100Ω 1MΩ VOUT RL + 100Ω -2.5V ACL = 10kV/V FIGURE 23. INPUT CURRENT LIMITING 11 FIGURE 24. HIGH GAIN, PRECISION DC-COUPLED AMPLIFIER FN7623.1 December 16, 2010 ISL28130, ISL28230, ISL28430 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION 12/7/10 FN7623.1 CHANGE Corrected Thermals for DFN package in “Tja from 125 to 53, “Tjc from 90 to 12” 12/3/10 Removed Part Markings from Full temp grade parts and changed to TBD until availability is validated. 12/2/10 --Updated copyright to legal's suggested verbiage on page 1. -Updated front page text to add DFN packaging and extended temp range -40°C to +125°C -Removed previous Ib vs Temp plot and added new -40°C to +125°C Ib vs Temp plot on front page. -Updated ordering information table by adding a full temp range option to all parts and temp range column. Also added in DFN part to ordering table. All full temp parts are stamped Coming Soon. Parts ISL28130CHZ-T7, ISL28130CHZ-T7A and ISL28130CEZ-T7, ISL28130CEZ-T7A shown they are Tape and reel only parts. -Added in DFN package to Pin Configurations table. -Added in -40°C to +125°C temp range under Operating Conditions page 5. -Added the testing standards performance information to the ESD ratings in Abs Max Table -Added new Input Bias Current Ib spec of 700pA MIN/MAX in Electrical Spec table for -40°C to +125°C temp range -Revised Note 9 for Electrical Spec table as: "Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design." -Updated all curves in the datasheet with 0°C to +70°C temp range to -40°C to +125°C temp range. -Added DFN package L8.3x3J outline drawing to the end of datasheet. 10/19/10 On page 6 changed “Supply Current, Per Amplifier” from a typical of 18µA to 20µA to comply with front page. 8/17/10 FN7623.0 Initial Release Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL28130, ISL28230 , ISL28430. To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. 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For information regarding Intersil Corporation and its products, see www.intersil.com 12 FN7623.1 December 16, 2010 ISL28130, ISL28230, ISL28430 Small Outline Transistor Plastic Packages (SC70-5) P5.049 D 5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE VIEW C e1 INCHES 5 4 E CL 1 2 CL 3 e E1 b CL 0.20 (0.008) M C C CL A A2 SEATING PLANE A1 -C- SYMBOL MIN MAX MIN MAX NOTES A 0.031 0.043 0.80 1.10 - A1 0.000 0.004 0.00 0.10 - A2 0.031 0.039 0.80 1.00 - b 0.006 0.012 0.15 0.30 b1 0.006 0.010 0.15 0.25 c 0.003 0.009 0.08 0.22 6 c1 0.003 0.009 0.08 0.20 6 D 0.073 0.085 1.85 2.15 3 E 0.071 0.094 1.80 2.40 - E1 0.045 0.053 1.15 1.35 3 e e1 L 0.10 (0.004) C WITH PLATING b1 0.0256 Ref 0.0512 Ref 0.010 c1 0.018 - 1.30 Ref 0.26 - 0.46 0.017 Ref. 0.420 Ref. L2 0.006 BSC 0.15 BSC 0o N c 0.65 Ref L1 α b MILLIMETERS 8o 0o 5 4 - 8o - 5 5 R 0.004 - 0.10 - R1 0.004 0.010 0.15 0.25 Rev. 3 7/07 NOTES: BASE METAL 1. Dimensioning and tolerances per ASME Y14.5M-1994. 2. Package conforms to EIAJ SC70 and JEDEC MO-203AA. 4X θ1 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. R1 4. Footlength L measured at reference to gauge plane. 5. “N” is the number of terminal positions. R GAUGE PLANE SEATING PLANE L C L1 α L2 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only. 4X θ1 VIEW C 0.4mm 0.75mm 2.1mm 0.65mm TYPICAL RECOMMENDED LAND PATTERN 13 FN7623.1 December 16, 2010 ISL28130, ISL28230, ISL28430 Package Outline Drawing P5.064A 5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE Rev 0, 2/10 1.90 0-3° D A 0.08-0.20 5 4 PIN 1 INDEX AREA 2.80 3 1.60 3 0.15 C D 2x 2 5 (0.60) 0.20 C 2x 0.95 SEE DETAIL X B 0.40 ±0.05 3 END VIEW 0.20 M C A-B D TOP VIEW 10° TYP (2 PLCS) 2.90 5 H 0.15 C A-B 2x 1.45 MAX C 1.14 ±0.15 0.10 C SIDE VIEW SEATING PLANE (0.25) GAUGE PLANE 0.45±0.1 0.05-0.15 4 DETAIL "X" (0.60) (1.20) NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 3. Dimension is exclusive of mold flash, protrusions or gate burrs. (2.40) 4. Foot length is measured at reference to guage plane. 5. This dimension is measured at Datum “H”. 6. Package conforms to JEDEC MO-178AA. (0.95) (1.90) TYPICAL RECOMMENDED LAND PATTERN 14 FN7623.1 December 16, 2010 ISL28130, ISL28230, ISL28430 Package Outline Drawing M8.118A 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP) Rev 0, 9/09 A 3.0±0.1 8 0.25 CAB 3.0±0.1 4.9±0.15 DETAIL "X" 1.10 Max PIN# 1 ID B SIDE VIEW 2 1 0.18 ± 0.05 2 0.65 BSC TOP VIEW 0.95 BSC 0.86±0.09 GAUGE PLANE H C 0.25 SEATING PLANE 0.33 +0.07/ -0.08 0.08 C A B 0.10 ± 0.05 3°±3° 0.10 C 0.55 ± 0.15 DETAIL "X" SIDE VIEW 1 5.80 NOTES: 4.40 3.00 1. Dimensions are in millimeters. 2. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSE Y14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. 4. Plastic interlead protrusions of 0.25mm max per side are not included. 5. Dimensions “D” and “E1” are measured at Datum Plane “H”. 6. This replaces existing drawing # MDP0043 MSOP 8L. 0.65 0.40 1.40 TYPICAL RECOMMENDED LAND PATTERN 15 FN7623.1 December 16, 2010 ISL28130, ISL28230, ISL28430 Thin Shrink Small Outline Package Family (TSSOP) 0.25 M C A B D MDP0044 A THIN SHRINK SMALL OUTLINE PACKAGE FAMILY (N/2)+1 N MILLIMETERS SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE PIN #1 I.D. E E1 0.20 C B A 1 (N/2) B 2X N/2 LEAD TIPS TOP VIEW 0.05 e C SEATING PLANE 0.10 M C A B b 0.10 C N LEADS H A 1.20 1.20 1.20 1.20 1.20 Max A1 0.10 0.10 0.10 0.10 0.10 ±0.05 A2 0.90 0.90 0.90 0.90 0.90 ±0.05 b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 D 5.00 5.00 6.50 7.80 9.70 ±0.10 E 6.40 6.40 6.40 6.40 6.40 Basic E1 4.40 4.40 4.40 4.40 4.40 ±0.10 e 0.65 0.65 0.65 0.65 0.65 Basic L 0.60 0.60 0.60 0.60 0.60 ±0.15 L1 1.00 1.00 1.00 1.00 1.00 Reference Rev. F 2/07 NOTES: 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. SIDE VIEW 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. SEE DETAIL “X” 3. Dimensions “D” and “E1” are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. c END VIEW L1 A A2 GAUGE PLANE 0.25 L A1 0° - 8° DETAIL X 16 FN7623.1 December 16, 2010 ISL28130, ISL28230, ISL28430 Small Outline Package Family (SO) A D h X 45° (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL “X” 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4° ±4° DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL SO-14 SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference - N SO-8 SO16 (0.150”) 8 14 16 Rev. M 2/07 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 17 FN7623.1 December 16, 2010 ISL28130, ISL28230, ISL28430 Package Outline Drawing M8.15E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09 4 4.90 ± 0.10 A DETAIL "A" 0.22 ± 0.03 B 6.0 ± 0.20 3.90 ± 0.10 4 PIN NO.1 ID MARK 5 (0.35) x 45° 4° ± 4° 0.43 ± 0.076 1.27 0.25 M C A B SIDE VIEW “B” TOP VIEW 1.75 MAX 1.45 ± 0.1 0.25 GAUGE PLANE C SEATING PLANE 0.10 C 0.175 ± 0.075 SIDE VIEW “A 0.63 ±0.23 DETAIL "A" (0.60) (1.27) NOTES: (1.50) (5.40) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. The pin #1 identifier may be either a mold or mark feature. 6. Reference to JEDEC MS-012. TYPICAL RECOMMENDED LAND PATTERN 18 FN7623.1 December 16, 2010 ISL28130, ISL28230, ISL28430 Package Outline Drawing L8.3x3J 8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 0 9/09 2X 1.950 3.00 B 0.15 8 5 3.00 (4X) 6X 0.65 A 1.64 +0.10/ - 0.15 6 PIN 1 INDEX AREA 6 PIN #1 INDEX AREA 1 4 4 8X 0.30 8X 0.400 ± 0.10 TOP VIEW 0.10 M C A B 2.38 +0.10/ - 0.15 BOTTOM VIEW SEE DETAIL "X" ( 2.38 ) ( 1.95) 0.10 C Max 1.00 C 0.08 C SIDE VIEW ( 8X 0.60) (1.64) ( 2.80 ) PIN 1 C 0 . 2 REF 5 (6x 0.65) 0 . 00 MIN. 0 . 05 MAX. ( 8 X 0.30) DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. 19 The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. FN7623.1 December 16, 2010