RFD14N06L, RFD14N06LSM, RFP14N06L
Data Sheet
July 1999
14A, 60V, 0.100 Ohm, Logic Level,
N-Channel Power MOSFETs
• 14A, 60V
Formerly developmental type TA09870.
Ordering Information
PACKAGE
4088.3
Features
These are N-Channel power MOSFETs manufactured using
the MegaFET process. This process, which uses feature
sizes approaching those of LSI integrated circuits, gives
optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
drivers and relay drivers. This performance is accomplished
through a special gate oxide design which provides full rated
conductance at gate bias in the 3V - 5V range, thereby
facilitating true on-off power control directly from logic level
(5V) integrated circuits.
PART NUMBER
File Number
• rDS(ON) = 0.100Ω
• Temperature Compensating PSPICE® Model
• Can be Driven Directly from CMOS, NMOS, and TTL
Circuits
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175oC Operating Temperature
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
BRAND
RFD14N06L
TO-251AA
14N06L
RFD14N06LSM
TO-252AA
14N06L
RFP14N06L
TO-220AB
FP14N06L
D
G
NOTE: When ordering, use the entire part number. Add the suffix 9A, to
obtain the TO-252AA variant in tape and reel, i.e. RFD14N06LSM9A.
S
Packaging
JEDEC TO-251AA
JEDEC TO-252AA
DRAIN (FLANGE)
SOURCE
DRAIN
GATE
DRAIN (FLANGE)
GATE
SOURCE
JEDEC TO-220AB
SOURCE
DRAIN
GATE
DRAIN (FLANGE)
6-1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
RFD14N06L, RFD14N06LSM, RFP14N06LS
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg
RFD14N06L, RFD14N06LSM,
RFP14N06LS
60
60
±10
14
Refer to Peak Current Curve
Refer to UIS Curve
48
0.32
-55 to 175
UNITS
V
V
V
A
W
W/oC
oC
oC
oC
300
260
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
BVDSS
ID = 250µA, VGS = 0V, Figure 13
60
-
-
V
Gate Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA, Figure 12
1
-
2
V
-
-
1
µA
-
-
50
µA
VGS = ±10V
-
-
100
nA
ID = 14A, VGS = 5V
-
-
0.100
Ω
VDD = 30V, ID = 7A,
RL = 4.28Ω, VGS = 5V,
RGS = 0.6Ω
Figures 10, 18, 19
-
-
60
ns
-
13
-
ns
-
24
-
ns
td(OFF)
-
42
-
ns
tf
-
16
-
ns
tOFF
-
-
100
ns
-
-
40
nC
-
-
25
nC
-
-
1.5
nC
-
670
-
pF
-
185
-
pF
-
50
-
pF
Zero Gate Voltage Drain Current
IDSS
Gate to Source Leakage Current
IGSS
On Resistance
rDS(ON)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
Fall Time
Turn-Off Time
VDS = 48V,
VGS = 0V
Total Gate Charge
Qg(TOT)
VGS = 0V to 10V
Gate Charge at 5V
Qg(5)
VGS = 0V to 5V
Qg(TH)
VGS = 0V to 1V
Threshold Gate Charge
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
Thermal Resistance Junction-to-Case
RθJC
Thermal Resistance Junction-to-Ambient
RθJA
TC = 25oC
TC = 150oC
VDD = 48V,
ID = 14A,
RL = 3.43Ω
Figures 20, 21
VDS = 25V, VGS = 0V,
f = 1MHz
Figure 14
-
-
3.125
oC/W
TO-251 and TO-252
-
-
100
oC/W
TO-220
-
-
80
oC/W
MIN
TYP
MAX
UNITS
ISD = 14A
-
-
1.5
V
ISD = 14A, dISD/dt = 100A/µs
-
-
125
ns
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Diode Voltage
Reverse Recovery Time
VSD
trr
6-2
TEST CONDITIONS
RFD14N06L, RFD14N06LSM, RFP14N06L
Typical Performance Curves
Unless Otherwise Specified
16
POWER DISSIPATION MULTIPLIER
1.2
ID, DRAIN CURRENT (A)
1.0
0.8
0.6
0.4
12
8
4
0.2
0
125
50
75
100
TC , CASE TEMPERATURE (oC)
25
0
150
0
175
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
25
50
75
100
125
TC, CASE TEMPERATURE (oC)
150
175
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
0.5
0.2
PDM
0.1
0.1
0.05
t1
t2
0.02
0.01
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA + TA
SINGLE PULSE
0.01
10-5
10-4
10-2
10-1
10-3
t, RECTANGULAR PULSE DURATION (s)
100
101
ID, DRAIN CURRENT (A)
100
IDM, PEAK CURRENT CAPABILITY (A)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
TC = 25oC
TJ = MAX RATED
100µs
10
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1
1
10ms
100ms
DC
10
100
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
6-3
200
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
100
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
175 – T C
I = I 25 ---------------------
150
VGS = 5V
TC = 25oC
VGS = 10V
10
10-5
10-4
10-3
10-2
10-1
t, PULSE WIDTH (s)
100
FIGURE 5. PEAK CURRENT CAPABILITY
101
RFD14N06L, RFD14N06LSM, RFP14N06L
Typical Performance Curves
Unless Otherwise Specified (Continued)
35
VGS = 10V
VGS = 5V
VGS = 4.5V
30
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
50
STARTING TJ = 25oC
10
STARTING TJ = +150oC
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
25
0.01
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
TC = 25oC
20
15
VGS = 3V
10
5
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS-VDD) +1]
1
VGS = 4V
0.1
1
tAV, TIME IN AVALANCHE (ms)
0
10
VGS = 2.5V
1.5
6.0
3.0
4.5
VDS , DRAIN TO SOURCE VOLTAGE (V)
0
7.5
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
35
VDD = 15V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
30
FIGURE 7. SATURATION CHARACTERISTICS
250
25oC
-55oC
175oC
25
20
15
10
rDS(ON) , DRAIN TO SOURCE
ON RESISTANCE (mΩ)
IDS(ON), DRAIN TO SOURCE CURRENT (A)
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
ID = 7A
ID = 28A
ID = 14A
150
100 ID = 3.5A
50
5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0
0
1.5
3.0
4.5
6.0
VGS, GATE TO SOURCE VOLTAGE (V)
0
2.5
7.5
FIGURE 8. TRANSFER CHARACTERISTICS
5.0
2.5
VDD = 25V, ID = 14A, RL = 1.78Ω
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
td(OFF)
140
120
100
tr
80
tf
60
40
td(ON)
20
0
3.0
3.5
4.0
4.5
VGS , GATE TO SOURCE VOLTAGE (V)
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
160
SWITCHING TIME (ns)
200
0
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 10. SWITCHING TIME vs GATE TO SOURCE
RESISTANCE
6-4
50
VGS = 5V, ID = 14A
2.0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
1.5
1.0
0.5
0
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
200
RFD14N06L, RFD14N06LSM, RFP14N06L
Unless Otherwise Specified (Continued)
2.0
2.0
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
NORMALIZED GATE
THRESHOLD VOLTAGE
VGS = VDS, ID = 250µA
1.5
1.0
0.5
0
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
1.5
1.0
0.5
0
-80
200
-40
0
40
80
120
60
VDS, DRAIN-SOURCE VOLTAGE (V)
CISS
600
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
COSS
200
CRSS
5
10
15
20
VDS, DRAIN TO SOURCE VOLTAGE (V)
10
VDD = BVDSS
VDD = BVDSS
45
7.5
30
5.0
0.75 BVDSS
0.50 BVDSS
0.25 BVDSS
15
2.5
RL = 3.57Ω
IG(REF) = 0.4mA
VGS = 5V
0
0
I G ( REF )
0
0
200
FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
800
400
160
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
C, CAPACITANCE (pF)
ID = 250µA
20 ---------------------I G ( ACT )
25
t, TIME (ms)
I G ( REF )
80 ---------------------I G ( ACT )
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS
BVDSS
L
VARY tP TO OBTAIN
REQUIRED PEAK IAS
tP
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
0V
tP
IAS
0
0.01Ω
tAV
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
6-5
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
VGS, GATE-SOURCE VOLTAGE (V)
Typical Performance Curves
RFD14N06L, RFD14N06LSM, RFP14N06L
Test Circuits and Waveforms
(Continued)
tON
tOFF
td(ON)
td(OFF)
tf
tr
RL
VDS
90%
90%
+
RG
-
VDD
10%
10%
0
DUT
90%
VGS
VGS
0
FIGURE 18. SWITCHING TIME TEST CIRCUIT
0.2µF
50%
PULSE WIDTH
10%
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
VDS
(ISOLATED
SUPPLY)
CURRENT
REGULATOR
12V
BATTERY
50%
SAME TYPE
AS DUT
50kΩ
VDD
Qg(TOT)
VDS
0.3µF
VGS = 10V
Qg(5)
D
VGS = 5V
VGS
DUT
G
VGS = 1V
0
IG(REF)
S
0
IG CURRENT
SAMPLING
RESISTOR
Qg(TH)
VDS
ID CURRENT
SAMPLING
RESISTOR
FIGURE 20. GATE CHARGE TEST CIRCUIT
6-6
IG(REF)
0
FIGURE 21. GATE CHARGE WAVEFORMS
RFD14N06L, RFD14N06LSM, RFP14N06L
PSPICE Electrical Model
.SUBCKT RFP14N06L 2 1 3 ;
CA 12 8 1.464e-9
CB 15 14 1.64e-9
CIN 6 8 6.17e-10
rev 9/15/94
DPLCAP
LDRAIN
DBODY 7 5 DBDMOD
DBREAK 5 11 DBKMOD
DPLCAP 10 5 DPLCAPMOD
DRAIN
2
RSCL1
RSCL2
+ 51
5
51
EBREAK 11 7 17 18 65.35
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1
DBREAK
ESCL
50
ESG
+
GATE
1
IT 8 17 1
6
8
11
RDRAIN
16
VTO
EVTO
9
20 + 18
8
LGATE RGATE
LDRAIN 2 5 1e-9
LGATE 1 9 5.68e-9
LSOURCE 3 7 5.35e-9
+
21
6
RBREAK 17 18 RBKMOD 1
RDRAIN 50 16 RDSMOD 33.1e-3
RGATE 9 20 5.85
RIN 6 8 1e9
RSCL1 5 51 RSCLMOD 1e-6
RSCL2 5 50 1e3
RSOURCE 8 7 RDSMOD 14.3e-3
RVTO 18 19 RVTOMOD 1
DBODY
MOS2
CIN
8
RSOURCE
7
LSOURCE
3
SOURCE
S2A
S1A
12
+
EBREAK 17
18
MOS1
RIN
MOS1 16 6 8 8 MOSMOD M = 0.99
MOS2 16 21 8 8 MOSMOD M = 0.01
S1A
S1B
S2A
S2B
5
10
13
8
S1B
RBREAK
15
14
13
17
18
S2B
RVTO
13
CA
CB
+
EGS
6
8
EDS
+ 14
5
8
IT
19
VBAT
+
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 8 19 DC 1
VTO 21 6 0.485
ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/46,7))}
.MODEL DBDMOD D (IS = 2.23e-13 RS = 1.15e-2 TRS1 = 1.64e-3 TRS2 = 7.89e-6 CJO = 6.83e-10 TT = 3.68e-8)
.MODEL DBKMOD D (RS = 3.8e-1 TRS1 = 1.89e-3 TRS2 = 1.13e-5)
.MODEL DPLCAPMOD D (CJO = 25.7e-11 IS = 1e-30 N = 10)
.MODEL MOSMOD NMOS (VTO = 1.935 KP = 18.89 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 7.18e-4 TC2 = 1.53e-6)
.MODEL RDSMOD RES (TC1 = 4.45e-3 TC2 = 2.9e-5)
.MODEL RSCLMOD RES (TC1 = 2.8e-3 TC2 = 6.0e-6)
.MODEL RVTOMOD RES (TC1 = -1.7e-3 TC2 = -2.0e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.55 VOFF= -1.55)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.55 VOFF= -3.55)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.55 VOFF= 2.45)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.45 VOFF= -2.55)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature
Options; authored by William J. Hepp and C. Frank Wheatley.
6-7
RFD14N06L, RFD14N06LSM, RFP14N06L
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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6-8
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