RFD15N06LE, RFD15N06LESM
Data Sheet
15A, 60V, 0.065 Ohm, ESD Rated, Logic
Level, N-Channel Power MOSFETs
These are N-Channel power MOSFETs manufactured using
the MegaFET process. This process, which uses feature
sizes approaching those of LSI circuits, gives optimum
utilization of silicon, resulting in outstanding performance.
They were designed for use in applications such as
switching regulators, switching converters, motor drivers,
and relay drivers. These transistors can be operated directly
from integrated circuits.
Formerly developmental type TA49165.
PACKAGE
File Number
4079.1
Features
• 15A, 60V
• rDS(ON) = 0.065Ω
• 2kV ESD Protected
• Temperature Compensating PSPICE™ Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175oC Operating Temperature
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Ordering Information
PART NUMBER
April 1999
BRAND
RFD15N06LE
TO-251AA
F15N6L
RFD15N06LESM
TO-252AA
F15N6L
Symbol
D
NOTE: When ordering, use the entire part number. For ordering in tape
and reel, add the suffix 9A to the part number, i.e. RFD15N06LESM9A.
G
S
Packaging
JEDEC TO-251AA
JEDEC TO-252AA
SOURCE
DRAIN
GATE
DRAIN (FLANGE)
DRAIN (FLANGE)
GATE
SOURCE
6-149
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE™ is a trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
RFD15N06LE, RFD15N06LESM
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD
Derate above 25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, TSTG
Electrostatic Discharge Rating MIL-STD-883, Category B(2) . . . . . . . . . . . . . . ESD
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
RFD15N06LE, RFD15N06LESM
60
60
±10
15
Refer to Peak Current Curve
Refer to UIS Curve
72
0.48
-55 to 175
2
UNITS
V
V
V
A
300
260
oC
oC
W
W/oC
oC
kV
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
BVDSS
ID = 250µA, VGS = 0V, Figure 13
60
-
-
V
Gate Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA, Figure 12
1
-
2
V
-
-
1
µA
-
-
50
µA
Zero Gate Voltage Drain Current
IDSS
Gate to Source Leakage Current
IGSS
Drain to Source On Resistance
rDS(ON)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
VDS = 48V,
VGS = 0V
VGS = ±10V
-
-
10
µA
ID = 15A, VGS = 5V
-
-
0.065
Ω
VDD = 30V, ID = 15A, RL = 2.0Ω,
VGS = 5V, RGS = 2.5Ω
Figures 10, 18, 19
-
-
77
ns
-
11
-
ns
tr
-
40
-
ns
td(OFF)
-
30
-
ns
tf
-
18
-
ns
tOFF
-
-
75
ns
Total Gate Charge
Qg(TOT)
VGS = 0V to 10V
Gate Charge at 5V
Qg(5)
VGS = 0V to 5V
Qg(TH)
VGS = 0V to 1V
Threshold Gate Charge
TC = 25oC
TC = 150oC
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
RθJA
VDD = 48V,
ID = 15A,
RL = 3.20Ω
Figures 20, 21
VDS = 25V, VGS = 0V,
f = 1MHz
Figure 14
-
39
49
nC
-
21
26
nC
-
0.95
1.20
nC
-
855
-
pF
-
240
-
pF
CRSS
-
75
-
pF
RθJC
-
-
2.08
oC/W
-
-
100
oC/W
TO-251 and TO-252
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Diode Voltage
VSD
Diode Reverse Recovery Time
trr
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ISD = 15A
-
-
1.5
V
ISD = 15A, dISD/dt = 100A/µs
-
-
80
ns
NOTES:
2. Pulse Test: Pulse Width ≤ 300ms, Duty Cycle ≤ 2%.
3. Repetitive Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance Curve (Figure 3) and Peak Current
Capability Curve (Figure 5).
6-150
RFD15N06LE, RFD15N06LESM
Typical Performance Curves
Unless Otherwise Specified
20
POWER DISSIPATION MULTIPLIER
1.2
ID, DRAIN CURRENT (A)
1.0
0.8
0.6
0.4
15
10
5
0.2
0
25
0
0
125
50
75
100
TC , CASE TEMPERATURE (oC)
25
175
150
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
50
75
100
125
TC, CASE TEMPERATURE (oC)
150
175
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
THERMAL IMPEDANCE
ZθJC, NORMALIZED
1
0.5
0.2
0.1
PDM
0.1
t1
t2
0.05
0.02
0.01
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
t, RECTANGULAR PULSE DURATION (s)
100
101
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
200
TC = 25oC, TJ = MAX RATED
ID, DRAIN CURRENT (A)
100
100µs
10
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
10ms
100ms
DC
60
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
6-151
100
IDM, PEAK CURRENT CAPABILITY (A)
200
TC = 25oC
VGS = 10V
100
VGS = 5V
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
175 - TC
I = I25
150
THERMAL IMPEDANCE
MAY LIMIT CURRENT
IN THIS REGION
10
10-5
10-4
10-3
10-2
10-1
t, PULSE WIDTH (s)
100
FIGURE 5. PEAK CURRENT CAPABILITY
101
RFD15N06LE, RFD15N06LESM
Typical Performance Curves
Unless Otherwise Specified (Continued)
30
STARTING TJ = 25oC
STARTING TJ = 150oC
10
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
VGS = 5V
VGS = 4V
20
VGS = 3.5V
15
10
VGS = 3V
5
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
1
0.001
TC = 25oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
VGS = 10V
25
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
50
VGS = 2.5V
0.01
0.1
1
tAV, TIME IN AVALANCHE (ms)
0
10
0
1.5
3.0
4.5
VDS, DRAIN TO SOURCE VOLTAGE (V)
6.0
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
200
25oC
-55oC
VDD = 15V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
25
175oC
20
15
10
5
0
ON RESISTANCE (mΩ)
30
FIGURE 7. SATURATION CHARACTERISTICS
rDS(ON), DRAIN TO SOURCE
IDS(ON), DRAIN TO SOURCE CURRENT (A)
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
ID = 15A
ID = 30A
ID = 7.5A
100
ID = 3.75A
50
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0
1.5
3
4.5
VGS, GATE TO SOURCE VOLTAGE (V)
0
2.0
6
2.5
3.5
3.0
4.0
4.5
5.0
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
250
2.5
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
VDD = 30 V, ID =15A, RL= 2.00Ω
200
SWITCHING TIME (ns)
150
td(OFF)
150
tr
100
tf
50
VGS = 5V, ID = 15A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
2.0
1.5
1.0
td(ON)
0
0
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 10. SWITCHING TIME vs GATE RESISTANCE
6-152
50
0.5
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
200
RFD15N06LE, RFD15N06LESM
Unless Otherwise Specified (Continued)
1.2
1.2
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
NORMALIZED GATE
THRESHOLD VOLTAGE
VGS = VDS, ID = 250µA
1.0
0.8
0.6
0.4
-80
-40
0
40
80
120
160
VDS , DRAIN TO SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
CISS
800
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
600
400
COSS
200
CRSS
5
10
15
20
VDS, DRAIN TO SOURCE VOLTAGE (V)
0.9
-40
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
200
5.00
60
VDD = BVDSS
VDD = BVDSS
3.75
45
RL =4.00Ω
IG(REF) = 0.44mA
VGS = 5V
2.50
30
15
0
0
1.0
FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
1200
1000
1.1
0.8
-80
200
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
ID = 250µA
PLATEAU VOLTAGES IN
DESCENDING ORDER:
VDD = BVDSS
VDD = 0.75 BVDSS
VDD = 0.50 BVDSS
VDD = 0.25 BVDSS
0
0
I G ( REF )
20 ------------------------I G ( ACT )
25
1.25
t, TIME (ms)
I G ( REF )
80 ------------------------I G ( ACT )
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS
BVDSS
L
VARY tP TO OBTAIN
REQUIRED PEAK IAS
tP
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
0V
tP
IAS
0
0.01Ω
tAV
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
6-153
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
VGS , GATE TO SOURCE VOLTAGE (V)
Typical Performance Curves
RFD15N06LE, RFD15N06LESM
Test Circuits and Waveforms
(Continued)
tON
tOFF
td(ON)
td(OFF)
VDS
VDS
VGS
tf
tr
RL
90%
90%
+
VGS
-
10%
10%
0
0V
90%
DUT
RGS
VGS
0
50%
10%
FIGURE 18. SWITCHING TIME TEST CIRCUIT
50%
PULSE WIDTH
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 10V
VGS
Qg(5)
+
VDD
DUT
IG(REF)
VGS = 5V
VGS
-
VGS = 1V
0
Qg(TH)
IG(REF)
0
FIGURE 20. GATE CHARGE TEST CIRCUIT
6-154
FIGURE 21. GATE CHARGE WAVEFORMS
RFD15N06LE, RFD15N06LESM
PSPICE Electrical Model
SUBCKT RFD15N06LE 2 1 3 ;
rev 5/13/95
CA 12 8 2.50e-9
CB 15 14 2.4e-9
CIN 6 8 7.70e-10
LDRAIN
DPLCAP
10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DESD1 91 9 DESD1MOD
DESD2 91 7 DESD2MOD
DPLCAP 10 5 DPLCAPMOD
RLDRAIN
ESG
LGATE
RLGATE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 14.52e-3
RGATE 9 20 2.6
RLDRAIN 2 5 10
RLGATE 1 9 27.7
RLSOURCE 3 7 29.8
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 20.05e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
DBREAK
11
50
GATE
1
LDRAIN 2 5 1e-9
LGATE 1 9 2.77e-9
LSOURCE 3 7 2.98e-9
RSLC1
51
+
5
ESLC
51
RSLC2
EBREAK 11 7 17 18 65.18
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
DRAIN
2
5
+
EBREAK 17
18
RDRAIN
16
6
8
+
EVTHRES
+ 19
8
EVTEMP
RGATE +
18
9
20 22
21
6
DBODY
MWEAK
MMED
MSTRO
DESD1
91
DESD2
LSOURCE
CIN
RSOURCE
8
SOURCE
3
7
RLSOURCE
S1A
12
13
8
S2A
15
14
13
S1B
RBREAK
18
17
S2B
13
CA
RVTEMP
CB
+
EGS
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
6
8
EDS
IT
14
+
19
VBAT
5
8
+
8
22
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*72),5))}
.MODEL DBODYMOD D (IS = 6.5e-13 RS = 1.20e-2 TRS1 = 1.75e-3 TRS2 = 5.08e-6 CJO = 7.45e-10 TT = 4.61e-8 M = 0.46)
.MODEL DBREAKMOD D (RS = 1.28e-1 TRS1 = -2.15e-3 TRS2 = 1.05e-5)
.MODEL DESD1MOD D (BV = 12.7 TBV1 = 0 TBV2 = 0 RS = 35 TRS1 = 1.2e-6 TRS2 = 0)
.MODEL DESD2MOD D (BV = 12.7 TBV1 = 0 TBV2 = 0 RS = 0 TRS1 =0 TRS2 = 0)
.MODEL DPLCAPMOD D (CJO = 4.32e-10 IS = 1e-30 N = 10 M = 0.54)
.MODEL MMEDMOD NMOS (VTO = 1.60 KP = 1.75 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.60)
.MODEL MSTROMOD NMOS (VTO = 1.93 KP = 26.0 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.39 KP = 0.09 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 26.0 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 9.76e-4 TC2 = 5.11e-7)
.MODEL RDRAINMOD RES (TC1 = 1.30e-2 TC2 = 4.49e-5)
.MODEL RSLCMOD RES (TC1 =3.00e-3 TC2 = 6.00e-6)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -1.43e-3 TC2 = -6.72e-6)
.MODEL RVTEMPMOD RES (TC1 = -9.91e-4 TC2 = 1.02e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.85 VOFF = -1.85)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.85 VOFF = -4.85)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.35 VOFF = 1.65)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.65 VOFF = -1.35
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature
Options; IEEE Power Electronics Specialist Conference Records, 1991.
6-155
RFD15N06LE, RFD15N06LESM
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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6-156
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