RFG60P03, RFP60P03, RF1S60P03SM Data Sheet July 1999 60A, 30V, 0.027 Ohm, P-Channel Power MOSFETs • 60A, 30V Formerly developmental type TA49045. Ordering Information PACKAGE 3951.3 Features These P-Channel power MOSFETs are manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers and relay drivers. These transistors can be operated directly from integrated circuits. PART NUMBER File Number • rDS(ON) = 0.027Ω • Temperature Compensating PSPICE® Model • Peak Current vs Pulse Width Curve • UIS Rating Curve • 175oC Operating Temperature • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol BRAND D RFG60P03 TO-247 RFG60P03 RFP60P03 TO-220AB RFP60P03 RF1S60P03SM TO-263AB F1S60P03 G NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-263AB variant in tape and reel, i.e. RF1S60P03SM9A. S Packaging JEDEC STYLE TO-247 JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (FLANGE) DRAIN (BOTTOM SIDE METAL) SOURCE DRAIN GATE JEDEC TO-263AB DRAIN (FLANGE) GATE SOURCE 4-140 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. PSPICE® is a registered trademark of MicroSim Corporation. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 RFG60P03, RFP60P03, RF1S60P03SM Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDSS Drain to Gate Voltage, (Rgs = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Continuous Drain Current (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Single Pulse Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Maximum Power Dissipation (Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ , TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg RFG60P03, RFP60P03, RFS60P03SM -30 -30 ±20 60 Refer to Peak Current Curve Figure 6 176 1.17 -55 to 175 UNITS V V V A 300 260 oC oC W W/oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage PARAMETER SYMBOL BVDSS ID = 250µA, VGS = 0V (Figure 11) -30 - - V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 10) -2 - -4 V VDS = Rated BVDSS, VGS = 0V - - -1 µA VDS = 0.8 x Rated BVDSS, TC = 150oC - - -50 µA VGS = ±20V - - ±100 nA ID = 60A, VGS = 10V - - 0.027 Ω VDD = 15V, ID ≈ 60A, RL = 0.25Ω, VGS = -10V, RG = 2.5Ω, (Figure 13) - - 140 ns Zero Gate Voltage Drain Current IDSS Gate to Source Leakage Current Drain to Source On Resistance (Note 2) IGSS rDS(ON) Turn-On Time tON Turn-On Delay Time td(ON) - 20 - ns tr - 75 - ns td(OFF) - 35 - ns tf - 40 - ns Rise Time Turn-Off Delay Time Fall Time Turn-Off Time tOFF Total Gate Charge Qg(TOT) VGS = 0 to -20V Gate Charge at 10V Qg(-10) VGS = 0 to -10V Threshold Gate Charge Qg(TH) VGS = 0 to -2V Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS Thermal Resistance, Junction to Case Thermal Resistance, Junction to Ambient VDD = -24V, ID ≈ 60A, RL = 0.4Ω Ig(REF) = -3mA - - 115 ns - 190 230 nC - 100 120 nC - 7.5 9 nC VDS = 25V, VGS = 0V, f = 1MHz (Figure 12) - 3000 - pF - 1500 - pF - 525 - pF RθJC (Figure 3) - - 0.85 oC/W RθJA TO-220AB, TO- 263AB - - 62 oC/W TO-247 - - 30 oC/W Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage (Note 2) Diode Reverse Recovery Time SYMBOL VSD trr TEST CONDITIONS MIN TYP MAX UNITS ISD = -60A - - -1.75 V ISD = -60A, dISD/dt = 100A/µs - - 200 ns NOTE: 2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3) 4-141 RFG60P03, RFP60P03, RF1S60P03SM Unless Otherwise Specified 1.2 -70 1.0 -60 ID , DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER Typical Performance Curves 0.8 0.6 0.4 0.2 -50 -40 -30 -20 -10 0 0 0 25 50 75 100 125 150 175 25 50 TC , CASE TEMPERATURE (oC) 75 100 125 150 175 TC , CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE ZθJC, NORMALIZED THERMAL IMPEDANCE 1 0.5 PDM 0.2 0.1 0.1 t1 0.05 t2 NOTES: 0.02 0.01 DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 t , RECTANGULAR PULSE DURATION (s) 100 101 FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE -103 -500 TC = 25oC -100 1ms 10ms -10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 100ms DC TC = 25oC TJ = MAX RATED -1 -1 -10 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA 4-142 -60 IDM , PEAK CURRENT (A) ID , DRAIN CURRENT (A) 100µs FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT CAPABILITY AS FOLLOWS: 175 – T C I = I 25 ------------------------ 150 VGS = -20V VGS = -10V -102 -50 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10-6 10-5 10-4 10-3 10-2 10-1 t , PULSE WIDTH (ms) 100 FIGURE 5. PEAK CURRENT CAPABILITY 101 RFG60P03, RFP60P03, RF1S60P03SM Typical Performance Curves Unless Otherwise Specified (Continued) -120 VGS = -20V STARTING TJ = 25oC VGS = -10V -100 ID, DRAIN CURRENT (A) IAS , AVALANCHE CURRENT (A) -200 STARTING TJ = 150oC If R = 0 tAV = (L) (IAS) / (1.3RATED BVDSS - VDD) -90 VGS = -8V PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TC = 25oC -60 VGS = -7V VGS = -6V -30 If R ≠ 0 VGS = -4.5V VGS = -5V tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1] -10 0.01 0 0.1 1 tAV, TIME IN AVALANCHE (ms) 0 10 -1.5 -3.0 -4.5 -6.0 -7.5 VDS , DRAIN TO SOURCE VOLTAGE (V) NOTE: Refer to Intersil Application Notes AN9321 and AN9322. -120 FIGURE 7. SATURATION CHARACTERISTICS 2 -55oC PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = -15V NORMALIZED DRAIN TO SOURCE ON RESISTANCE IDS(ON), DRAIN TO SOURCE CURRENT (A) FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING 25oC -90 175oC -60 -30 0 0 -2 -4 -6 -8 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 1.5V, ID = 60A 1.5 1 0.5 0 -80 -10 FIGURE 8. TRANSFER CHARACTERISTICS 40 80 120 160 200 2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250µA NORMALIZED GATE THRESHOLD VOLTAGE 0 FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 2 1.5 1 0.5 0 -80 -40 TJ , JUNCTION TEMPERATURE (oC) VGS , GATE TO SOURCE VOLTAGE (V) -40 0 40 80 120 160 200 TJ , JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 4-143 ID = 250µA 1.5 1 0.5 0 -80 -40 0 40 80 120 160 200 TJ , JUNCTION TEMPERATURE (oC) FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE RFG60P03, RFP60P03, RF1S60P03SM Unless Otherwise Specified -10 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGS 4000 CISS 3000 COSS 2000 CRSS 1000 VDS , DRAIN TO SOURCE VOLTAGE (V) -30 5000 C, CAPACITANCE (pF) (Continued) VDD = BVDSS -7.5 -22.5 RL = 0.5Ω IG(REF) = -3mA VGS = -10V 0.75 BVDSS 0.75 BV -15 -7.5 0 -5 -10 -15 -20 -5.0 DSS 0 0 VDD = BVDSS -25 20 VDS , DRAIN TO SOURCE VOLTAGE (V) 0.50 BVDSS 0.50 BVDSS 0.25 BVDSS 0.25 BVDSS IG(REF) t, TIME (µs) IG(ACT) 80 -2.5 0 IG(REF) IG(ACT) NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms VDS tAV L 0 VARY tP TO OBTAIN REQUIRED PEAK IAS - RG + 0V VGS VDD DUT VDD tP IAS IAS VDS tP 0.01Ω BVDSS FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORM tON tOFF td(OFF) td(ON) tr VDS 0 RL tf 10% 10% VGS VDS VDD + VGS DUT RGS VGS 0 90% 90% 10% 50% 50% PULSE WIDTH 90% FIGURE 16. SWITCHING TIME TEST CIRCUIT 4-144 FIGURE 17. RESISTIVE SWITCHING WAVEFORMS VGS , GATE TO SOURCE VOLTAGE (V) Typical Performance Curves RFG60P03, RFP60P03, RF1S60P03SM Test Circuits and Waveforms (Continued) VDS RL VDS Qg(TH) 0 VGS = -2V VGS - Qg(-10) + DUT VGS = -10V -VGS VDD VGS = -20V VDD IG(REF) Qg(TOT) 0 IG(REF) FIGURE 18. GATE CHARGE TEST CIRCUIT 4-145 FIGURE 19. GATE CHARGE WAVEFORMS RFG60P03, RFP60P03, RF1S60P03SM PSPICE Electrical Model .SUBCKT RFP60P03 2 1 3 REV 6/21/94 CA 12 8 5.01e-9 CB 15 14 3.9e-9 CIN 6 8 3.09e-9 - 10 DBODY 5 7 DBDMOD DBREAK 7 11 DBKMOD DPLCAP 10 6 DPLCAPMOD 5 6 + 8 ESG + RDRAIN EBREAK 5 11 17 18 -36.59 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 5 10 8 6 1 EVTO 20 6 8 18 1 DRAIN 2 LDRAIN EBREAK DPLCAP 17 18 - 11 DBODY 16 VTO GATE IT 8 17 1 9 1 LGATE LDRAIN 2 5 1e-9 LGATE 1 9 4.92e-9 LSOURCE 3 7 2.36e-9 20 EVTO + 18 21 - 8 RGATE + MOS1 6 RIN S1A 12 RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 1e-4 RGATE 9 20 3.25 RIN 6 8 1e9 RSOURCE 8 7 RDSMOD 11.28e-3 RVTO 18 19 RVTOMOD 1 RSOURCE 7 LSOURCE 3 SOURCE S2A 14 13 13 8 S1B RBREAK 15 17 18 S2B 13 RVTO CB CA DBREAK CIN 8 MOS1 16 6 8 8 MOSMOD M=0.99 MOS2 16 21 8 8 MOSMOD M=0.01 MOS2 + EGS - 6 8 + EDS - 14 5 8 IT 19 VBAT + S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 -0.92 .MODEL DBDMOD D (IS=4.21e-13 RS=1e-2 TRS1=-2.69e-4 TRS2=-1.33e-6 CJO=5.05e-9 TT=5.33e-8) .MODEL DBKMOD D (RS=3.80e-2 TRS1=-4.76e-4 TRS2=-4.17e-12) .MODEL DPLCAPMOD D (CJO=4.05e-9 IS=1e-30 N=10) .MODEL MOSMOD PMOS (VTO=-3.98 KP=16.27 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL RBKMOD RES (TC1=8.05e-4 TC2=1.48e-6) .MODEL RDSMOD RES (TC1=2.80e-3 TC2=2.62e-6) .MODEL RVTOMOD RES (TC1=-3.34e-3 TC2=1.46e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=7.5 VOFF=4.5) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=4.5 VOFF=7.5) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=1.43 VOFF=-3.57) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.57 VOFF=1.43) .ENDS NOTE: For further discussion of the PSPICE model consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; authors, William J. Hepp and C. Frank Wheatley. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 4-146