RFW2N06RLE Data Sheet July 1999 2A, 60V, 0.160 Ohm, Logic Level, N-Channel Power MOSFET File Number 2838.3 Features • 2A, 60V The RFW2N06RLE N-Channel, logic level, ESD protected, power MOSFET is manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits, gives optimum utilization of silicon, resulting in outstanding performance. The RFW2N06RLE was designed for use with logic level (5V) driving sources in applications such as programmable controllers, automotive switching, switching regulators, switching converters, motor and relay drivers and emitter switches for bipolar transistors. This performance is accomplished through a special gate oxide design which provides full rated conductance at gate biases in the 3V to 5V range, thereby facilitating true on-off power control directly from logic circuit supply voltages. • rDS(on) = 0.160Ω • UIS Rating Curve (Single Pulse) • Design Optimized For 5 Volt Gate Drive • Can be Driven Directly from CMOS, NMOS, TTL Circuits • Compatible with Automotive Drive Requirements • SOA is Power Dissipation Limited • Nanosecond Switching Speeds • Linear Transfer Characteristics • High Input Impedance • Majority Carrier Device Formerly developmental type TA9861. • Electrostatic Discharge Protected Ordering Information PART NUMBER RFW2N06RLE PACKAGE HEXDIP BRAND RFW2N06RLE • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol NOTE: When ordering, use the entire part number. D G S Packaging 4 PIN HEXDIP DRAIN GATE SOURCE 6-283 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 RFW2N06RLE Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation (Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor (Figure 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Electrostatic Discharge Rating, MIL-STD-883, Catagory B(2). . . . . . . . . . . . . . . . . . . . . . . .ESD Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg RFW2N06RLE 60 60 2 14 -5 to 10 1.09 0.009 Refer to UIS Curve 2 -55 to 150 UNITS V V A A V W W/oC 300 260 oC oC KV oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BVDSS ID =250µA, VGS = 0V 60 - - V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA 1 - 2 V Zero Gate Voltage Drain Current IDSS Gate to Source Leakage Current Drain to Source On Resistance (Note 2) IGSS rDS(ON) Turn-On Time t(ON) Turn-On Delay Time td(ON) Rise Time Turn-Off Delay Time - - 1 µA - - 25 µA VGS =-5V to 10V - - ±100 nA ID = 2A, VGS = 5V (Figure 8) - - 160 mΩ ID = 2A, VGS = 4.3V (Figure 8) - - 200 mΩ VDD = 30V, ID = 2A, RL = 15Ω, VGS = 5V, RG = 25Ω (Figures 12, 13, 14) - - 100 ns - 13 - ns tr - 42 - ns td(OFF) - 95 - ns tf - 45 - ns - 200 ns - 20 30 nC - 11 16 nC - 0.6 1.0 nC Fall Time Turn-Off Time VDS = Rated BVDSS, VGS = 0V VDS = 0.8 x Rated BVDSS, VGS = 0V TC = 125oC t(OFF) Total Gate Charge Qg(TOT) VGS = 0 to 10V Gate Charge at 5V Qg(5) VGS = 0 to 5V Qg(TH) VGS = 0 to 1V Threshold Gate Charge Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance Thermal Resistance, Junction to Ambient VDD = 48V, ID = 2A, IG(REF) =0.5mA, RL = 24Ω (Figures 12, 15, 16) VDS = 25V, VGS = 0V, f = 1MHz (Figure 11) - 535 - pF - 175 - pF CRSS - 32 - pF RθJA - - 115 oC/W MIN TYP MAX UNITS ISD = 2A - - 1.2 V ISD = 2A, dlSD/dt = 100A/µs - - 200 ns Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage (Note 2) Reverse Recovery Time SYMBOL VSD trr TEST CONDITIONS NOTES: 2. Pulse test: width ≤ 300µs duty cycle ≤ 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. 6-284 RFW2N06RLE Typical Performance Curves Unless Otherwise Specified 2.5 POWER DISSIPATION MULTIPLIER 1.2 1.0 ID, DRAIN CURRENT (A) 2.0 0.8 0.6 0.4 1.5 1.0 0.5 0.2 0 0 0 25 50 75 100 TC , CASETEMPERATURE (oC) 25 150 125 50 IF R ≠ 0 tav = (L/R) IN ((Ias x R) / (1.3 RATED BVDSS - VDD) + 1) Idm 1 IAS (A) ID, DRAIN CURRENT, (A) ID MAX CONTINUOUS OPERATION IN THIS AREA IS LIMITED BY rDS(ON) 0.01 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 5V 4V PULSE DURATION = 250µs DUTY CYCLE = 0.5% MAX TC = 25oC 10 3V 5 2V 1 2 3 4 5 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 5. SATURATION CHARACTERISTICS 6-285 0.1 1 TAV, TIME IN AVALANCHE (ms) 10 FIGURE 4. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY IDS(ON), DRAIN TO SOURCE CURRENT (A) ID, DRAIN TO SOURCE CURRENT (A) 10V STARTING TJ = 25oC STARTING TJ = 150oC 10 1 0.01 100 FIGURE 3. FORWARD BIAS SAFE OPERATING AREA 15 150 IF R = 0 tav = (L)(Ias) / (1.3 RATED BVDSS - VDD) TJ = MAX RATED TC = 25oC 0.10 125 100 FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 10 0 75 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE 0 50 6 15 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = 15V -55oC 25oC 150oC 10 5 0 0 1 2 3 4 5 VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 6. TRANSFER CHARACTERISTICS 6 RFW2N06RLE Typical Performance Curves 2.5 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX ID = 2A NORMALIZED DRAIN TO SOURCE ON RESISTANCE 1.25 1.00 0.75 0.50 4.0 4.5 5.0 5.5 6.0 6.5 VGS, GATE TO SOURCE VOLTAGE (V) 1.5 1.0 0.5 0 -50 7.0 0 100 150 FIGURE 8. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 1.50 1.50 ID = 250µA NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250µA 1.25 1.00 0.75 0.50 0.25 -50 0 50 100 1.25 1.00 0.75 0.50 -50 150 0 TJ , JUNCTION TEMPERATURE (oC) 50 100 FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 10 60 VDS, DRAIN TO SOURCE VOLTAGE (V) 1500 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGS 1200 900 600 CISS 300 COSS CRSS RL = 30Ω IG(REF) = 0.5mA VGS = 5V 45 0.75 BVDSS 0.50 BVDSS 0.25 BVDSS 30 VDD = BVDSS 15 GATE SOURCE VOLTAGE 0.75 BVDSS 0.50 BVDSS 0.25 BVDSS VDD = BVDSS DRAIN SOURCE VOLTAGE 0 0 0 5 10 15 150 TJ , JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE C, CAPACITANCE (pF) 50 TJ , JUNCTION TEMPERATURE (oC) FIGURE 7. NORMALIZED DRAIN TO SOURCE ON VOLTAGE vs GATE VOLTAGE NORMALIZED GATE THRESHOLD VOLTAGE 2.0 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 5V, ID = 2A 20 25 VDS, DRAIN TO SOURCE VOLTAGE (V) I 20 G(REF) IG(ACT) t, TIME (µs) 5 0 I 80 G(REF) IG(ACT) NOTE: Refer to Harris Application Notes AN7254 and AN7260. FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 6-286 FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT VGS, GATE TO SOURCE VOLTAGE (V) NORMALIZED DRAIN TO SOURCE ON RESISTANCE 1.50 Unless Otherwise Specified (Continued) RFW2N06RLE Test Circuits and Waveforms tON tOFF td(ON) td(OFF) VDS VDS VGS tf tr RL 90% 90% + VGS - 10% 10% 0 0V 90% DUT RGS VGS 0 50% 50% PULSE WIDTH 10% FIGURE 13. SWITCHING TIME TEST CIRCUIT FIGURE 14. RESISTIVE SWITCHING WAVEFORMS VDS VDD RL Qg(TOT) VDS VGS = 10V VGS Qg(5) + VDD DUT VGS = 5V VGS - VGS = 1V IG(REF) 0 Qg(TH) IG(REF) 0 FIGURE 15. GATE CHARGE TEST CIRCUIT FIGURE 16. GATE CHARGE WAVEFORMS All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. 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