Revised August 2000 100329 Low Power Octal ECL/TTL Bidirectional Translator with Register General Description Features The 100329 is an octal registered bidirectional translator designed to convert TTL logic levels to 100K ECL logic levels and vice versa. The direction of the translation is determined by the DIR input. A LOW on the output enable input (OE) holds the ECL outputs in a cut-off state and the TTL outputs at a high impedance level. The outputs change synchronously with the rising edge of the clock input (CP) even though only one output is enabled at the time. ■ Bidirectional translation ■ ECL high impedance outputs ■ Registered outputs ■ FAST TTL outputs ■ 3-STATE outputs ■ Voltage compensated operating range = −4.2V to −5.7V ■ High drive IOS The cut-off state is designed to be more negative than a normal ECL LOW level. This allows the output emitter-followers to turn off when the termination supply is −2.0V, presenting a high impedance to the data bus. This high impedance reduces the termination power and prevents loss of low state noise margin when several loads share the bus. The 100329 is designed with FAST TTL output buffers, featuring optimal DC drive and capable of quickly charging and discharging highly capacitive loads. All inputs have 50 kΩ pull-down resistors. Ordering Code: Order Number 100329PC Package Number N24E Package Description 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 100329QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 100329QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (−40°C to +85°C) Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagrams 24-Pin DIP 28-Pin PLCC FAST is a registered trademark of Fairchild Semiconductor Corporation. © 2000 Fairchild Semiconductor Corporation DS010583 www.fairchildsemi.com 100329 Low Power Octal ECL/TTL Bidirectional Translator with Register August 1989 100329 Logic Symbol Functional Diagram Pin Descriptions Pin Names E0–E7 Description ECL Data I/O T0–T7 TTL Data I/O OE Output Enable Input CP Clock Pulse Input (Active Rising Edge) DIR Direction Control Input All pins function at 100K ECL levels except for T0–T7. Truth Table OE ECL TTL Port Port DIR CP L L X Input L H X LOW L H L (Cut-Off) H H L H H H H H H L L Z Notes (Note 1)(Note 3) Input (Note 2)(Note 3) L L (Note 1) H H (Note 1) X NC (Note 1)(Note 3) L L (Note 2) H H (Note 2) NC X (Note 2)(Note 3) Note: DIR and OE use ECL logic levels H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance = LOW-to-HIGH Clock Transition NC = No Change Detail Note 1: ECL input to TTL output mode. Note 2: TTL input to ECL output mode. Note 3: Retains data present before CP. www.fairchildsemi.com 2 Storage Temperature (TSTG) Recommended Operating Conditions −65°C to +150°C Maximum Junction Temperature (Tj) +150°C VEE Pin Potential to Ground Pin −7.0V to +0.5V VTTL Pin Potential to Ground Pin −0.5V to +6.0V ECL Input Voltage (DC) 0°C to +85°C Case Temperature (TC) VEE to +0.5V ECL Supply Voltage (VEE) −5.7V to −4.2V TTL Supply Voltage (VTTL) +4.5V to +5.5V ECL Output Current −50 mA (DC Output HIGH) TTL Input Voltage (Note 6) −0.5V to +6.0V TTL Input Current (Note 6) −30 mA to +5.0 mA Voltage Applied to Output Note 4: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. in HIGH State 3-STATE Output −0.5V to +5.5V Current Applied to TTL Output in LOW State (Max) twice the rated IOL (mA) Note 5: ESD testing conforms to MIL-STD-883, Method 3015. ≥2000V ESD (Note 5) Note 6: Either voltage limit or current limit is sufficient to protect inputs. TTL-to-ECL DC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C, VTTL = +4.5V to +5.5V (Note 7) Symbol Parameter Min Typ Max Units VOH VOL Output HIGH Voltage −1025 −955 −870 mV Output LOW Voltage −1830 −1705 −1620 mV Cutoff Voltage Conditions VIN = VIH (Max) or VIL (Min) Loading with 50Ω to −2V OE or DIR LOW, −2000 −1950 mV VIN = VIH (Max) or VIL (Min) Loading with 50Ω to −2V VOHC Output HIGH Voltage Corner Point HIGH VOLC mV −1035 VIN = VIH (Min) or VIL (Max) Output LOW Voltage Corner Point LOW −1610 mV Loading with 50Ω to −2V VIH Input HIGH Voltage 2.0 5.0 V Over VTTL, V EE, TC Range VIL Input LOW Voltage 0 0.8 V Over VTTL, V EE, TC Range IIH Input HIGH Current 70 µA VIN = +2.7V Breakdown Test 1.0 mA VIN = +5.5V −700 µA VIN = +0.5V −1.2 V IIN = −18 mA IIL Input LOW Current VFCD Input Clamp Diode Voltage IEE VEE Supply Current LE LOW, OE and DIR HIGH Inputs Open −189 −94 −199 −94 mA VEE = −4.2V to −4.8V VEE = −4.2V to −5.7V Note 7: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. 3 www.fairchildsemi.com 100329 Absolute Maximum Ratings(Note 4) 100329 ECL-to-TTL DC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C, CL = 50 pF, VTTL = +4.5V to +5.5V (Note 8) Symbol Parameter Min Typ Max Units Conditions VOH Output HIGH Voltage 2.7 3.1 V IOH = −3 mA, VTTL = 4.75V 2.4 2.9 V IOH = −3 mA, VTTL = 4.50V VOL Output LOW Voltage 0.5 V IOL = 24 mA, VTTL = 4.50V VIH Input HIGH Voltage −1165 −870 mV Guaranteed HIGH Signal VIL Input LOW Voltage −1830 −1475 mV Guaranteed LOW Signal IIH Input HIGH Current 350 µA VIN = VIH (Max) IIL Input LOW Current µA VIN = VIL (Min) IOZHT 3-STATE Current µA VOUT = +2.7V µA VOUT = +0.5V −100 mA VOUT = 0.0V, VTTL = +5.5V 74 mA TTL Outputs LOW 49 mA TTL Outputs HIGH 67 mA TTL Outputs in 3-STATE 0.3 for All Inputs for All Inputs 0.50 70 Output HIGH IOZLT −700 3-STATE Current Output LOW IOS −225 Output Short-Circuit Current ITTL VTTL Supply Current Note 8: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. DIP TTL-to-ECL AC Electrical Characteristics VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V, VCC = VCCA = GND TC = 0°C TC = 25°C Symbol Parameter Min Max Min Max 350 TC = 85°C Min Max 350 Units Conditions fMAX Max Toggle Frequency 350 tPLH CP to En 1.7 3.6 1.7 3.7 1.9 3.9 MHz ns Figures 1, 2 OE to En 1.3 4.2 1.5 4.4 1.7 4.8 ns Figures 1, 2 1.5 4.5 1.6 4.5 1.6 4.6 ns Figures 1, 2 1.6 4.3 1.6 4.3 1.7 4.5 ns Figures 1, 2 tPHL tPZH (Cutoff to HIGH) tPHZ OE to En (HIGH to Cutoff) tPHZ DIR to En (HIGH to Cutoff) tSET Tn to CP 1.1 1.1 1.1 ns Figures 1, 2 tHOLD Tn to CP 1.7 1.7 1.9 ns Figures 1, 2 tPW(H) Pulse Width CP 2.1 2.1 2.1 ns Figures 1, 2 tTLH Transition Time 0.6 ns Figures 1, 2 tTHL 20% to 80%, 80% to 20% www.fairchildsemi.com 1.6 0.6 4 1.6 0.6 1.6 100329 DIP ECL-to-TTL AC Electrical Characteristics VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V, VCC = VCCA = GND, CL = 50 pF TC = 0°C TC = 25°C Symbol Parameter Min Max Min Max Min fMAX Max Toggle Frequency 125 125 tPLH CP to Tn 3.1 7.2 125 3.1 7.2 TC = 85°C Units Conditions Max MHz 3.3 7.7 ns Figures 3, 4 ns Figures 3, 5 ns Figures 3, 5 ns Figures 3, 6 tPHL tPZH OE to Tn 3.4 8.45 3.7 8.95 4.0 9.7 tPZL (Enable Time) 3.8 9.2 4.0 9.2 4.3 9.95 tPHZ OE to Tn 3.2 8.95 3.3 8.95 3.5 9.2 tPLZ (Disable Time) 3.0 7.7 3.4 8.7 4.1 9.95 tPHZ DIR to Tn 2.7 8.2 2.8 8.7 3.1 8.95 tPLZ (Disable Time) 2.8 7.45 3.1 7.95 4.0 9.2 tSET En to CP 1.1 1.1 1.1 ns Figures 3, 4 tHOLD En to CP 2.1 2.1 2.6 ns Figures 3, 4 tPW(H) Pulse Width CP 4.1 4.1 4.1 ns Figures 3, 4 PLCC and TTL-to-ECL AC Electrical Characteristics VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V Symbol Parameter TC = 0°C Min Max TC = 25°C Min Max 350 TC = 85°C Min Max 350 Units Conditions fMAX Max Toggle Frequency 350 tPLH CP to En 1.7 3.4 1.7 3.5 1.9 3.7 MHz ns Figures 1, 2 OE to En 1.3 4.0 1.5 4.2 1.7 4.6 ns Figures 1, 2 1.5 4.3 1.6 4.3 1.6 4.4 ns Figures 1, 2 1.6 4.1 1.6 4.1 1.7 4.3 ns Figures 1, 2 tPHL tPZH (Cutoff to HIGH) tPHZ OE to En (HIGH to Cutoff) tPHZ DIR to En (HIGH to Cutoff) tSET Tn to CP 1.0 1.0 1.0 ns Figures 1, 2 tHOLD Tn to CP 1.7 1.7 1.9 ns Figures 1, 2 tPW(H) Pulse Width CP 2.0 2.0 2.0 ns Figures 1, 2 tTLH Transition Time 0.6 1.6 ns Figures 1, 2 tTHL 20% to 80%, 80% to 20% tOSHL Maximum Skew Common Edge Output-to-Output Variation 1.6 0.6 1.6 0.6 PLCC Only 200 200 200 ps 200 200 200 ps 650 650 650 ps 650 650 650 ps (Note 9) Data to Output Path tOSLH Maximum Skew Common Edge Output-to-Output Variation PLCC Only (Note 9) Data to Output Path tOST Maximum Skew Opposite Edge Output-to-Output Variation PLCC Only (Note 9) Data to Output Path tPS Maximum Skew Pin (Signal) Transition Variation PLCC Only (Note 9) Data to Output Path Note 9: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite directions both HL and LH (tOST ). Parameters tOST and tPS guaranteed by design. 5 www.fairchildsemi.com 100329 PLCC and ECL-to-TTL AC Electrical Characteristics VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V, CL = 50 pF TC = 0°C Symbol Parameter Min Max fMAX Max Toggle Frequency 125 tPLH CP to Tn 3.1 7.0 TC = 25°C Min Max 125 TC = 85°C Min 125 3.1 7.0 3.3 Units Conditions Max MHz 7.5 ns Figures 3, 4 ns Figures 3, 5 ns Figures 3, 5 ns Figures 3, 6 Figures 3, 4 tPHL tPZH OE to Tn 3.4 8.25 3.7 8.75 4.0 9.5 tPZL (Enable Time) 3.8 9.0 4.0 9.0 4.3 9.75 tPHZ OE to Tn 3.2 8.75 3.3 8.75 3.5 9.0 tPLZ (Disable Time) 3.0 7.5 3.4 8.5 4.1 9.75 tPHZ DIR to Tn 2.7 8.0 2.8 8.5 3.1 8.75 tPLZ (Disable Time) 2.8 7.25 3.1 7.75 4.0 9.0 tSET En to CP 1.0 1.0 1.0 ns tHOLD En to CP 2.0 2.0 2.5 ns Figures 3, 4 tPW(H) Pulse Width CP 4.0 4.0 4.0 ns Figures 3, 4 tOSHL Maximum Skew Common Edge Output-to-Output Variation PLCC Only 600 600 600 ps 850 850 850 ps 1350 1350 1350 ps 950 950 950 ps (Note 10) Data to Output Path tOSLH Maximum Skew Common Edge Output-to-Output Variation PLCC Only (Note 10) Data to Output Path tOST Maximum Skew Opposite Edge Output-to-Output Variation PLCC Only (Note 10) Data to Output Path tPS Maximum Skew Pin (Signal) Transition Variation PLCC Only (Note 10) Data to Output Path Note 10: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite directions both HL and LH (tOST). Parameters tOST and tPS guaranteed by design. www.fairchildsemi.com 6 100329 Test Circuitry (TTL-to-ECL) Note 11: RT = 50Ω termination resistive load. When an input or output is being monitored by a scope, RTis supplied by the scope’s 50Ω input resistance. When an input or output is not being monitored, an external 50Ω resistance must be applied to serve as RT. Note 12: TTL and ECL force signals are brought to the DUT via 50Ω coax lines. Note 13: VTTL is decoupled to ground with 0.1 µF, VEE is decoupled to ground with 0.01 µF and VCC is connected to ground. FIGURE 1. TTL-to-ECL AC Test Circuit Switching Waveforms (TTL-to-ECL) FIGURE 2. TTL to ECL Transition—Propagation Delay and Transition Times 7 www.fairchildsemi.com 100329 Test Circuitry (ECL-to-TTL) Note 14: RT = 50Ω termination resistive load. When an input or output is being monitored by a scope, RT is supplied by the scope’s 50Ω input resistance. When an input or output is not being monitored, an external 50Ω resistance must be applied to serve as RT. Note 15: The TTL 3-STATE pull-up switch is connected to +7V only for ZL and LZ tests. Note 16: TTL and ECL force signals are brought to the DUT via 50Ω coax lines. Note 17: VTTL is decoupled to ground with 0.1 µF, VEE is decoupled to ground with 0.01 µF and VCC is connected to ground. FIGURE 3. ECL-to-TTL AC Test Circuit www.fairchildsemi.com 8 100329 Switching Waveforms (ECL-to-TTL) Note: DIR is LOW, OE is HIGH FIGURE 4. ECL-to-TTL Transition—Propagation Delay and Transition Times Note: DIR is LOW FIGURE 5. ECL-to-TTL Transition, OE to TTL Output, Enable and Disable Times Note: OE is HIGH FIGURE 6. ECL-to-TTL Transition, DIR to TTL Output, Disable Time 9 www.fairchildsemi.com 100329 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E www.fairchildsemi.com 10 100329 Low Power Octal ECL/TTL Bidirectional Translator with Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 11 www.fairchildsemi.com