Revised August 2000 100329A Low Power Octal ECL/TTL Bidirectional Translator with Register General Description Features The 100329A is an octal registered bidirectional translator designed to convert TTL logic levels to 100K ECL logic levels and vice versa. The direction of the translation is determined by the DIR input. A LOW on the output enable input (OE) holds the ECL outputs in a cut-off state and the TTL outputs at a high impedance level. The outputs change synchronously with the rising edge of the clock input (CP) even though only one output is enabled at the time. ■ Bidirectional translation ■ ECL high impedance outputs ■ Registered outputs ■ FAST TTL outputs ■ 3-STATE outputs ■ Voltage compensated operating range = −4.2V to −5.7V ■ High drive IOS The cut-off state is designed to be more negative than a normal ECL LOW level. This allows the output emitter-followers to turn off when the termination supply is −2.0V, presenting a high impedance to the data bus. This high impedance reduces the termination power and prevents loss of low state noise margin when several loads share the bus. The 100329A is designed with FAST TTL output buffers, featuring optimal DC drive and capable of quickly charging and discharging highly capacitive loads. All inputs have 50 kΩ pull-down resistors. Ordering Code: Order Number Package Number 100329APC N24E Package Description 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Logic Symbol Connection Diagram Pin Descriptions Pin Names E0–E7 Description ECL Data I/O T0–T7 TTL Data I/O OE Output Enable Input CP Clock Pulse Input (Active Rising Edge) DIR Direction Control Input All pins function at 100K ECL levels except for T0–T7. FAST is a registered trademark of Fairchild Semiconductor Corporation. © 2000 Fairchild Semiconductor Corporation DS500047 www.fairchildsemi.com 100329A Low Power Octal ECL/TTL Bidirectional Translator with Register August 1989 100329A Truth Table OE ECL TTL Port Port DIR CP Notes L L X Input Z 1, 3 L H X LOW Input 2, 3 H L [N] L L 1 H L [N] H H 1 H L L X NC 1, 3 H H [N] L L 2 H H [N] H H 2 H H L NC X 2, 3 (Cut-Off) H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance [N] = LOW-to-HIGH Clock Transition NC = No Change Functional Diagram Detail Note 1: ECL input to TTL output mode. Note 2: TTL input to ECL output mode. Note 3: Retains data present before CP. Note: DIR and OE use ECL logic levels www.fairchildsemi.com 2 Storage Temperature (TSTG) Recommended Operating Conditions −65°C to +150°C +150°C Maximum Junction Temperature (Tj) VEE Pin Potential to Ground Pin −7.0V to +0.5V VTTL Pin Potential to Ground Pin −0.5V to +6.0V VEE to +0.5V ECL Input Voltage (DC) 0°C to +85°C Case Temperature (TC) ECL Supply Voltage (VEE) −5.7V to −4.2V TTL Supply Voltage (VTTL) +4.5V to +5.5V ECL Output Current −50 mA (DC Output HIGH) TTL Input Voltage (Note 6) −0.5V to +6.0V TTL Input Current (Note 6) −30 mA to +5.0 mA Voltage Applied to Output Note 4: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. in HIGH State −0.5V to +5.5V 3-STATE Output Current Applied to TTL Output twice the rated IOL (mA) in LOW State (Max) Note 5: ESD testing conforms to MIL-STD-883, Method 3015. ≥2000V ESD (Note 5) Note 6: Either voltage limit or current limit is sufficient to protect inputs. TTL-to-ECL DC Electrical Characteristics (Note 7) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C, VTTL = +4.5V to +5.5V Min Typ Max Units VOH Symbol Output HIGH Voltage Parameter −1025 −955 −870 mV VIN = VIH (Max) or VIL (Min) VOL Output LOW Voltage −1830 −1705 −1620 mV Loading with 50Ω to −2V −2000 −1950 mV Cutoff Voltage Conditions OE or DIR LOW, VIN = VIH (Max) or VIL (Min) Loading with 50Ω to −2V VOHC Output HIGH Voltage Corner Point HIGH VOLC mV −1035 VIN = VIH (Min) or VIL (Max) Loading with 50Ω to −2V Output LOW Voltage Corner Point LOW −1610 mV VIH Input HIGH Voltage 2.0 5.0 V VIL Input LOW Voltage 0 0.8 V IIH Input HIGH Current 70 µA VIN = +2.7V 1.0 Input LOW Current VFCD Input Clamp Diode Voltage IEE Over VTTL, VEE, TC Range mA VIN = +5.5V −700 µA VIN = +0.5V −1.2 V IIN = −18 mA Breakdown Test IIL Over VTTL, VEE, TC Range VEE Supply Current LE LOW, OE and DIR HIGH Inputs OPEN −189 −94 −199 −94 mA VEE = −4.2V to −4.8V VEE = −4.2V to −5.7V Note 7: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. 3 www.fairchildsemi.com 100329A Absolute Maximum Ratings(Note 4) 100329A ECL-to-TTL DC Electrical Characteristics (Note 8) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C, CL = 50 pF, VTTL = +4.5V to +5.5V Symbol Parameter VOH Output HIGH Voltage VOL Output LOW Voltage Min Typ 2.7 3.1 2.4 Max Units Conditions IOH = −3 mA, VTTL = 4.75V V V IOH = −3 mA, VTTL = 4.50V 0.5 V IOL = 24 mA, VTTL = 4.50V 2.9 0.3 VIH Input HIGH Voltage −1165 −870 mV Guaranteed HIGH Signal for All Inputs VIL Input LOW Voltage −1830 −1475 mV Guaranteed LOW Signal for All Inputs IIH Input HIGH Current 350 µA VIN = VIH (Max) IIL Input LOW Current µA VIN = VIL (Min) IOZHT 3-STATE Current Output HIGH µA VOUT = +2.7V IOZLT 3-STATE Current Output LOW −700 µA VOUT = +0.5V IOS Output Short-Circuit Current −225 ITTL VTTL Supply Current 0.50 70 −100 mA VOUT = 0.0V, VTTL = +5.5V 74 mA TTL Outputs LOW 49 mA TTL Outputs HIGH 67 mA TTL Outputs in 3-STATE Note 8: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. DIP TTL-to-ECL AC Electrical Characteristics VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V, VCC = VCCA = GND TC = 0°C TC = 25°C Symbol Parameter Min Max Min Max 350 TC = 85°C Min Max 350 Units Conditions fMAX Max Toggle Frequency 350 tPLH CP to En 1.7 3.6 1.7 3.7 1.9 3.9 MHz ns Figures 1, 2 1.3 4.2 1.5 4.4 1.7 4.8 ns Figures 1, 2 1.5 4.5 1.6 4.5 1.6 4.6 ns Figures 1, 2 1.6 4.3 1.6 4.3 1.7 4.5 ns Figures 1, 2 tPHL tPZH OE to En (Cut-off to HIGH) tPHZ OE to En (HIGH to Cut-off) tPHZ DIR to En (HIGH to Cut-off) tset Tn to CP 1.1 1.1 1.1 ns Figures 1, 2 thold Tn to CP 1.7 1.7 1.9 ns Figures 1, 2 tpw(H) Pulse Width CP 2.1 2.1 2.1 ns Figures 1, 2 tTLH Transition Time tTHL 20% to 80%, 80% to 20% ns Figures 1, 2 0.6 1.6 0.6 1.6 0.6 1.6 DIP ECL-to-TTL AC Electrical Characteristics VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V, VCC = VCCA = GND, CL = 50.pF TC = 0°C TC = 25°C TC = 85°C Symbol Parameter Min Max Min Max Min Max fMAX Max Toggle Frequency 125 tPLH CP to Tn 3.1 7.2 125 125 3.1 7.2 3.3 Units Conditions MHz 7.7 ns Figures 3, 4 ns Figures 3, 5 ns Figures 3, 5 ns Figures 3, 6 Figures 3, 4 tPHL tPZH OE to Tn 3.4 8.45 3.7 8.95 4.0 9.7 tPZL (Enable Time) 3.8 9.2 4.0 9.2 4.3 9.95 tPHZ OE to Tn 3.2 8.95 3.3 8.95 3.5 9.2 tPLZ (Disable Time) 3.0 7.7 3.4 8.7 4.1 9.95 tPHZ DIR to Tn 2.7 8.2 2.8 8.7 3.1 8.95 tPLZ (Disable Time) 2.8 7.45 3.1 7.95 4.0 9.2 tset En to CP 1.1 1.1 1.1 ns thold En to CP 2.1 2.1 2.6 ns Figures 3, 4 tpw(H) Pulse Width CP 4.1 4.1 4.1 ns Figures 3, 4 www.fairchildsemi.com 4 100329A Test Circuitry (TTL-to-ECL) Note: RT = 50Ω termination resistive load. When an input or output is being monitored by a scope, RTis supplied by the scope’s 50Ω input resistance. When an input or output is not being monitored, an external 50Ω resistance must be applied to serve as RT. Note: TTL and ECL force signals are brought to the DUT via 50Ω coax lines. Note: VTTL is decoupled to ground with 0.1 µF, VEE is decoupled to ground with 0.01 µF and VCC is connected to ground. FIGURE 1. TTL-to-ECL AC Test Circuit Switching Waveforms (TTL-to-ECL) FIGURE 2. TTL to ECL Transition—Propagation Delay and Transition Times 5 www.fairchildsemi.com 100329A Test Circuitry (ECL-to-TTL) Note: RT = 50Ω termination resistive load. When an input or output is being monitored by a scope, RTis supplied by the scope’s 50Ω input resistance. When an input or output is not being monitored, an external 50Ω resistance must be applied to serve as R T. Note: The TTL 3-STATE pull-up switch is connected to +7V only for ZL and LZ tests. Note: TTL and ECL force signals are brought to the DUT via 50Ω coax lines. Note: VTTL is decoupled to ground with 0.1 µF, VEE is decoupled to ground with 0.01 µF and VCC is connected to ground. FIGURE 3. ECL-to-TTL AC Test Circuit Switching Waveforms (ECL-to-TTL) Note: DIR is LOW, OE is HIGH FIGURE 4. ECL-to-TTL Transition—Propagation Delay and Transition Times www.fairchildsemi.com 6 100329A Switching Waveforms (Continued) Note: DIR is LOW FIGURE 5. ECL-to-TTL Transition, OE to TTL Output, Enable and Disable Times Note: OE is HIGH FIGURE 6. ECL-to-TTL Transition, DIR to TTL Output, Disable Time 7 www.fairchildsemi.com 100329A Low Power Octal ECL/TTL Bidirectional Translator with Register Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8