54AC169 • 54ACT169 4-Stage Synchronous Bidirectional Counter General Description The ’AC/’ACT169 is fully synchronous 4-stage up/down counter. The ’AC/’ACT169 is a modulo-16 binary counter. It features a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the LOW-to-HIGH transition of the Clock. n n n n n n Synchronous counting and loading Built-In lookahead carry capability Presettable for programmable operation Outputs source/sink 24 mA ’ACT has TTL-compatible inputs Standard Microcircuit Drawing (SMD) 5962-91603 Features n ICC reduced by 50% Logic Symbols Pin Names DS100276-1 Description CEP Count Enable Parallel Input CET Count Enable Trickle Input CP Clock Pulse Input P0–P3 Parallel Data Inputs PE Parallel Enable Input U/D Up-Down Count Control Input Q0–Q3 Flip-Flop Outputs TC Terminal Count Output IEEE/IEC DS100276-2 FACT™ is a trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100276 www.national.com 54AC169 • 54ACT169 4-Stage Synchronous Bidirectional Counter July 1998 Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC DS100276-3 DS100276-4 Logic Diagram DS100276-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. data on the P0–P3 inputs enters the flip-flops on the next rising edge of the Clock. In order for counting to occur, both CEP and CET must be LOW and PE must be HIGH; the U/D input then determines the direction of counting. The Terminal Count (TC) output is normally HIGH and goes LOW, provided that CET is LOW, when a counter reaches zero in the Count Down mode or reaches 15 in the Count Up mode. The TC output state is not a function of the Count Enable Parallel (CEP) input level. If an illegal state occurs, the ’AC169 will return to the legitimate sequence within two counts. Since Functional Description The ’AC/’ACT169 uses edge-triggered J-K-type flip-flops and have no constraints on changing the control or data input signals in either state of the Clock. The only requirement is that the various inputs attain the desired state at least a setup time before the rising edge of the clock and remain valid for the recommended hold time thereafter. The parallel load operation takes precedence over the other operations, as indicated in the Mode Select Table. When PE is LOW, the www.national.com 2 Functional Description State Diagrams (Continued) the TC signal is derived by decoding the flip-flop states, there exists the possibility of decoding spikes on TC. For this reason the use of TC as a clock signal is not recommended (see logic equations below). 1. Count Enable = CEP • CET • PE 2. Up: TC = Q0 • Q1 • Q 2Q3 • (Up) • CET 3. Down: TC = Q0 • Q1 • Q2 • Q3 • (Down) • CET Mode Select Table DS100276-6 PE CEP CET U/D Action on Rising L X X X Load (Pn to Qn) H L L H Count Up (Increment) H L L L Count Down (Decrement) H H X X No Change (Hold) H X H X No Change (Hold) Clock Edge H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial 3 www.national.com Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP Supply Voltage (VCC) ’AC ’ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54AC/ACT Minimum Input Edge Rate (∆V/∆t) ’AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (∆V/∆t) ’ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA ± 50 mA −65˚C to +150˚C 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT™ circuits outside databook specifications. 175˚C DC Characteristics for ’AC Family Devices Symbol Parameter VCC 54AC TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits VIH VIL VOH Minimum High Level 3.0 2.1 Input Voltage 4.5 3.15 5.5 3.85 Maximum Low Level 3.0 0.9 Input Voltage 4.5 1.35 5.5 1.65 Minimum High Level 3.0 2.9 Output Voltage 4.5 4.4 5.5 5.4 VOUT = 0.1V V or VCC − 0.1V V or VCC − 0.1V VOUT = 0.1V IOUT = −50 µA V (Note 2) VIN = VIL or VIH VOL 3.0 2.4 4.5 3.7 5.5 4.7 Maximum Low Level 3.0 0.1 Output Voltage 4.5 0.1 5.5 0.1 IOH = −12 mA V IOH = −24 mA IOH = −24 mA IOUT = 50 µA V (Note 2) VIN = VIL or VIH IIN Maximum Input 3.0 0.50 4.5 0.50 5.5 0.50 5.5 ± 1.0 Leakage Current www.national.com 4 IOL = 12 mA V IOL = 24 mA µA IOL = 24 mA VI = VCC, GND DC Characteristics for ’AC Family Devices Symbol Parameter (Continued) VCC 54AC TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits Minimum Dynamic Output Current (Note 3) 5.5 50 mA IOHD 5.5 −50 mA VOLD = 1.65V Max VOHD = 3.85V Min ICC Maximum Quiescent 5.5 80.0 µA VIN = VCC IOLD Supply Current or GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ICC for 54AC @ 25˚C is identical to 74AC @ 25˚C. DC Characteristics for ’ACT Family Devices Symbol Parameter VCC 54ACT TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits VIH VIL VOH Minimum High Level 4.5 2.0 Input Voltage 5.5 2.0 Maximum Low Level 4.5 0.8 Input Voltage 5.5 0.8 Minimum High Level 4.5 4.4 Output Voltage 5.5 5.4 V VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V IOUT = −50 µA (Note 5) VIN = VIL or VIH VOL 4.5 3.70 5.5 4.70 Maximum Low Level 4.5 0.1 Output Voltage 5.5 0.1 V IOH = −24 mA V IOH = −24 mA IOUT = 50 µA (Note 5) VIN = VIL or VIH IIN Maximum Input 4.5 0.50 5.5 0.50 V IOL = 24 mA ± 1.0 µA IOL = 24 mA VI = VCC, GND 5.5 5.5 1.6 mA VI = VCC − 2.1V Leakage Current ICCT Maximum ICC/Input Minimum Dynamic Output Current (Note 6) 5.5 50 mA IOHD 5.5 −50 mA VOLD = 1.65V Max VOHD = 3.85V Min ICC Maximum Quiescent 5.5 80.0 µA VIN = VCC IOLD Supply Current or GND Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. Note 7: ICC for 54ACT @ 25˚C is identical to 74ACT @ 25˚C. 5 www.national.com AC Electrical Characteristics 54AC TA = −55˚C VCC Symbol Parameter (V) (Note 8) Min fmax tPLH Fig. to +125˚C CL = 50 pF Maximum Clock 3.3 55 Frequency 5.0 75 Units No. Max MHz Propagation Delay 3.3 1.0 15.0 CP to Qn 5.0 1.5 12.0 ns (PE HIGH or LOW) tPHL Propagation Delay 3.3 1.0 16.5 CP to Qn 5.0 1.5 13.0 ns ns (PE HIGH or LOW) tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay 3.3 3.0 22.0 CP to TC 5.0 3.0 16.0 Propagation Delay 3.3 3.0 22.0 CP to TC 5.0 3.0 16.0 Propagation Delay 3.3 1.0 18.5 CET to TC 5.0 1.5 13.0 Propagation Delay 3.3 1.0 16.0 CET to TC 5.0 1.5 11.0 Propagation Delay 3.3 1.0 18.5 U/D to TC 5.0 1.5 13.0 Propagation Delay 3.3 1.0 16.5 U/D to TC 5.0 1.5 12.0 ns ns ns ns ns Note 8: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements VCC Symbol Parameter (V) (Note 9) 54AC TA = −55˚C to +125˚C CL = 50 pF Fig. Units Guaranteed Minimum ts Setup Time, 3.3 7.0 HIGH or LOW 5.0 4.5 ns ns Pn to CP th ts Hold Time, HIGH or LOW 3.3 2.0 Pn to CP 5.0 2.5 Setup Time, 3.3 13.5 HIGH or LOW 5.0 9.0 ns ns CEP to CP th ts Hold Time, HIGH or LOW 3.3 0.5 CEP to CP 5.0 2.5 Setup Time, 3.3 13.5 HIGH or LOW 5.0 9.0 CET to CP www.national.com 6 ns No. AC Operating Requirements (Continued) 54AC TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 9) Fig. Units No. Guaranteed Minimum th ts Hold Time, HIGH or LOW 3.3 0.5 CET to CP 5.0 2.5 ns Setup Time, 3.3 8.5 HIGH or LOW 5.0 6.5 ns ns PE to CP th ts Hold Time, HIGH or LOW 3.3 0.5 PE to CP 5.0 2.0 Setup Time, 3.3 13.0 HIGH or LOW 5.0 9.0 ns ns U/D to CP th tw Hold Time, HIGH or LOW 3.3 0.5 U/D to CP 5.0 2.0 CP Pulse Width, 3.3 5.0 HIGH or LOW 5.0 5.0 ns Note 9: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V AC Electrical Characteristics 54ACT TA = −55˚C VCC Symbol Parameter (V) (Note 10) Min fmax Maximum Clock Fig. to +125˚C CL = 50 pF Units No. Max 5.0 75 MHz 5.0 1.5 12.5 ns 5.0 1.5 12.5 ns 5.0 1.5 16.5 ns 5.0 1.5 16.5 ns 5.0 1.5 13.5 ns 5.0 1.5 13.5 ns 5.0 1.5 14.5 ns 5.0 1.5 14.5 ns Frequency tPLH Propagation Delay CP to Qn (PE HIGH or LOW) tPHL Propagation Delay CP to Qn (PE HIGH or LOW) tPLH Propagation Delay CP to TC tPHL Propagation Delay CP to TC tPLH Propagation Delay CET to TC tPHL Propagation Delay CET to TC tPLH Propagation Delay U/D to TC tPHL Propagation Delay U/D to TC 7 www.national.com AC Electrical Characteristics (Continued) Note 10: Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements VCC Symbol Parameter (V) (Note 11) 54ACT TA = −55˚C to +125˚C CL = 50 pF Fig. Units Guaranteed Minimum ts Setup Time, HIGH or LOW 5.0 4.5 ns 5.0 2.5 ns 5.0 9.0 ns 5.0 2.5 ns 5.0 9.0 ns 5.0 2.5 ns 5.0 6.5 ns 5.0 2.0 ns 5.0 9.0 ns 5.0 2.0 ns 5.0 5.0 ns Pn to CP th Hold Time, HIGH or LOW Pn to CP ts Setup Time, HIGH or LOW CEP to CP th Hold Time, HIGH or LOW CEP to CP ts Setup Time, HIGH or LOW CET to CP th Hold Time, HIGH or LOW CET to CP ts Setup Time, HIGH or LOW PE to CP th Hold Time, HIGH or LOW PE to CP ts Setup Time, HIGH or LOW U/D to CP th Hold Time, HIGH or LOW U/D to CP tw CP Pulse Width, HIGH or LOW Note 11: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Symbol CIN CPD Typ Units Input Capacitance Parameter 4.5 pF Power Dissipation 60.0 pF Capacitance www.national.com 8 Conditions VCC = Open VCC = 5.0V No. Physical Dimensions inches (millimeters) unless otherwise noted 20-Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A 16-Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A 9 www.national.com 54AC169 • 54ACT169 4-Stage Synchronous Bidirectional Counter Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Ceramic Flatpak (F) NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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