1.2 MB

The following document contains information on Cypress products.
F2MC-16FX MB96680 Series
16-bit Proprietary Microcontroller
MB96F683R/A, MB96F685R/A
Data Sheet (Full Production)
Publication Number MB96680_DS704-00002
CONFIDENTIAL
Revision 2.1
Issue Date January 31, 2014
D a t a S h e e t
2
CONFIDENTIAL
MB96680_DS704-00002-2v1-E, January 31, 2014
F2MC-16FX MB96680 Series
16-bit Proprietary Microcontroller
MB96F683R/A, MB96F685R/A
Data Sheet (Full Production)
 DESCRIPTION
MB96680 series is based on Spansion’s advanced F2MC-16FX architecture (16-bit with instruction pipeline
for RISC-like performance). The CPU uses the same instruction set as the established F2MC-16LX family
thus allowing for easy migration of F2MC-16LX Software to the new F2MC-16FX products.
F2MC-16FX product improvements compared to the previous generation include significantly improved
performance - even at the same operation frequency, reduced power consumption and faster start-up time.
For high processing speed at optimized power consumption an internal PLL can be selected to supply the
CPU with up to 32MHz operation frequency from an external 4MHz to 8MHz resonator. The result is a
minimum instruction cycle time of 31.2ns going together with excellent EMI behavior. The emitted power
is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree
allows selecting suitable operation frequencies for peripheral resources independent of the CPU speed.
Spansion Inc. provides information facilitating product development via the following website.
The website contains information useful for customers.
http://www.spansion.com/Support/microcontrollers/Pages/default.aspx
Publication Number MB96680_DS704-00002
Revision 2.1
Issue Date January 31, 2014
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient
production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the
valid combinations offered may occur.
CONFIDENTIAL
D a t a S h e e t
 FEATURES
 Technology
0.18m CMOS
 CPU
 F2MC-16FX CPU
 Optimized instruction set for controller applications
(bit, byte, word and long-word data types, 23 different addressing modes, barrel shift, variety of pointers)
 8-byte instruction queue
 Signed multiply (16-bit  16-bit) and divide (32-bit/16-bit) instructions available
 System clock
 On-chip PLL clock multiplier (1 to 8, 1 when PLL stop)
 4MHz to 8MHz crystal oscillator
(maximum frequency when using ceramic resonator depends on Q-factor)
 Up to 8MHz external clock for devices with fast clock input feature
 32.768kHz subsystem quartz clock
100kHz/2MHz internal RC clock for quick and safe startup, clock stop detection function, watchdog
 Clock source selectable from mainclock oscillator, subclock oscillator and on-chip RC oscillator,
independently for CPU and 2 clock domains of peripherals
 The subclock oscillator is enabled by the Boot ROM program controlled by a configuration marker after a
Power or External reset
 Low Power Consumption - 13 operating modes (different Run, Sleep, Timer, Stop modes)
 On-chip voltage regulator
Internal voltage regulator supports a wide MCU supply voltage range (Min=2.7V), offering low power
consumption
 Low voltage detection function
Reset is generated when supply voltage falls below programmable reference voltage
 Code Security
Protects Flash Memory content from unintended read-out
 DMA
Automatic transfer function independent of CPU, can be assigned freely to resources
 Interrupts
 Fast Interrupt processing
 8 programmable priority levels
 Non-Maskable Interrupt (NMI)
 CAN
 Supports CAN protocol version 2.0 part A and B
 ISO16845 certified
 Bit rates up to 1Mbps
 32 message objects
 Each message object has its own identifier mask
 Programmable FIFO mode (concatenation of message objects)
 Maskable interrupt
 Disabled Automatic Retransmission mode for Time Triggered CAN applications
 Programmable loop-back mode for self-test operation
2
CONFIDENTIAL
MB96680_DS704-00002-2v1-E, January 31, 2014
D a t a S h e e t
 USART
 Full duplex USARTs (SCI/LIN)
 Wide range of baud rate settings using a dedicated reload timer
 Special synchronous options for adapting to different synchronous serial protocols
 LIN functionality working either as master or slave LIN device
 Extended support for LIN-Protocol to reduce interrupt load
 I2C
 Up to 400kbps
 Master and Slave functionality, 7-bit and 10-bit addressing
 A/D converter
 SAR-type
 8/10-bit resolution
 Signals interrupt on conversion end, single conversion mode, continuous conversion mode,
stop conversion mode, activation by software, external trigger, reload timers and PPGs
 Range Comparator Function
 Scan Disable Function
 ADC Pulse Detection Function
 Source Clock Timers
Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit Sub clock timer)
 Hardware Watchdog Timer
 Hardware watchdog timer is active after reset
 Window function of Watchdog Timer is used to select the lower window limit of the watchdog interval
 Reload Timers
 16-bit wide
 Prescaler with 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 of peripheral clock frequency
 Event count function
 Free-Running Timers
 Signals an interrupt on overflow
 Prescaler with 1, 1/21, 1/22, 1/23, 1/24, 1/25, 1/26, 1/27, 1/28 of peripheral clock frequency
 Input Capture Units
 16-bit wide
 Signals an interrupt upon external event
 Rising edge, Falling edge or Both (rising & falling) edges sensitive
 Programmable Pulse Generator
 16-bit down counter, cycle and duty setting registers
 Can be used as 2  8-bit PPG
 Interrupt at trigger, counter borrow and/or duty match
 PWM operation and one-shot operation
 Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock or of selected Reload timer
underflow as clock input
 Can be triggered by software or reload timer
 Can trigger ADC conversion
 Timing point capture
January 31, 2014, MB96680_DS704-00002-2v1-E
CONFIDENTIAL
3
D a t a S h e e t
 Stepping Motor Controller
 Stepping Motor Controller with integrated high current output drivers
 Four high current outputs for each channel
 Two synchronized 8/10-bit PWMs per channel
 Internal prescaling for PWM clock: 1, 1/4, 1/5, 1/6, 1/8, 1/10, 1/12, 1/16 of peripheral clock
 Dedicated power supply for high current output drivers
 LCD Controller
 LCD controller with up to 4COM  32SEG
 Internal or external voltage generation
 Duty cycle: Selectable from options: 1/2, 1/3 and 1/4
 Fixed 1/3 bias
 Programmable frame period
 Clock source selectable from four options (main clock, peripheral clock, subclock or RC oscillator clock)
 Internal divider resistors or external divider resistors
 On-chip data memory for display
 LCD display can be operated in Timer Mode
 Blank display: selectable
 All SEG, COM and V pins can be switched between general and specialized purposes
 Sound Generator
 8-bit PWM signal is mixed with tone frequency from 16-bit reload counter
 PWM clock by internal prescaler: 1, 1/2, 1/4, 1/8 of peripheral clock
 Real Time Clock
 Operational on main oscillation (4MHz), sub oscillation (32kHz) or RC oscillation (100kHz/2MHz)
 Capable to correct oscillation deviation of Sub clock or RC oscillator clock (clock calibration)
 Read/write accessible second/minute/hour registers
 Can signal interrupts every half second/second/minute/hour/day
 Internal clock divider and prescaler provide exact 1s clock
 External Interrupts
 Edge or Level sensitive
 Interrupt mask bit per channel
 Each available CAN channel RX has an external interrupt for wake-up
 Selected USART channels SIN have an external interrupt for wake-up
 Non Maskable Interrupt
 Disabled after reset, can be enabled by Boot-ROM depending on ROM configuration block
 Once enabled, can not be disabled other than by reset
 High or Low level sensitive
 Pin shared with external interrupt 0
 I/O Ports
 Most of the external pins can be used as general purpose I/O
 All push-pull outputs (except when used as I2C SDA/SCL line)
 Bit-wise programmable as input/output or peripheral signal
 Bit-wise programmable input enable
 One input level per GPIO-pin (either Automotive or CMOS hysteresis)
 Bit-wise programmable pull-up resistor
4
CONFIDENTIAL
MB96680_DS704-00002-2v1-E, January 31, 2014
D a t a S h e e t
 Built-in On Chip Debugger (OCD)
 One-wire debug tool interface
 Break function:
- Hardware break: 6 points (shared with code event)
- Software break: 4096 points
 Event function
- Code event: 6 points (shared with hardware break)
- Data event: 6 points
- Event sequencer: 2 levels + reset
 Execution time measurement function
 Trace function: 42 branches
 Security function
 Flash Memory
 Dual operation flash allowing reading of one Flash bank while programming or erasing the other bank
 Command sequencer for automatic execution of programming algorithm and for supporting DMA for
programming of the Flash Memory
 Supports automatic programming, Embedded Algorithm
 Write/Erase/Erase-Suspend/Resume commands
 A flag indicating completion of the automatic algorithm
 Erase can be performed on each sector individually
 Sector protection
 Flash Security feature to protect the content of the Flash
 Low voltage detection during Flash erase or write
January 31, 2014, MB96680_DS704-00002-2v1-E
CONFIDENTIAL
5
D a t a S h e e t
 PRODUCT LINEUP
Features
MB96680
Remark
Product Type
Subclock
Dual Operation Flash Memory
RAM
Flash Memory Product
Subclock can be set by software
-
64.5KB + 32KB
4KB
MB96F683R, MB96F683A
128.5KB + 32KB
4KB
MB96F685R, MB96F685A
Package
DMA
USART
with automatic LIN-Header
transmission/reception
with 16 byte RX- and
TX-FIFO
2
IC
8/10-bit A/D Converter
with Data Buffer
with Range Comparator
with Scan Disable
with ADC Pulse Detection
16-bit Reload Timer (RLT)
16-bit Free-Running Timer (FRT)
16-bit Input Capture Unit (ICU)
8/16-bit Programmable Pulse Generator
(PPG)
with Timing point capture
with Start delay
with Ramp
LQFP-80
FPT-80P-M21
2ch
2ch
LIN-USART 0/1
Yes (only 1ch)
LIN-USART 0
No
RLT 1/2/6
FRT 0/1
ICU 0/1/4/5
(ICU 0/1 for LIN-USART)
4ch (16-bit) / 8ch (8-bit)
PPG 0 to 3
Yes
No
No
1ch
Stepping Motor Controller (SMC)
External Interrupts (INT)
Non-Maskable Interrupt (NMI)
Sound Generator (SG)
2ch
7ch
1ch
1ch
Real Time Clock (RTC)
I/O Ports
Clock Calibration Unit (CAL)
Clock Output Function
Low Voltage Detection Function
I2C 0
AN 8 to 13/16 to 23
1ch
14ch
No
Yes
Yes
Yes
3ch
2ch
4ch
(2 channels for LIN-USART)
CAN Interface
LCD Controller
Product Options
R: MCU with CAN
A: MCU without CAN
CAN 0
32 Message Buffers
SMC 0/1
INT 0 to 4/6/7
SG 0
COM 0 to 3
SEG 1 to 12/19 to 24/
30/36 to 39/42/45 to 47/
52 to 56
4COM × 32SEG
1ch
63 (Dual clock mode)
65 (Single clock mode)
1ch
2ch
Yes
Low voltage detection
function can be
disabled by software
Hardware Watchdog Timer
Yes
On-chip RC-oscillator
Yes
On-chip Debugger
Yes
Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the general I/O port according to your function use.
6
CONFIDENTIAL
MB96680_DS704-00002-2v1-E, January 31, 2014
D a t a S h e e t
 BLOCK DIAGRAM
DEBUG I/F
CKOT0_R, CKOT1
CKOTX0, CKOTX1
X0, X1
X0A, X1A
RSTX
MD
NMI
Flash
Memory A
Interrupt
Controller
16FX
CPU
OCD
Clock &
Mode Controller
16FX Core Bus (CLKB)
Peripheral
Bus Bridge
Watchdog
I2C
1ch
AVcc
AVss
AVRH
AN8 to AN13
AN16 to AN23
ADTG
8/10-bit ADC
14ch
TIN1, TIN2
TIN1_R, TIN2_R
TOT1, TOT2
TOT1_R, TOT2_R
16-bit Reload
Timer
1/2/6
3ch
FRCK0, FRCK0_R
IN0, IN0_R, IN1, IN1_R
FRCK1
IN4_R, IN5_R
INT0 to INT4
INT6, INT7
INT1_R, INT2_R, INT3_R
I/O Timer 0
FRT 0
ICU 0/1
I/O Timer 1
FRT 1
ICU 4/5
External
Interrupt
7ch
COM0 to COM3
CAN
Interface
1ch
RX0
Voltage
Regulator
Vcc
Vss
C
TX0
Sound
Generator
1ch
USART
2ch
Boot ROM
SGO0
SGA0
SIN0, SIN1
SOT0, SOT1
SCK0, SCK1
TTG0, TTG1
PPG
4ch (16-bit) /
8ch (8-bit)
Stepping
Motor
Controller
2ch
PPG0, PPG1, PPG3
PPG0_R to PPG3_R
PPG0_B to PPG3_B
DVcc
DVss
PWM1P0, PWM1P1
PWM1M0, PWM1M1
PWM2P0, PWM2P1
PWM2M0, PWM2M1
WOT, WOT_R
LCD
controller/
driver
4COM×32SEG
January 31, 2014, MB96680_DS704-00002-2v1-E
CONFIDENTIAL
RAM
Real Time
Clock
V0 to V3
SEG1 to SEG12
SEG19 to SEG24
SEG30, SEG36 to SEG39
SEG42, SEG45 to SEG47
SEG52 to SEG56
Peripheral
Bus Bridge
Peripheral Bus 2 (CLKP2)
SDA0
SCL0
Peripheral Bus 1 (CLKP1)
DMA
Controller
7
D a t a S h e e t
 PIN ASSIGNMENT
P12_1 / SEG5 / TIN1_R / PPG0_B
50
49
48
47
46
45
43
42
P04_5 / SCL0*2
P17_0
44
Vss
51
DEBUG I/F
52
MD
53
X0
54
X1
P11_5 / SEG1
55
Vss
P11_6 / SEG2 / FRCK0_R
56
P04_0 / X0A*3
P11_7 / SEG3 / IN0_R
57
P04_1 / X1A*3
P11_0 / COM0
58
RSTX
P11_1 / COM1 / PPG0_R
59
P11_4 / PPG3_R
P11_2 / COM2 / PPG1_R
60
61
P11_3 / COM3 / PPG2_R
P12_0 / SEG4 / IN1_R
(Top view)
41
40
P04_4 / PPG3 / SD A0 *2
P13_6 / SCK0 / CKOTX0 / SEG47*1
P12_2 / SEG6 / TOT1_R / PPG1_B
62
39
P12_3 / SEG7
63
38
P13_5 / SOT0 / ADTG / INT7 / SEG46
P12_4 / SEG8
64
37
P13_4 / SIN0 / INT6 / SEG45*1
P12_5 / SEG9 / TIN2_R / PPG2_B
65
36
P13_3 / PPG1 / WOT
P12_6 / SEG10 / TOT2_R / PPG3_B
66
35
P13_2 / PPG0 / FRCK1
P12_7 / SEG11 / INT1_R
67
34
P08_7 / PWM2M1/ AN23
P00_0 / SEG12 / INT3_R
68
33
P08_6 / PWM2P1 / AN22
P01_1 / SEG21 / CKOT1
69
32
P08_5 / PWM1M1 / AN21
P01_2 / SEG22 / CKOTX1
70
31
P08_4 / PWM1P1 / AN20
P01_3 / SEG23
71
30
DVss
LQFP - 80
P03_6 / INT0 / NMI
79
22
P05_5 / AN13
Vcc
80
21
P05_4 / AN12 / INT2_R / WOT_R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
P05_3 / AN11
P05_6 / TIN2
P05_2 / AN10
23
AVss
78
AVRH
P05_7 / TOT2
P03_5 / TX0
AVcc
24
P05_1 / AN9
77
P05_0 / AN8
P08_0 / PWM1P0 / AN16
P03_4 / RX0 / INT4*1
P06_7 / TOT1 / SEG56 / IN5_R
25
P06_6 / TIN1 / SEG55 / IN4_R
76
P06_5 / IN1 / SEG54 / TTG1
P08_1 / PWM1M0 / AN17
P03_3 / SEG39 / V3
P06_4 / IN0 / SEG53 / TTG0
26
P06_3 / FRCK0 / SEG52
75
P02_2 / SEG30 / CKOT0_R
P08_2 / PWM2P0 / AN18
P03_2 / SEG38 / V2
P01_0 / SEG20 / SGA0
27
P00_7 / SEG19 / SGO0
74
P13_1 / INT3 / SCK1 / SEG42*1
P08_3 / PWM2M0 / AN19
P03_1 / SEG37 / V1
P13_0 / INT2 / SOT1
DVcc
28
P03_7 / INT1 / SIN1*1
29
73
C
72
Vss
P01_4 / SEG24
P03_0 / SEG36 / V0
(FPT-80P-M21)
*1: CMOS input level only
2
*2: CMOS input level only for I C
*3: Please set ROM Configuration Block (RCB) to use the subclock.
Other than those above, general-purpose pins have only Automotive input level.
8
CONFIDENTIAL
MB96680_DS704-00002-2v1-E, January 31, 2014
D a t a S h e e t
 PIN DESCRIPTION
Pin name
Feature
Description
ADTG
ANn
AVcc
AVRH
ADC
ADC
Supply
ADC
AVss
C
CKOTn
CKOTn_R
CKOTXn
COMn
Supply
Voltage regulator
Clock Output function
Clock Output function
Clock Output function
LCD
DEBUG I/F
DVcc
DVss
FRCKn
FRCKn_R
INn
OCD
Supply
Supply
Free-Running Timer
Free-Running Timer
ICU
On Chip Debugger input/output pin
SMC pins power supply
SMC pins power supply
Free-Running Timer n input pin
Relocated Free-Running Timer n input pin
Input Capture Unit n input pin
INn_R
INTn
INTn_R
MD
NMI
Pnn_m
ICU
External Interrupt
External Interrupt
Core
External Interrupt
GPIO
Relocated Input Capture Unit n input pin
External Interrupt n input pin
Relocated External Interrupt n input pin
Input pin for specifying the operating mode
Non-Maskable Interrupt input pin
General purpose I/O pin
PPGn
PPG
PPGn_R
PPG
PPGn_B
PWMn
RSTX
RXn
PPG
SMC
Core
CAN
SCKn
SCLn
SDAn
SEGn
SGAn
SGOn
USART
I2C
I2C
LCD
Sound Generator
Sound Generator
SINn
SOTn
TINn
TINn_R
USART
USART
Reload Timer
Reload Timer
USART n serial data input pin
USART n serial data output pin
Reload Timer n event input pin
Relocated Reload Timer n event input pin
A/D converter trigger input pin
A/D converter channel n input pin
Analog circuits power supply pin
A/D converter high reference voltage input pin
Analog circuits power supply pin
Internally regulated power supply stabilization capacitor pin
Clock Output function n output pin
Relocated Clock Output function n output pin
Clock Output function n inverted output pin
LCD Common driver pin
Programmable Pulse Generator n output pin (16bit/8bit)
Relocated Programmable Pulse Generator n output pin
(16bit/8bit)
Programmable Pulse Generator n output pin (16bit/8bit)
SMC PWM high current output pin
Reset input pin
CAN interface n RX input pin
USART n serial clock input/output pin
I2C interface n clock I/O input/output pin
I2C interface n serial data I/O input/output pin
LCD Segment driver pin
Sound Generator amplitude output pin
Sound Generator sound/tone output pin
TOTn
Reload Timer
Reload Timer n output pin
TOTn_R
TTGn
Reload Timer
PPG
Relocated Reload Timer n output pin
Programmable Pulse Generator n trigger input pin
TXn
Vn
CAN
LCD
Vcc
Supply
January 31, 2014, MB96680_DS704-00002-2v1-E
CONFIDENTIAL
CAN interface n TX output pin
LCD voltage reference pin
Power supply pin
9
D a t a S h e e t
Pin name
Feature
Vss
Supply
WOT
WOT_R
RTC
RTC
Real Time clock output pin
Relocated Real Time clock output pin
X0
Clock
Oscillator input pin
X0A
X1
Clock
Clock
Subclock Oscillator input pin
Oscillator output pin
X1A
Clock
Subclock Oscillator output pin
10
CONFIDENTIAL
Description
Power supply pin
MB96680_DS704-00002-2v1-E, January 31, 2014
D a t a S h e e t
 PIN CIRCUIT TYPE
Pin no.
I/O circuit type*
Pin name
1
Supply
Vss
2
F
C
3
M
P03_7 / INT1 / SIN1
4
H
P13_0 / INT2 / SOT1
5
P
P13_1 / INT3 / SCK1 / SEG42
6
J
P00_7 / SEG19 / SGO0
7
J
P01_0 / SEG20 / SGA0
8
J
P02_2 / SEG30 / CKOT0_R
9
J
P06_3 / FRCK0 / SEG52
10
J
P06_4 / IN0 / SEG53 / TTG0
11
J
P06_5 / IN1 / SEG54 / TTG1
12
J
P06_6 / TIN1 / SEG55 / IN4_R
13
J
P06_7 / TOT1 / SEG56 / IN5_R
14
K
P05_0 / AN8
15
K
P05_1 / AN9
16
Supply
AVcc
17
G
AVRH
18
Supply
AVss
19
K
P05_2 / AN10
20
K
P05_3 / AN11
21
K
P05_4 / AN12 / INT2_R / WOT_R
22
K
P05_5 / AN13
23
H
P05_6 / TIN2
24
H
P05_7 / TOT2
25
R
P08_0 / PWM1P0 / AN16
26
R
P08_1 / PWM1M0 / AN17
27
R
P08_2 / PWM2P0 / AN18
28
R
P08_3 / PWM2M0 / AN19
29
Supply
DVcc
30
Supply
DVss
31
R
P08_4 / PWM1P1 / AN20
32
R
P08_5 / PWM1M1 / AN21
33
R
P08_6 / PWM2P1 / AN22
34
R
P08_7 / PWM2M1 / AN23
35
H
P13_2 / PPG0 / FRCK1
36
H
P13_3 / PPG1 / WOT
37
P
P13_4 / SIN0 / INT6 / SEG45
38
J
P13_5 / SOT0 / ADTG / INT7 / SEG46
39
P
P13_6 / SCK0 / CKOTX0 / SEG47
40
N
P04_4 / PPG3 / SDA0
January 31, 2014, MB96680_DS704-00002-2v1-E
CONFIDENTIAL
11
D a t a S h e e t
Pin no.
I/O circuit type*
Pin name
41
N
P04_5 / SCL0
42
Supply
Vss
43
O
DEBUG I/F
44
H
P17_0
45
C
MD
46
A
X0
47
A
X1
48
Supply
Vss
49
B
P04_0 / X0A
50
B
P04_1 / X1A
51
C
RSTX
52
H
P11_4 / PPG3_R
53
J
P11_5 / SEG1
54
J
P11_6 / SEG2 / FRCK0_R
55
J
P11_7 / SEG3 / IN0_R
56
J
P11_0 / COM0
57
J
P11_1 / COM1 / PPG0_R
58
J
P11_2 / COM2 / PPG1_R
59
J
P11_3 / COM3 / PPG2_R
60
J
P12_0 / SEG4 / IN1_R
61
J
P12_1 / SEG5 / TIN1_R / PPG0_B
62
J
P12_2 / SEG6 / TOT1_R / PPG1_B
63
J
P12_3 / SEG7
64
J
P12_4 / SEG8
65
J
P12_5 / SEG9 / TIN2_R / PPG2_B
66
J
P12_6 / SEG10 / TOT2_R / PPG3_B
67
J
P12_7 / SEG11 / INT1_R
68
J
P00_0 / SEG12 / INT3_R
69
J
P01_1 / SEG21 / CKOT1
70
J
P01_2 / SEG22 / CKOTX1
71
J
P01_3 / SEG23
72
J
P01_4 / SEG24
73
L
P03_0 / SEG36 / V0
74
L
P03_1 / SEG37 / V1
75
L
P03_2 / SEG38 / V2
76
L
P03_3 / SEG39 / V3
77
M
P03_4 / RX0 / INT4
78
H
P03_5 / TX0
79
H
P03_6 / INT0 / NMI
80
Supply
Vcc
■ I/O CIRCUIT TYPE” for details on the I/O circuit types.
*: See “
12
CONFIDENTIAL
MB96680_DS704-00002-2v1-E, January 31, 2014
D a t a S h e e t
 I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
X1
R
0
1
FCI
X0
X out
High-speed oscillation circuit:
 Programmable between
oscillation mode (external
crystal or resonator connected
to X0/X1 pins) and Fast
external Clock Input (FCI)
mode (external clock
connected to X0 pin)
 Feedback resistor = approx.
1.0M
 The amplitude: 1.8V±0.15V
to operate by the internal
supply voltage
FCI or Osc disable
January 31, 2014, MB96680_DS704-00002-2v1-E
CONFIDENTIAL
13
D a t a S h e e t
Type
Circuit
Remarks
B
Pull-up control
P-ch
Standby
control
for input
shutdown
P-ch
Pout
N-ch
Nout
R
Low-speed oscillation circuit
shared with GPIO functionality:
 Feedback resistor = approx.
5.0M
 GPIO functionality selectable
(CMOS level output (IOL =
4mA, IOH = -4mA),
Automotive input with input
shutdown function and
programmable pull-up
resistor)
Automotive input
X1A
R
X out
0
1
FCI
X0A
FCI or Osc disable
Pull-up control
P-ch
Standby
control
for input
shutdown
C
14
CONFIDENTIAL
P-ch
Pout
N-ch
Nout
R
Automotive input
CMOS hysteresis input pin
MB96680_DS704-00002-2v1-E, January 31, 2014
D a t a S h e e t
Type
Circuit
Remarks
F
Power supply input protection
circuit
P-ch
N-ch
 A/D converter ref+ (AVRH)
power supply input pin with
protection circuit
 Without protection circuit
against VCC for pins AVRH
G
P-ch
N-ch
H
Pull-up control
P-ch
P-ch
Pout
N-ch
Nout
 CMOS level output
(IOL = 4mA, IOH = -4mA)
 Automotive input with input
shutdown function
 Programmable pull-up
resistor
R
Standby control
for input shutdown
Automotive input
J
Pull-up control
P-ch
P-ch
Pout
N-ch
Nout
 CMOS level output
(IOL = 4mA, IOH = -4mA)
 Automotive input with input
shutdown function
 Programmable pull-up
resistor
 SEG or COM output
R
Automotive input
Standby control
for input shutdown
SEG or COM output
January 31, 2014, MB96680_DS704-00002-2v1-E
CONFIDENTIAL
15
D a t a S h e e t
Type
Circuit
Remarks
K
Pull-up control
P-ch
P-ch
Pout
N-ch
Nout
 CMOS level output
(IOL = 4mA, IOH = -4mA)
 Automotive input with input
shutdown function
 Programmable pull-up
resistor
 Analog input
R
Automotive input
Standby control
for input shutdown
Analog input
L
Pull-up control
P-ch
P-ch
Pout
N-ch
Nout
 CMOS level output
(IOL = 4mA, IOH = -4mA)
 Automotive input with input
shutdown function
 Programmable pull-up
resistor
 Vn input or SEG output
R
Automotive input
Standby control
for input shutdown
Vn input or SEG output
M
Pull-up control
P-ch
R
P-ch
Pout
N-ch
Nout
 CMOS level output
(IOL = 4mA, IOH = -4mA)
 CMOS hysteresis input with
input shutdown function
 Programmable pull-up
resistor
Hysteresis input
Standby control
for input shutdown
16
CONFIDENTIAL
MB96680_DS704-00002-2v1-E, January 31, 2014
D a t a S h e e t
Type
Circuit
Remarks
N
Pull-up control
P-ch
P-ch
Pout
N-ch
Nout*
R
 CMOS level output
(IOL = 3mA, IOH = -3mA)
 CMOS hysteresis input with
input shutdown function
 Programmable pull-up
resistor
*: N-channel transistor has slew
rate control according to I2C
spec, irrespective of usage.
Hysteresis input
Standby control
for input shutdown
 Open-drain I/O
 Output 25mA, Vcc = 2.7V
 TTL input
O
N-ch
Nout
R
Standby control
for input shutdown
TTL input
P
Pull-up control
P-ch
P-ch
Pout
N-ch
Nout
 CMOS level output
(IOL = 4mA, IOH = -4mA)
 CMOS hysteresis inputs with
input shutdown function
 Programmable pull-up
resistor
 SEG or COM output
R
Hysteresis input
Standby control
for input shutdown
SEG or COM output
January 31, 2014, MB96680_DS704-00002-2v1-E
CONFIDENTIAL
17
D a t a S h e e t
Type
Circuit
Remarks
R
Pull-up control
P-ch
N-ch
P-ch
Pout
N-ch
Nout
 CMOS level output
(programmable IOL = 4mA,
IOH = -4mA and IOL = 30mA,
IOH = -30mA)
 Automotive input with input
shutdown function
 Programmable pull-up /
pull-down resistor
 Analog input
Pull-down control
R
Automotive input
Standby control
for input shutdown
Analog input
18
CONFIDENTIAL
MB96680_DS704-00002-2v1-E, January 31, 2014
D a t a S h e e t
 MEMORY MAP
FF:FFFFH
USER ROM*1
DE:0000H
DD:FFFFH
Reserved
10:0000H
0F:C000H
Boot-ROM
Peripheral
0E:9000H
Reserved
01:0000H
00:8000H
RAMSTART0*2
ROM/RAM
MIRROR
Internal RAM
bank0
Reserved
00:0C00H
00:0380H
Peripheral
00:0180H
GPR*3
00:0100H
DMA
00:00F0H
Reserved
00:0000H
Peripheral
*1: For details about USER ROM area, see “USER ROM MEMORY MAP FOR FLASH DEVICES”
on the following pages.
*2: For RAMSTART addresses, see the table on the next page.
*3: Unused GPR banks can be used as RAM area.
GPR: General-Purpose Register
The DMA area is only available if the device contains the corresponding resource.
The available RAM and ROM area depends on the device.
January 31, 2014, MB96680_DS704-00002-2v1-E
CONFIDENTIAL
19
D a t a S h e e t
 RAMSTART ADDRESSES
Devices
Bank 0
RAM size
RAMSTART0
MB96F683
MB96F685
4KB
00:7200H
20
CONFIDENTIAL
MB96680_DS704-00002-2v1-E, January 31, 2014
D a t a S h e e t
 USER ROM MEMORY MAP FOR FLASH DEVICES
MB96F683
CPU mode
address
Flash memory
mode address
FF:FFFFH
3F:FFFFH
FF:0000H
3F:0000H
FE:FFFFH
3E:FFFFH
FE:0000H
3E:0000H
MB96F685
Flash size
Flash size
64.5KB + 32KB
128.5KB + 32KB
SA39 - 64KB
SA39 - 64KB
SA38 - 64KB
Bank A of Flash A
FD:FFFFH
Reserved
Reserved
DF:A000H
DF:9FFFH
1F:9FFFH
DF:8000H
1F:8000H
DF:7FFFH
1F:7FFFH
DF:6000H
1F:6000H
DF:5FFFH
1F:5FFFH
DF:4000H
1F:4000H
DF:3FFFH
1F:3FFFH
DF:2000H
1F:2000H
DF:1FFFH
1F:1FFFH
DF:0000H
1F:0000H
DE:FFFFH
DE:0000H
SA4 - 8KB
SA4 - 8KB
SA3 - 8KB
SA3 - 8KB
SA2 - 8KB
SA2 - 8KB
SA1 - 8KB
SA1 - 8KB
SAS - 512B*
SAS - 512B*
Reserved
Reserved
Bank B of Flash A
Bank A of Flash A
*: Physical address area of SAS-512B is from DF:0000H to DF:01FFH.
Others (from DF:0200H to DF:1FFFH) is mirror area of SAS-512B.
Sector SAS contains the ROM configuration block RCBA at CPU address DF:0000 H -DF:01FFH.
2
SAS can not be used for E PROM emulation.
January 31, 2014, MB96680_DS704-00002-2v1-E
CONFIDENTIAL
21
D a t a S h e e t
 SERIAL PROGRAMMING COMMUNICATION INTERFACE
USART pins for Flash serial programming (MD = 0, DEBUG I/F = 0, Serial Communication mode)
MB96680
Pin Number
USART Number
37
38
USART0
SOT0
SCK0
3
SIN1
5
CONFIDENTIAL
SIN0
39
4
22
Normal Function
USART1
SOT1
SCK1
MB96680_DS704-00002-2v1-E, January 31, 2014
D a t a S h e e t
 INTERRUPT VECTOR TABLE
Vector
number
Offset in
vector table
Vector name
Cleared by
DMA
Index in
ICR to
program
Description
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
3FCH
3F8H
3F4H
3F0H
3ECH
3E8H
3E4H
3E0H
3DCH
3D8H
3D4H
3D0H
3CCH
3C8H
3C4H
3C0H
3BCH
3B8H
3B4H
3B0H
3ACH
3A8H
3A4H
3A0H
39CH
398H
394H
390H
38CH
388H
384H
380H
37CH
378H
374H
370H
36CH
368H
364H
360H
35CH
CALLV0
CALLV1
CALLV2
CALLV3
CALLV4
CALLV5
CALLV6
CALLV7
RESET
INT9
EXCEPTION
NMI
DLY
RC_TIMER
MC_TIMER
SC_TIMER
LVDI
EXTINT0
EXTINT1
EXTINT2
EXTINT3
EXTINT4
EXTINT6
EXTINT7
CAN0
PPG0
PPG1
PPG2
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
CALLV instruction
CALLV instruction
CALLV instruction
CALLV instruction
CALLV instruction
CALLV instruction
CALLV instruction
CALLV instruction
Reset vector
INT9 instruction
Undefined instruction execution
Non-Maskable Interrupt
Delayed Interrupt
RC Clock Timer
Main Clock Timer
Sub Clock Timer
Low Voltage Detector
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
Reserved
External Interrupt 6
External Interrupt 7
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CAN Controller 0
Reserved
Reserved
Reserved
Reserved
Programmable Pulse Generator 0
Programmable Pulse Generator 1
Programmable Pulse Generator 2
January 31, 2014, MB96680_DS704-00002-2v1-E
CONFIDENTIAL
23
D a t a S h e e t
Vector
number
Offset in
vector table
Vector name
Cleared by
DMA
Index in
ICR to
program
Description
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
358H
354H
350H
34CH
348H
344H
340H
33CH
338H
334H
330H
32CH
328H
324H
320H
31CH
318H
314H
310H
30CH
308H
304H
300H
2FCH
2F8H
2F4H
2F0H
2ECH
2E8H
2E4H
2E0H
2DCH
2D8H
2D4H
2D0H
2CCH
2C8H
2C4H
2C0H
2BCH
PPG3
RLT1
RLT2
RLT6
ICU0
ICU1
ICU4
ICU5
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Programmable Pulse Generator 3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reload Timer 1
Reload Timer 2
Reserved
Reserved
Reserved
Reload Timer 6
Input Capture Unit 0
Input Capture Unit 1
Reserved
Reserved
Input Capture Unit 4
Input Capture Unit 5
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
24
CONFIDENTIAL
MB96680_DS704-00002-2v1-E, January 31, 2014
D a t a S h e e t
Vector
number
Offset in
vector table
Vector name
Cleared by
DMA
Index in
ICR to
program
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
2B8H
2B4H
2B0H
2ACH
2A8H
2A4H
2A0H
29CH
298H
294H
290H
28CH
288H
284H
280H
27CH
278H
274H
270H
26CH
268H
264H
260H
25CH
258H
254H
250H
24CH
248H
244H
240H
23CH
238H
234H
230H
22CH
228H
224H
220H
21CH
FRT0
FRT1
RTC0
CAL0
SG0
IIC0
ADC0
LINR0
LINT0
LINR1
LINT1
-
Yes
Yes
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
-
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
January 31, 2014, MB96680_DS704-00002-2v1-E
CONFIDENTIAL
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Free-Running Timer 0
Free-Running Timer 1
Reserved
Reserved
Real Time Clock
Clock Calibration Unit
Sound Generator 0
I2C interface 0
Reserved
A/D Converter 0
Reserved
Reserved
LIN USART 0 RX
LIN USART 0 TX
LIN USART 1 RX
LIN USART 1 TX
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
25
D a t a S h e e t
Vector
number
Offset in
vector table
Vector name
Cleared by
DMA
Index in
ICR to
program
Description
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
218H
214H
210H
20CH
208H
204H
200H
1FCH
1F8H
1F4H
1F0H
1ECH
1E8H
1E4H
1E0H
1DCH
1D8H
1D4H
1D0H
1CCH
1C8H
1C4H
1C0H
FLASHA
ADCRC0
ADCPD0
-
Yes
No
No
-
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Flash memory A interrupt
Reserved
Reserved
Reserved
Reserved
Reserved
A/D Converter 0 - Range Comparator
A/D Converter 0 - Pulse detection
Reserved
Reserved
Reserved
26
CONFIDENTIAL
MB96680_DS704-00002-2v1-E, January 31, 2014
D a t a S h e e t
 HANDLING PRECAUTIONS
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly
affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This
page describes precautions that must be observed to minimize the chance of failure and to obtain higher
reliability from your Spansion semiconductor devices.
1. Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
 Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
 Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device's electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their sales
representative beforehand.
 Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power
supply and input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause
deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to
prevent such overvoltage or over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can
cause large current flows. Such conditions if present for extended periods of time can damage the
device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation.
Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.
 Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When
subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may
be formed, causing large current levels in excess of several hundred mA to flow continuously at the power
supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but
can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the
following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should
include attention to abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
Code: DS00-00004-3E
January 31, 2014, MB96680_DS704-00002-2v1-E
CONFIDENTIAL
27
D a t a S h e e t
 Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards
in the design of products.
 Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury,
damage or loss from such failures by incorporating safety design measures into your facility and equipment
such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions.
 Precautions Related to Usage of Devices
Spansion semiconductor devices are intended for use in standard applications (computers, office automation
and other office equipment, industrial, communications, and measurement equipment, personal or
household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or
abnormal operation may directly affect human lives or cause physical injury or property damage, or where
extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea
floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult
with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
2. Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat
resistance during soldering, you should only mount under Spansion's recommended conditions. For detailed
information about mount conditions, contact your sales representative.
 Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct
soldering on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the
board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the
soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for
storage temperature. Mounting processes should conform to Spansion recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can
lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment
of socket contacts and IC leads be verified before mounting.
 Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads
are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results
in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Spansion recommends the solder reflow method, and has
established a ranking of mounting conditions for each product. Users are advised to mount packages in
accordance with Spansion ranking of recommended conditions.
28
CONFIDENTIAL
MB96680_DS704-00002-2v1-E, January 31, 2014
D a t a S h e e t
 Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic
soldering, junction strength may be reduced under some conditions of use.
 Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions
will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed
moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent,
do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.
Store products in locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at
temperatures between 5°C and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, Spansion packages semiconductor devices in highly moisture-resistant aluminum
laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags
for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
 Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion
recommended conditions for baking.
Condition: 125°C/24 h
 Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take
the following precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus
for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high
resistance (on the level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to
minimize shock loads is recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board
assemblies.
January 31, 2014, MB96680_DS704-00002-2v1-E
CONFIDENTIAL
29
D a t a S h e e t
3. Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described
above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high
humidity levels are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal
operation. In such cases, use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will
adversely affect the device. If you use devices in such conditions, consider ways to prevent such
exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation.
Users should provide shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible
substances. If devices begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Spansion products in other special environmental conditions should
consult with sales representatives.
Please check the latest handling precautions at the following URL.
http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf
30
CONFIDENTIAL
MB96680_DS704-00002-2v1-E, January 31, 2014
D a t a S h e e t
 HANDLING DEVICES
Special care is required for the following when handling the device:
• Latch-up prevention
• Unused pins handling
• External clock usage
• Notes on PLL clock mode operation
• Power supply pins (Vcc/Vss)
• Crystal oscillator and ceramic resonator circuit
• Turn on sequence of power supply to A/D converter and analog inputs
• Pin handling when not using the A/D converter
• Notes on Power-on
• Stabilization of power supply voltage
• SMC power supply pins
• Serial communication
• Mode Pin (MD)
1. Latch-up prevention
CMOS IC chips may suffer latch-up under the following conditions:
- A voltage higher than VCC or lower than VSS is applied to an input or output pin.
- A voltage higher than the rated voltage is applied between Vcc pins and Vss pins.
- The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current dramatically, causing thermal damages to the device.
For the same reason, extra care is required to not let the analog power-supply voltage (AVCC, AVRH) exceed
the digital power-supply voltage.
2. Unused pins handling
Unused input pins can be left open when the input is disabled (corresponding bit of Port Input Enable register
PIER = 0).
Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent
damage of the device. To prevent latch-up, they must therefore be pulled up or pulled down through resistors
which should be more than 2kΩ.
Unused bidirectional pins can be set either to the output state and be then left open, or to the input state with
either input disabled or external pull-up/pull-down resistor as described above.
3. External clock usage
The permitted frequency range of an external clock depends on the oscillator type and configuration.
See AC Characteristics for detailed modes and frequency limits. Single and opposite phase external clocks must
be connected as follows:
(1) Single phase external clock for Main oscillator
When using a single phase external clock for the Main oscillator, X0 pin must be driven and X1 pin left open.
And supply 1.8V power to the external clock.
X0
X1
January 31, 2014, MB96680_DS704-00002-2v1-E
CONFIDENTIAL
31
D a t a S h e e t
(2) Single phase external clock for Sub oscillator
When using a single phase external clock for the Sub oscillator, “External clock mode” must be selected and
X0A/P04_0 pin must be driven. X1A/P04_1 pin can be configured as GPIO.
(3) Opposite phase external clock
When using an opposite phase external clock, X1 (X1A) pins must be supplied with a clock signal which has
the opposite phase to the X0 (X0A) pins. Supply level on X0 and X1 pins must be 1.8V.
X0
X1
4. Notes on PLL clock mode operation
If the microcontroller is operated with PLL clock mode and no external oscillator is operating or no external
clock is supplied, the microcontroller attempts to work with the free oscillating PLL. Performance of this
operation, however, cannot be guaranteed.
5. Power supply pins (Vcc/Vss)
It is required that all VCC-level as well as all VSS-level power supply pins are at the same potential. If there is
more than one VCC or VSS level, the device may operate incorrectly or be damaged even within the guaranteed
operating range.
Vcc and Vss pins must be connected to the device from the power supply with lowest possible impedance.
The smoothing capacitor at Vcc pin must use the one of a capacity value that is larger than Cs.
Besides this, as a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1F
between Vcc and Vss pins as close as possible to Vcc and Vss pins.
6. Crystal oscillator and ceramic resonator circuit
Noise at X0, X1 pins or X0A, X1A pins might cause abnormal operation. It is required to provide bypass
capacitors with shortest possible distance to X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic
resonator) and ground lines, and, to the utmost effort, that the lines of oscillation circuit do not cross the lines of
other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A
pins with a ground area for stabilizing the operation.
It is highly recommended to evaluate the quartz/MCU or resonator/MCU system at the quartz or resonator
manufacturer, especially when using low-Q resonators at higher frequencies.
7. Turn on sequence of power supply to A/D converter and analog inputs
It is required to turn the A/D converter power supply (AV CC, AVRH) and analog inputs (ANn) on after turning
the digital power supply (VCC) on.
It is also required to turn the digital power off after turning the A/D converter supply and analog inputs off. In
this case, AVRH must not exceed AVCC . Input voltage for ports shared with analog input ports also must not
exceed AVCC (turning the analog and digital power supplies simultaneously on or off is acceptable).
8. Pin handling when not using the A/D converter
If the A/D converter is not used, the power supply pins for A/D converter should be connected such as AV CC =
VCC , AVSS = AVRH = VSS.
32
CONFIDENTIAL
MB96680_DS704-00002-2v1-E, January 31, 2014
D a t a S h e e t
9. Notes on Power-on
To prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply
on should be slower than 50s from 0.2V to 2.7V.
10. Stabilization of power supply voltage
If the power supply voltage varies acutely even within the operation safety range of the VCC power supply
voltage, a malfunction may occur. The VCC power supply voltage must therefore be stabilized. As stabilization
guidelines, the power supply voltage must be stabilized in such a way that VCC ripple fluctuations (peak to peak
value) in the commercial frequencies (50Hz to 60Hz) fall within 10% of the standard VCC power supply voltage
and the transient fluctuation rate becomes 0.1V/s or less in instantaneous fluctuation for power supply
switching.
11. SMC power supply pins
All DVcc /DVss pins must be set to the same level as the Vcc /Vss pins.
Note that the SMC I/O pin state is undefined if DV CC is powered on and VCC is below 3V. To avoid this, VCC
must always be powered on before DVCC.
DVcc/DVss must be applied when using SMC I/O pin as GPIO.
12. Serial communication
There is a possibility to receive wrong data due to noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider receiving of wrong data when designing the system. For example apply a checksum and retransmit
the data if an error occurs.
13. Mode Pin (MD)
Connect the mode pin directly to Vcc or Vss pin. To prevent the device unintentionally entering test mode due to
noise, lay out the printed circuit board so as to minimize the distance from the mode pin to Vcc or Vss pin and
provide a low-impedance connection.
January 31, 2014, MB96680_DS704-00002-2v1-E
CONFIDENTIAL
33
D a t a S h e e t
 ELECTRICAL CHARACTERISTICS
1.
Absolute Maximum Ratings
Parameter
Power supply
voltage*1
Analog power
supply voltage*1
Analog reference
voltage*1
SMC Power
supply*1
LCD power supply
voltage*1
Input voltage*1
Output voltage*1
Maximum Clamp
Current
Total Maximum
Clamp Current
"L" level maximum
output current
Condition
VCC
-
VSS - 0.3
VSS + 6.0
V
AVCC
-
VSS - 0.3
VSS + 6.0
V
VCC = AVCC*2
AVRH
-
VSS - 0.3
VSS + 6.0
V
AVCC ≥ AVRH,
AVRH ≥ AVSS
DVCC
-
VSS - 0.3
VSS + 6.0
V
VCC = AVCC= DVCC*2
V0 to V3
-
VSS - 0.3
VSS + 6.0
V
VI
VO
-
VSS - 0.3
VSS - 0.3
VSS + 6.0
VSS + 6.0
V
V
ICLAMP
-
-4.0
+4.0
mA
Σ|ICLAMP|
-
-
21
mA
IOL
ΣIOL
TA= -40°C
TA= +25°C
TA= +85°C
TA= +105°C
TA= -40°C
TA= +25°C
TA= +85°C
TA= +105°C
-
-
15
52
39
32
30
4
40
30
25
23
46
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
ΣIOLSMC
-
-
180
mA
High current port
ΣIOLAV
-
-
23
mA
Normal port
ΣIOLAVSMC
IOH
-
90
-15
-52
-39
-32
-30
-4
-40
-30
-25
-23
-46
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
High current port
Normal port
ΣIOH
TA= -40°C
TA= +25°C
TA= +85°C
TA= +105°C
TA= -40°C
TA= +25°C
TA= +85°C
TA= +105°C
-
ΣIOHSMC
-
-
-180
mA
High current port
ΣIOHAV
-
-
-23
mA
Normal port
ΣIOHAVSMC
-
-
-90
mA
High current port
IOLSMC
IOLAV
"L" level average
output current
"L" level maximum
overall output
current
"L" level average
overall output
current
"H" level maximum
output current
IOLAVSMC
IOHSMC
IOHAV
"H" level average
output current
"H" level maximum
overall output
current
"H" level average
overall output
current
34
CONFIDENTIAL
Rating
Min
Max
Symbol
IOHAVSMC
Unit
Remarks
V0 to V3 must not
exceed VCC
VI ≤ (D)VCC + 0.3V*3
VO ≤ (D)VCC + 0.3V*3
Applicable to general
purpose I/O pins *4
Applicable to general
purpose I/O pins *4
Normal port
High current port
Normal port
High current port
Normal port
High current port
Normal port
High current port
Normal port
MB96680_DS704-00002-2v1-E, January 31, 2014
D a t a S h e e t
Parameter
Power
consumption*5
Symbol
Condition
PD
TA= +105°C
Min
-
Rating
Max
Unit
317*6
mW
Remarks
Operating ambient
TA
-40
+105
°C
temperature
Storage temperature
TSTG
-55
+150
°C
*1: This parameter is based on VSS = AVSS = DVSS = 0V.
*2: AVCC and VCC and DVCC must be set to the same voltage. It is required that AVCC does not exceed VCC,
DVCC and that the voltage at the analog inputs does not exceed AVCC when the power is switched on.
*3: VI and VO should not exceed VCC + 0.3V. VI should also not exceed the specified ratings. However if the
maximum current to/from an input is limited by some means with external components, the ICLAMP rating
supersedes the VI rating. Input/Output voltages of high current ports depend on DVCC. Input/Output voltages
of standard ports depend on VCC.
*4: • Applicable to all general purpose I/O pins (Pnn_m).
• Use within recommended operating conditions.
• Use at DC voltage (current).
• The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the V CC pin, and this may
affect other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0V), the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the Power reset.
• The DEBUG I/F pin has only a protective diode against VSS. Hence it is only permitted to input a negative
clamping current (4mA). For protection against positive input voltages, use an external clamping diode
which limits the input voltage to maximum 6.0V.
January 31, 2014, MB96680_DS704-00002-2v1-E
CONFIDENTIAL
35
D a t a S h e e t
• Sample recommended circuits:
Protective diode
VCC
Limiting
resistance
P-ch
+B input (0V to 16V)
N-ch
R
*5: The maximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the
thermal conductance of the package on the PCB.
The actual power dissipation depends on the customer application and can be calculated as follows:
PD = PIO + PINT
PIO = Σ (VOL  IOL + VOH  IOH) (I/O load power dissipation, sum is performed on all I/O ports)
PINT = VCC  (ICC + IA) (internal power dissipation)
ICC is the total core current consumption into VCC as described in the “DC characteristics” and depends on the
selected operation mode and clock frequency and the usage of functions like Flash programming.
IA is the analog current consumption into AVCC.
*6: Worst case value for a package mounted on single layer PCB at specified T A without air flow.
<WARNING>
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
36
CONFIDENTIAL
MB96680_DS704-00002-2v1-E, January 31, 2014
D a t a S h e e t
2.
Recommended Operating Conditions
(VSS = AVSS = DVSS = 0V)
Parameter
Power supply
voltage
Smoothing
capacitor at C pin
Symbol
VCC,
AVCC,
DVCC
CS
Min
Value
Typ
Max
2.7
-
5.5
V
2.0
-
5.5
V
Maintains RAM data in stop mode
F
1.0F (Allowance within ± 50%)
3.9µF (Allowance within ± 20%)
Please use the ceramic capacitor or the
capacitor of the frequency response of
this level.
The smoothing capacitor at VCC must
use the one of a capacity value that is
larger than CS.
0.5
1.0 to 3.9
4.7
Unit
Remarks
<WARNING>
The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure. No warranty is made
with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their representatives beforehand.
January 31, 2014, MB96680_DS704-00002-2v1-E
CONFIDENTIAL
37
D a t a S h e e t
3.
DC Characteristics
(1) Current Rating
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin
name
Conditions
PLL Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 32MHz
ICCPLL
Main Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 4MHz
ICCMAIN
Remarks
-
25
-
mA
TA = +25°C
-
-
34
mA
TA = +105°C
-
3.5
-
mA
TA = +25°C
-
-
7.5
mA
TA = +105°C
-
1.7
-
mA
TA = +25°C
-
-
5.5
mA
TA = +105°C
-
0.15
-
mA
TA = +25°C
-
-
3.2
mA
TA = +105°C
-
0.1
-
mA
TA = +25°C
-
-
3
mA
TA = +105°C
Flash 0 wait
(CLKPLL, CLKSC and
CLKRC stopped)
RC Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = CLKRC =
2MHz
ICCRCH
Unit
Flash 0 wait
(CLKRC and CLKSC
stopped)
Power supply
current in Run
modes*1
Min
Value
Typ Max
Vcc
Flash 0 wait
(CLKMC, CLKPLL and
CLKSC stopped)
RC Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = CLKRC =
100kHz
ICCRCL
Flash 0 wait
(CLKMC, CLKPLL and
CLKSC stopped)
Sub Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 32kHz
ICCSUB
Flash 0 wait
(CLKMC, CLKPLL and
CLKRC stopped)
38
CONFIDENTIAL
MB96680_DS704-00002-2v1-E, January 31, 2014
D a t a S h e e t
Parameter
Symbol
Pin
name
PLL Sleep mode with
CLKS1/2 = CLKP1/2 =
32MHz
(CLKRC and CLKSC
stopped)
ICCSPLL
ICCSMAIN
Power supply
current in
Sleep modes*1
ICCSRCH
Vcc
ICCSRCL
ICCSSUB
January 31, 2014, MB96680_DS704-00002-2v1-E
CONFIDENTIAL
Conditions
Main Sleep mode with
CLKS1/2 = CLKP1/2 =
4MHz,
SMCR:LPMSS = 0
(CLKPLL, CLKRC
and CLKSC stopped)
RC Sleep mode with
CLKS1/2 = CLKP1/2 =
CLKRC = 2MHz,
SMCR:LPMSS = 0
(CLKMC, CLKPLL
and CLKSC stopped)
RC Sleep mode with
CLKS1/2 = CLKP1/2 =
CLKRC = 100kHz
(CLKMC, CLKPLL
and CLKSC stopped)
Sub Sleep mode with
CLKS1/2 = CLKP1/2 =
32kHz,
(CLKMC, CLKPLL
and CLKRC stopped)
Min
Value
Typ Max
Unit
Remarks
-
6.5
-
mA
TA = +25°C
-
-
13
mA
TA = +105°C
-
0.9
-
mA
TA = +25°C
-
-
4
mA
TA = +105°C
-
0.5
-
mA
TA = +25°C
-
-
3.5
mA
TA = +105°C
-
0.06
-
mA
TA = +25°C
-
-
2.7
mA
TA = +105°C
-
0.04
-
mA
TA = +25°C
-
-
2.5
mA
TA = +105°C
39
D a t a S h e e t
Parameter Symbol
Pin
name
ICCTMAIN
ICCTRCH
ICCTRCL
ICCTSUB
40
CONFIDENTIAL
Vcc
Min
Value
Typ Max
Unit
Remarks
-
1800
2245
A
TA = +25°C
-
-
3140
A
TA = +105°C
-
285
325
A
TA = +25°C
-
-
1055
A
TA = +105°C
-
160
210
A
TA = +25°C
-
-
970
A
TA = +105°C
RC Timer mode with
CLKRC = 100kHz
(CLKPLL, CLKMC and
CLKSC stopped)
-
30
70
A
TA = +25°C
-
-
820
A
TA = +105°C
Sub Timer mode with
CLKSC = 32kHz
(CLKMC, CLKPLL and
CLKRC stopped)
-
25
55
A
TA = +25°C
-
-
800
A
TA = +105°C
PLL Timer mode with
CLKPLL = 32MHz (CLKRC
and CLKSC stopped)
ICCTPLL
Power
supply
current in
Timer
modes*2
Conditions
Main Timer mode with
CLKMC = 4MHz,
SMCR:LPMSS = 0
(CLKPLL, CLKRC and
CLKSC stopped)
RC Timer mode with
CLKRC = 2MHz,
SMCR:LPMSS = 0
(CLKPLL, CLKMC and
CLKSC stopped)
MB96680_DS704-00002-2v1-E, January 31, 2014
D a t a S h e e t
Parameter
Symbol
Power supply
current in Stop
mode*3
ICCH
Flash Power
Down current
ICCFLASHPD
Power supply
current
for active Low
Voltage
detector*4
Flash Write/
Erase current*5
ICCLVD
ICCFLASH
Pin
name
Vcc
Conditions
Value
Typ Max
Unit
Remarks
-
20
55
A
TA = +25°C
-
-
800
A
TA = +105°C
-
36
70
A
-
5
-
A TA = +25°C
-
-
12.5
A TA = +105°C
-
12.5
-
mA TA = +25°C
-
-
20
mA TA = +105°C
-
Vcc
-
Vcc
Low voltage
detector enabled
Vcc
Min
-
*1: The power supply current is measured with a 4MHz external clock connected to the Main oscillator and
a 32kHz external clock connected to the Sub oscillator. See chapter “Standby mode and voltage regulator
control circuit” of the Hardware Manual for further details about voltage regulator control. Current for "On
Chip Debugger" part is not included. Power supply current in Run mode does not include Flash Write / Erase
current.
*2: The power supply current in Timer mode is the value when Flash is in Power-down / reset mode.
When Flash is not in Power-down / reset mode, ICCFLASHPD must be added to the Power supply current.
The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a
32kHz external clock connected to the Sub oscillator. The current for "On Chip Debugger" part is not
included.
*3: The power supply current in Stop mode is the value when Flash is in Power-down / reset mode.
When Flash is not in Power-down / reset mode, ICCFLASHPD must be added to the Power supply current.
*4: When low voltage detector is enabled, ICCLVD must be added to Power supply current.
*5: When Flash Write / Erase program is executed, ICCFLASH must be added to Power supply current.
January 31, 2014, MB96680_DS704-00002-2v1-E
CONFIDENTIAL
41
D a t a S h e e t
(2) Pin Characteristics
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter Symbol
VIH
"H" level
input
voltage
"L" level
input
voltage
42
CONFIDENTIAL
Pin
name
Port inputs
Pnn_m
Conditions
External clock in
"Fast Clock Input mode"
External clock in
"Oscillation mode"
VIHX0S
X0
VIHX0AS
X0A
VIHR
RSTX
-
VIHM
MD
-
VIHD
DEBUG
I/F
-
VIL
Port
inputs
Pnn_m
External clock in "Fast
Clock Input mode"
External clock in
"Oscillation mode"
VILX0S
X0
VILX0AS
X0A
VILR
RSTX
-
VILM
MD
-
VILD
DEBUG
I/F
-
Value
Unit
Min Typ Max
VCC
 0.7
VCC
 0.8
VD
 0.8
VCC
 0.8
VCC
 0.8
VCC
- 0.3
2.0
VSS
- 0.3
VSS
- 0.3
VSS
VSS
- 0.3
VSS
- 0.3
VSS
- 0.3
VSS
- 0.3
-
VCC
+ 0.3
VCC
+ 0.3
VD
VCC
+ 0.3
VCC
+ 0.3
VCC
+ 0.3
VCC
+ 0.3
VCC
 0.3
VCC
 0.5
VD
 0.2
VCC
 0.2
VCC
 0.2
VSS
+ 0.3
0.8
V
V
V
Remarks
CMOS Hysteresis
input
AUTOMOTIVE
Hysteresis input
VD=1.8V±0.15V
V
V
V
V
V
V
V
CMOS Hysteresis
input
CMOS Hysteresis
input
TTL Input
CMOS Hysteresis
input
AUTOMOTIVE
Hysteresis input
VD=1.8V±0.15V
V
V
V
V
CMOS Hysteresis
input
CMOS Hysteresis
input
TTL Input
MB96680_DS704-00002-2v1-E, January 31, 2014
D a t a S h e e t
Parameter Symbol
VOH4
"H" level
output
voltage
"L" level
output
voltage
VOH30
Pin
name
4mA
type
High
Drive
type*
VOH3
3mA
type
VOL4
4mA
type
VOL30
VOL3
VOLD
High
Drive
type*
3mA
type
DEBUG
I/F
Conditions
4.5V ≤ (D)VCC ≤ 5.5V
IOH = -4mA
2.7V ≤ (D)VCC < 4.5V
IOH = -1.5mA
4.5V ≤ DVCC ≤ 5.5V
IOH = -52mA
2.7V ≤ DVCC < 4.5V
IOH = -18mA
4.5V ≤ DVCC ≤ 5.5V
IOH = -39mA
2.7V ≤ DVCC < 4.5V
IOH = -16mA
4.5V ≤ DVCC ≤ 5.5V
IOH = -32mA
2.7V ≤ DVCC < 4.5V
IOH = -14.5mA
4.5V ≤ DVCC ≤ 5.5V
IOH = -30mA
2.7V ≤ DVCC < 4.5V
IOH = -14mA
4.5V ≤ VCC ≤ 5.5V
IOH = -3mA
2.7V ≤ VCC < 4.5V
IOH = -1.5mA
4.5V ≤ (D)VCC ≤ 5.5V
IOL = +4mA
2.7V ≤ (D)VCC < 4.5V
IOL = +1.7mA
4.5V ≤ DVCC ≤ 5.5V
IOL = +52mA
2.7V ≤ DVCC < 4.5V
IOL = +22mA
4.5V ≤ DVCC ≤ 5.5V
IOL = +39mA
2.7V ≤ DVCC < 4.5V
IOL = +18mA
4.5V ≤ DVCC ≤ 5.5V
IOL = +32mA
2.7V ≤ DVCC < 4.5V
IOL = +14mA
4.5V ≤ DVCC ≤ 5.5V
IOL = +30mA
2.7V ≤ DVCC < 4.5V
IOL = +13.5mA
2.7V ≤ VCC < 5.5V
IOL = +3mA
VCC = 2.7V
IOL = +25mA
January 31, 2014, MB96680_DS704-00002-2v1-E
CONFIDENTIAL
Min
(D)VCC
- 0.5
Value
Typ Max
-
(D)VCC
Unit
Remarks
V
TA = -40°C
TA = +25°C
DVCC
- 0.5
-
DVCC
V
TA = +85°C
TA = +105°C
VCC
- 0.5
-
VCC
V
-
-
0.4
V
TA = -40°C
TA = +25°C
-
-
0.5
V
TA = +85°C
TA = +105°C
-
-
0.4
V
0
-
0.25
V
43
D a t a S h e e t
Parameter Symbol Pin name
Input leak
current
Total LCD
leak
current
Internal
LCD
divide
resistance
Pull-up
resistance
value
Pull-down
resistance
value
Input
capacitance
Conditions
Min
Value
Unit
Typ Max
Pnn_m
VSS < VI < VCC
AVSS < VI <
AVCC, AVRH
-1
-
+1
Single port pin
except high
A
current output
I/O for SMC
P08_m
DVSS < VI < DVCC
AVSS < VI <
AVCC, AVRH
-3
-
+3
A
IIL
Σ|IILCD|
All SEG/
COM pin
VCC = 5.0V
-
0.5
10
A
RLCD
Between
V3 and V2,
V2 and V1,
V1 and V0
VCC = 5.0V
6.25
12.5
25
k
RPU
Pnn_m
VCC = 5.0V ±10%
25
50
100
k
RDOWN
P08_m
VCC = 5.0V ±10%
25
50
100
k
Other than
C,
Vcc,
Vss,
DVcc
DVss,
AVcc,
AVss,
AVRH,
P08_m
-
-
5
15
pF
P08_m
-
-
15
30
pF
CIN
Remarks
Maximum
leakage
current of all
LCD pins
*: In the case of driving stepping motor directly or high current outputs, set "1" to the bit in the Port High Drive
Register (PHDRnn:HDx="1").
44
CONFIDENTIAL
MB96680_DS704-00002-2v1-E, January 31, 2014
D a t a S h e e t
4.
AC Characteristics
(1) Main Clock Input Characteristics
(VCC = AVCC = DVCC = 2.7V to 5.5V, VD=1.8V±0.15V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Input frequency
Input frequency
Symbol
Pin
name
fC
fFCI
X0,
X1
Min
Value
Typ
Max
4
-
8
MHz
-
-
8
MHz
4
-
8
MHz
-
-
8
MHz
4
-
8
MHz
Unit
X0
Input clock cycle
tCYLH
-
125
-
-
ns
Input clock pulse
width
PWH,
PWL
-
55
-
-
ns
January 31, 2014, MB96680_DS704-00002-2v1-E
CONFIDENTIAL
Remarks
When using a crystal
oscillator, PLL off
When using an opposite
phase external
clock, PLL off
When using a crystal
oscillator or opposite
phase external clock,
PLL on
When using a single
phase external
clock in “Fast Clock
Input mode”, PLL off
When using a single
phase external
clock in “Fast Clock
Input mode”, PLL on
45
D a t a S h e e t
(2) Sub Clock Input Characteristics
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Min
Value
Typ
Max
-
-
32.768
-
kHz
-
-
-
100
kHz
X0A
-
-
-
50
kHz
Pin
Conditions
name
X0A,
X1A
Input frequency
fCL
Unit
Input clock cycle
tCYLL
-
-
10
-
-
s
Input clock pulse
width
-
-
PWH/tCYLL,
PWL/tCYLL
30
-
70
%
46
CONFIDENTIAL
Remarks
When using an
oscillation circuit
When using an
opposite phase
external clock
When using a
single phase
external clock
MB96680_DS704-00002-2v1-E, January 31, 2014
D a t a S h e e t
(3) Built-in RC Oscillation Characteristics
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Clock frequency
Symbol
Min
Value
Typ
Max
50
100
200
kHz
1
2
4
MHz
80
160
320
s
64
128
256
s
Unit
fRC
RC clock stabilization
time
tRCSTAB
Remarks
When using slow frequency of
RC oscillator
When using fast frequency of
RC oscillator
When using slow frequency of
RC oscillator
(16 RC clock cycles)
When using fast frequency of
RC oscillator
(256 RC clock cycles)
(4) Internal Clock Timing
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Value
Min
Max
Unit
Internal System clock frequency
(CLKS1 and CLKS2)
fCLKS1, fCLKS2
-
54
MHz
Internal CPU clock frequency (CLKB),
Internal peripheral clock frequency (CLKP1)
fCLKB, fCLKP1
-
32
MHz
Internal peripheral clock frequency (CLKP2)
fCLKP2
-
32
MHz
January 31, 2014, MB96680_DS704-00002-2v1-E
CONFIDENTIAL
47
D a t a S h e e t
(5) Operating Conditions of PLL
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Value
Min Typ Max
Unit
PLL oscillation stabilization wait time
tLOCK
1
-
4
ms
PLL input clock frequency
fPLLI
4
-
8
MHz
PLL oscillation clock frequency
fCLKVCO
56
-
108
MHz
PLL phase jitter
tPSKEW
-5
-
+5
ns
Remarks
For CLKMC = 4MHz
Permitted VCO output
frequency of PLL
(CLKVCO)
For CLKMC (PLL input
clock) ≥ 4MHz
(6) Reset Input
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin name
tRSTL
RSTX
Value
Reset input time
Rejection of reset input time
Unit
Min
Max
10
-
s
1
-
s
tRSTL
RSTX
0.2VCC
48
CONFIDENTIAL
0.2VCC
MB96680_DS704-00002-2v1-E, January 31, 2014
D a t a S h e e t
(7) Power-on Reset Timing
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Power on rise time
Power off time
Symbol
Pin name
tR
tOFF
Vcc
Vcc
January 31, 2014, MB96680_DS704-00002-2v1-E
CONFIDENTIAL
Min
Value
Typ
Max
0.05
1
-
30
-
Unit
ms
ms
49
D a t a S h e e t
(8) USART Timing
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C, CL=50pF)
Parameter
Symbol
4.5V  VCC 5.5V
Pin
Conditions
Min
Max
name
Serial clock cycle time
tSCYC
SCKn
SCKn,
SOTn
SCKn,
Internal shift
SOTn
clock mode
SCKn,
SINn
SCKn,
SINn
SCK   SOT delay time
tSLOVI
SOT  SCK  delay time
tOVSHI
SIN  SCK  setup time
tIVSHI
SCK   SIN hold time
tSHIXI
Serial clock "L" pulse width
tSLSH
SCKn
Serial clock "H" pulse width
tSHSL
SCKn
2.7V  VCC  4.5V
Min
Max
Unit
4tCLKP1
-
4tCLKP1
-
ns
- 20
+ 20
- 30
+ 30
ns
-
ns
-
ns
-
ns
-
ns
-
ns
NtCLKP1
– 20*
tCLKP1
+ 45
0
-
tCLKP1
+ 10
tCLKP1
+ 10
-
NtCLKP1
– 30*
tCLKP1
+ 55
0
tCLKP1
+ 10
tCLKP1
+ 10
SCKn,
2tCLKP1
2tCLKP1
ns
SOTn External shift
+ 45
+ 55
SCKn, clock mode
tCLKP1/2
tCLKP1/2
SIN  SCK  setup time
tIVSHE
ns
SINn
+ 10
+ 10
SCKn,
tCLKP1
tCLKP1
tSHIXE
ns
SCK   SIN hold time
SINn
+ 10
+ 10
SCK fall time
tF
SCKn
ns
20
20
SCK rise time
tR
SCKn
ns
20
20
Notes:  AC characteristic in CLK synchronized mode.
 CL is the load capacity value of pins when testing.
 Depending on the used machine clock frequency, the maximum possible baud rate can be limited by
some parameters. These parameters are shown in “MB96600 series HARDWARE MANUAL”.
 tCLKP1 indicates the peripheral clock 1 (CLKP1), Unit: ns
 These characteristics only guarantee the same relocate port number.
 For example, the combination of SCKn and SOTn_R is not guaranteed.
SCK   SOT delay time
tSLOVE
*: Parameter N depends on tSCYC and can be calculated as follows:
 If tSCYC = 2  k  tCLKP1, then N = k, where k is an integer > 2
 If tSCYC = (2  k + 1)  tCLKP1, then N = k + 1, where k is an integer > 1
Examples:
50
CONFIDENTIAL
tSCYC
N
4  tCLKP1
2
5  tCLKP1, 6  tCLKP1
3
7  tCLKP1, 8  tCLKP1
4
...
...
MB96680_DS704-00002-2v1-E, January 31, 2014
D a t a S h e e t
tSCYC
VOH
SCK
VOL
VOL
tOVSHI
tSLOVI
VOH
SOT
VOL
tIVSHI
SIN
tSHIXI
VIH
VIH
VIL
VIL
Internal shift clock mode
SCK
tSHSL
tSLSH
VIH
VIH
VIL
tF
SOT
VIL
VIH
tR
tSLOVE
VOH
VOL
SIN
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
External shift clock mode
January 31, 2014, MB96680_DS704-00002-2v1-E
CONFIDENTIAL
51
D a t a S h e e t
(9) External Input Timing
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Value
Min
Max
Pin name
Unit
Pnn_m
ADTG
Input pulse width
TINn, TINn_R
TTGn
FRCKn,
FRCKn_R
INn, INn_R
INTn, INTn_R
tINH,
tINL
2tCLKP1 +200
(tCLKP1=
1/fCLKP1)*
-
ns
Remarks
General Purpose I/O
A/D Converter trigger
input
Reload Timer
PPG trigger input
Free-Running Timer
input clock
Input Capture
External Interrupt
200
ns
Non-Maskable
NMI
Interrupt
*: tCLKP1 indicates the peripheral clock1 (CLKP1) cycle time except stop when in stop mode.
tINH
External input timing
VIH
tINL
VIH
VIL
52
CONFIDENTIAL
VIL
MB96680_DS704-00002-2v1-E, January 31, 2014
D a t a S h e e t
2
(10) I C Timing
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Conditions
High-speed
mode*4
Min
Max
Typical mode
Min
Max
Unit
SCL clock frequency
fSCL
0
100
0
400
kHz
(Repeated) START condition
hold time
tHDSTA
4.0
0.6
s
SDA   SCL 
SCL clock "L" width
tLOW
4.7
1.3
s
SCL clock "H" width
tHIGH
4.0
0.6
s
(Repeated) START condition
setup time
tSUSTA
4.7
0.6
s
CL = 50pF,
SCL   SDA 
R = (Vp/IOL)*1
Data hold time
tHDDAT
0
3.45*2
0
0.9*3
s
SCL   SDA  
Data setup time
tSUDAT
250
100
ns
SDA    SCL 
STOP condition setup time
tSUSTO
4.0
0.6
s
SCL   SDA 
Bus free time between
"STOP condition" and
tBUS
4.7
1.3
s
"START condition"
Pulse width of spikes which
(1-1.5)
(1-1.5)
will be suppressed by input
tSP
0
0
ns
tCLKP1*5
tCLKP1*5
noise filter
*1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively.
Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT only has to be met if the device does not extend the "L" width (t LOW) of the SCL signal.
*3: A high-speed mode I2C bus device can be used on a standard mode I2C bus system as long as the device
satisfies the requirement of "tSUDAT ≥ 250ns".
*4: For use at over 100kHz, set the peripheral clock1 (CLKP1) to at least 6MHz.
*5: tCLKP1 indicates the peripheral clock1 (CLKP1) cycle time.
SDA
tSUDAT
tSUSTA
tBUS
tLOW
SCL
tHDSTA
tHDDAT
January 31, 2014, MB96680_DS704-00002-2v1-E
CONFIDENTIAL
tHIGH
tHDSTA
tSP
tSUSTO
53
D a t a S h e e t
5.
A/D Converter
(1) Electrical Characteristics for the A/D Converter
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Min
Value
Typ
Max
-
-
-
10
bit
-
-
- 3.0
-
+ 3.0
LSB
Nonlinearity error
-
-
- 2.5
-
+ 2.5
LSB
Differential
Nonlinearity error
-
-
- 1.9
-
+ 1.9
LSB
Zero transition
voltage
VOT
ANn
Typ - 20
AVSS
+ 0.5LSB
Typ + 20
mV
Full scale transition
voltage
VFST
ANn
Typ - 20
Typ + 20
mV
Compare time*
-
-
Sampling time*
-
-
5.0
8.0
3.1
s
s
s
s
mA
Symbol
Pin
name
Resolution
-
Total error
Parameter
Power supply
current
Reference power
supply current
(between AVRH
and AVSS )
Analog input
capacity
Analog impedance
54
CONFIDENTIAL
1.0
2.2
0.5
1.2
-
-
3.3
A
-
520
810
A
A/D Converter active
-
-
1.0
A
AN8 to 13
- 1.0
-
15.5
17.4
1450
2700
+ 1.0
pF
pF


A
A/D Converter not
operated
Normal outputs
High current outputs
4.5V ≤ AVCC ≤ 5.5V
2.7V ≤ AVCC < 4.5V
AN16 to 23
- 3.0
-
+ 3.0
ANn
AVSS
-
AVRH
V
AVRH
AVCC
- 0.1
-
AVCC
V
ANn
-
-
4.0
LSB
AVCC
IR
AVRH
IRH
CVIN
AN8 to 13
AN16 to 23
RVIN
ANn
Analog port input
current (during
IAIN
conversion)
Analog input
VAIN
voltage
Reference voltage
range
Variation between
channels
*: Time for each channel.
Remarks
AVRH
- 1.5LSB
2.0
IA
IAH
Unit
4.5V ≤ ΑVCC ≤ 5.5V
2.7V ≤ ΑVCC  4.5V
4.5V ≤ ΑVCC ≤ 5.5V
2.7V ≤ ΑVCC  4.5V
A/D Converter active
A/D Converter not
operated
AVSS VAIN 
A AVCC, AVRH
MB96680_DS704-00002-2v1-E, January 31, 2014
D a t a S h e e t
(2) Accuracy and Setting of the A/D Converter Sampling Time
If the external impedance is too high or the sampling time too short, the analog voltage charged to the
internal sample and hold capacitor is insufficient, adversely affecting the A/D conversion precision.
To satisfy the A/D conversion precision, a sufficient sampling time must be selected. The required sampling
time (Tsamp) depends on the external driving impedance R ext, the board capacitance of the A/D converter
input pin Cext and the AVCC voltage level. The following replacement model can be used for the calculation:
MCU
Rext
Analog
input
RVIN
Source
Comparator
Cext
CVIN
Sampling switch
(During sampling:ON)
Rext: External driving impedance
Cext: Capacitance of PCB at A/D converter input
CVIN: Analog input capacity (I/O, analog switch and ADC are contained)
RVIN: Analog input impedance (I/O, analog switch and ADC are contained)
The following approximation formula for the replacement model above can be used:
Tsamp = 7.62  (Rext  Cext + (Rext + RVIN)  CVIN)
 Do not select a sampling time below the absolute minimum permitted value.
(0.5s for 4.5V ≤ AVCC ≤ 5.5V, 1.2s for 2.7V ≤ AVCC < 4.5V)
 If the sampling time cannot be sufficient, connect a capacitor of about 0.1F to the analog input pin.
 A big external driving impedance also adversely affects the A/D conversion precision due to the pin
input leakage current IIL (static current before the sampling switch) or the analog input leakage
current IAIN (total leakage current of pin input and comparator during sampling). The effect of the
pin input leakage current IIL cannot be compensated by an external capacitor.
 The accuracy gets worse as |AVRH - AVSS| becomes smaller.
January 31, 2014, MB96680_DS704-00002-2v1-E
CONFIDENTIAL
55
D a t a S h e e t
(3) Definition of A/D Converter Terms
 Resolution
 Nonlinearity error
: Analog variation that is recognized by an A/D converter.
: Deviation of the actual conversion characteristics from a straight line that connects
the zero transition point (0b0000000000 ←→ 0b0000000001) to the full-scale
transition point (0b1111111110 ←→ 0b1111111111).
 Differential nonlinearity error : Deviation from the ideal value of the input voltage that is required to
change the output code by 1LSB.
Total error
: Difference between the actual value and the theoretical value. The total error
includes zero transition error, full-scale transition error and nonlinearity error.
 Zero transition voltage: Input voltage which results in the minimum conversion value.
 Full scale transition voltage: Input voltage which results in the maximum conversion value.
Nonlinearity error of digital output N =
VNT - {1LSB  (N - 1) + VOT}
1LSB
Differential nonlinearity error of digital output N =
1LSB =
N
VOT
VFST
VNT
56
CONFIDENTIAL
:
:
:
:
V(N + 1) T - VNT
1LSB
[LSB]
- 1 [LSB]
VFST - VOT
1022
A/D converter digital output value.
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0x3FE to 0x3FF.
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
MB96680_DS704-00002-2v1-E, January 31, 2014
D a t a S h e e t
1LSB (Ideal value) =
Total error of digital output N =
AVRH - AVSS
1024
[V]
VNT - {1LSB  (N - 1) + 0.5LSB}
1LSB
N
: A/D converter digital output value.
VNT : Voltage at which the digital output changes from 0x(N + 1) to 0xN.
VOT (Ideal value) = AVSS + 0.5LSB[V]
VFST (Ideal value) = AVRH - 1.5LSB[V]
January 31, 2014, MB96680_DS704-00002-2v1-E
CONFIDENTIAL
57
D a t a S h e e t
6.
High Current Output Slew Rate
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Output rise/fall
time
Symbol
tR30,
tF30
Pin
Conditions
name
P08_m
Outputs
driving
strength set to
"30mA"
Min
Value
Typ
Max
15
-
75
Voltage
Unit
ns
Remarks
CL=85pF
VH=VOL30+0.9 × (V OH30-VOL30)
VL=VOL30+0.1 × (V OH30-VOL30)
VH
VH
VL
VL
tR30
tF30
Time
58
CONFIDENTIAL
MB96680_DS704-00002-2v1-E, January 31, 2014
D a t a S h e e t
7.
Low Voltage Detection Function Characteristics
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Min
Value
Typ
Max
CILCR:LVL = 0000B
CILCR:LVL = 0001B
CILCR:LVL = 0010B
CILCR:LVL = 0011B
CILCR:LVL = 0100B
CILCR:LVL = 0111B
CILCR:LVL = 1001B
2.70
2.79
2.98
3.26
3.45
3.73
3.91
2.90
3.00
3.20
3.50
3.70
4.00
4.20
3.10
3.21
3.42
3.74
3.95
4.27
4.49
V
V
V
V
V
V
V
dV/dt
-
- 0.004
-
+ 0.004
V/s
Hysteresis width
VHYS
CILCR:LVHYS=0
CILCR:LVHYS=1
80
100
50
120
mV
mV
Stabilization time
TLVDSTAB
-
-
-
75
s
Parameter
Symbol
Conditions
Detected voltage*1
VDL0
VDL1
VDL2
VDL3
VDL4
VDL5
VDL6
Power supply voltage
change rate*2
Unit
Detection delay time
td
30
s
*1: If the power supply voltage fluctuates within the time less than the detection delay time (t d), there is a
possibility that the low voltage detection will occur or stop after the power supply voltage passes the
detection range.
*2: In order to perform the low voltage detection at the detection voltage (V DLX), be sure to suppress fluctuation
of the power supply voltage within the limits of the change ration of power supply voltage.
January 31, 2014, MB96680_DS704-00002-2v1-E
CONFIDENTIAL
59
D a t a S h e e t
Voltage
Vcc
dV
Detected Voltage
dt
VDLX max
VDLX min
Time
RCR:LVDE
···Low voltage detection
function enable
60
CONFIDENTIAL
Low voltage detection
function disable
Stabilization time
TLVDSTAB
Low voltage detection
function enable···
MB96680_DS704-00002-2v1-E, January 31, 2014
D a t a S h e e t
8.
Flash Memory Write/Erase Characteristics
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Conditions
Unit
Remarks
Includes write time
prior to internal erase.
-
-
1.6
0.4
0.31
7.5
2.1
1.65
s
s
s
Word (16-bit) write time
-
-
25
400
s
Chip erase time
-
-
5.11
25.05
s
Sector erase time
Large Sector
Small Sector
Security Sector
Value
Min Typ Max
Not including
system-level overhead
time.
Includes write time
prior to internal erase.
Note: While the Flash memory is written or erased, shutdown of the external power (VCC) is prohibited. In the
application system where the external power (VCC) might be shut down while writing or erasing, be sure
to turn the power off by using a low voltage detection function.
To put it concrete, change the external power in the range of change ration of power supply voltage
(-0.004V/s to +0.004V/s) after the external power falls below the detection voltage (V DLX)*1.
Write/Erase cycles and data hold time
Write/Erase cycles
(cycle)
Data hold time
(year)
1,000
10,000
100,000
20 *2
10 *2
5 *2
*1: See "7. Low Voltage Detection Function Characteristics".
*2: This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85C).
January 31, 2014, MB96680_DS704-00002-2v1-E
CONFIDENTIAL
61
D a t a S h e e t
 EXAMPLE CHARACTERISTICS
This characteristic is an actual value of the arbitrary sample. It is not the guaranteed value.
 MB96F685
Run Mode
(VCC = 5.5V)
100.00
PLL clock (32MHz)
10.00
ICC [mA]
Main osc. (4MHz)
1.00
RC clock (2MHz)
RC clock (100kHz)
0.10
Sub osc. (32kHz)
0.01
-50
0
50
100
150
TA [ºC]
Sleep Mode
100.000
PLL clock (32MHz)
10.000
ICC [mA]
(VCC = 5.5V)
Main osc. (4MHz)
1.000
RC clock (2MHz)
0.100
RC clock (100kHz)
0.010
Sub osc. (32kHz)
0.001
-50
0
50
100
150
TA [ºC]
62
CONFIDENTIAL
MB96680_DS704-00002-2v1-E, January 31, 2014
D a t a S h e e t
 MB96F685
Timer Mode
(VCC = 5.5V)
10.000
PLL clock (32MHz)
1.000
ICC [mA]
Main osc. (4MHz)
0.100
RC clock (2MHz)
RC clock (100kHz)
0.010
Sub osc. (32kHz)
0.001
-50
0
50
100
150
TA [ºC]
Stop Mode
(VCC = 5.5V)
1.000
ICC [mA]
0.100
0.010
0.001
-50
0
50
100
150
TA [ºC]
January 31, 2014, MB96680_DS704-00002-2v1-E
CONFIDENTIAL
63
D a t a S h e e t
 Used setting
Mode
Run mode
Sleep mode
Selected Source
Clock
PLL
Main osc.
RC clock fast
RC clock slow
Sub osc.
PLL
Main osc.
RC clock fast
RC clock slow
Sub osc.
Timer mode
PLL
Main osc.
RC clock fast
RC clock slow
Sub osc.
Stop mode
64
CONFIDENTIAL
stopped
Clock/Regulator and FLASH Settings
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 32MHz
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 4MHz
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 2MHz
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 100kHz
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 32kHz
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 32MHz
Regulator in High Power Mode,
(CLKB is stopped in this mode)
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 4MHz
Regulator in High Power Mode,
(CLKB is stopped in this mode)
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 2MHz
Regulator in High Power Mode,
(CLKB is stopped in this mode)
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 100kHz
Regulator in Low Power Mode,
(CLKB is stopped in this mode)
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 32kHz
Regulator in Low Power Mode,
(CLKB is stopped in this mode)
CLKMC = 4MHz, CLKPLL = 32MHz
(System clocks are stopped in this mode)
Regulator in High Power Mode,
FLASH in Power-down / reset mode
CLKMC = 4MHz
(System clocks are stopped in this mode)
Regulator in High Power Mode,
FLASH in Power-down / reset mode
CLKMC = 2MHz
(System clocks are stopped in this mode)
Regulator in High Power Mode,
FLASH in Power-down / reset mode
CLKMC = 100kHz
(System clocks are stopped in this mode)
Regulator in Low Power Mode,
FLASH in Power-down / reset mode
CLKMC = 32 kHz
(System clocks are stopped in this mode)
Regulator in Low Power Mode,
FLASH in Power-down / reset mode
(All clocks are stopped in this mode)
Regulator in Low Power Mode,
FLASH in Power-down / reset mode
MB96680_DS704-00002-2v1-E, January 31, 2014
D a t a S h e e t
 ORDERING INFORMATION
MCU with CAN controller
Part number
Flash memory
MB96F683RBPMC-GSE1
Flash A
(96.5KB)
MB96F683RBPMC-GSE2
MB96F685RBPMC-GSE1
Flash A
(160.5KB)
MB96F685RBPMC-GSE2
*: For details about package, see "PACKAGE DIMENSION".
Package*
80-pin plastic LQFP
(FPT-80P-M21)
80-pin plastic LQFP
(FPT-80P-M21)
MCU without CAN controller
Part number
Flash memory
MB96F683ABPMC-GSE1
Flash A
(96.5KB)
MB96F683ABPMC-GSE2
MB96F685ABPMC-GSE1
Flash A
(160.5KB)
MB96F685ABPMC-GSE2
*: For details about package, see "PACKAGE DIMENSION".
January 31, 2014, MB96680_DS704-00002-2v1-E
CONFIDENTIAL
Package*
80-pin plastic LQFP
(FPT-80P-M21)
80-pin plastic LQFP
(FPT-80P-M21)
65
D a t a S h e e t
 PACKAGE DIMENSION
80-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
12 mm × 12 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm Max
Weight
0.47 g
Code
(Reference)
P-LFQFP80-12×12-0.50
(FPT-80P-M21)
80-pin plastic LQFP
(FPT-80P-M21)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00±0.20(.551±.008)SQ
* 12.00±0.10(.472±.004)SQ
60
0.145±0.055
(.006±.002)
41
61
40
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008 (Mounting height)
.059 –.004
INDEX
0°~8°
80
21
"A"
LEAD No.
1
20
0.50(.020)
C
0.10±0.05
(.004±.002)
(Stand off)
0.20±0.05
(.008±.002)
0.08(.003)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
M
2006-2010 FUJITSU SEMICONDUCTOR LIMITED F80035S-c-2-4
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
66
CONFIDENTIAL
MB96680_DS704-00002-2v1-E, January 31, 2014
D a t a S h e e t
 Major Changes
Page
Section
Change Results
Revision 2.0
40
Revision 2.1
-
ELECTRICAL CHARACTERISTICS
3. DC Characteristics
(1) Current Rating
-
January 31, 2014, MB96680_DS704-00002-2v1-E
CONFIDENTIAL
Changed the Value of “Power supply current in Timer modes”
ICCTPLL
Typ: 1880μA → 1800μA (TA = +25°C)
Company name and layout design change
67
D a t a S h e e t
68
CONFIDENTIAL
MB96680_DS704-00002-2v1-E, January 31, 2014
D a t a S h e e t
January 31, 2014, MB96680_DS704-00002-2v1-E
CONFIDENTIAL
69
D a t a S h e e t
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use
where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not
be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the
products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire
protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in
this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and
Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a
Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any
product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to
its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party
rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind
arising out of the use of the information in this document.
Copyright © 2013-2014 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit®
EclipseTM, ORNANDTM and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the
United States and other countries. Other names used are for informational purposes only and may be trademarks of their
respective owners.
70
CONFIDENTIAL
MB96680_DS704-00002-2v1-E, January 31, 2014