DISCRETE SEMICONDUCTORS DATA SHEET BF909WR N-channel dual-gate MOS-FET Product specification Supersedes data of 1997 Sep 05 2010 Sep 15 NXP Semiconductors Product specification N-channel dual-gate MOS-FET BF909WR FEATURES PINNING Specially designed for use at 5 V supply voltage Short channel transistor with high forward transfer admittance to input capacitance ratio Low noise gain controlled amplifier up to 1 GHz Superior cross-modulation performance during AGC. PIN SYMBOL DESCRIPTION 1 s, b 2 d drain 3 g2 gate 2 4 g1 gate 1 source APPLICATIONS VHF and UHF applications with 3 to 7 V supply voltage such as television tuners and professional communications equipment. d handbook, halfpage 3 4 DESCRIPTION g 2 g1 Enhancement type field-effect transistor in a plastic microminiature SOT343R package. The transistor consists of an amplifier MOS-FET with source and substrate interconnected and an internal bias circuit to ensure good cross-modulation performance during AGC. 2 1 Top view Marking code: ME* CAUTION The device is supplied in an antistatic package. The gate-source input must be protected against static discharge during transport or handling. s,b MAM192 * = - : made in Hong Kong * = p : made in Hong Kong * = t : made in Malaysia Fig.1 Simplified outline (SOT343R) and symbol. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDS drain-source voltage 7 V ID drain current 40 mA Ptot total power dissipation 280 mW Tj operating junction temperature 150 C yfs forward transfer admittance 36 43 50 mS Cig1-s input capacitance at gate 1 3.6 4.3 pF Crs reverse transfer capacitance f = 1 MHz 30 50 fF F noise figure f = 800 MHz 2 2.8 dB 2010 Sep 15 2 NXP Semiconductors Product specification N-channel dual-gate MOS-FET BF909WR LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS drain-source voltage 7 V ID drain current 40 mA IG1 gate 1 current 10 mA IG2 gate 2 current 10 mA Ptot total power dissipation 280 mW Tstg storage temperature range 65 +150 C Tj operating junction temperature +150 C up to Tamb = 50 C; see Fig.2; note 1 Note 1. Device mounted on a printed-circuit board. MLD150 300 handbook, halfpage Ptot (mW) 200 100 0 0 50 100 150 200 Tamb ( oC) Fig.2 Power derating curve. 2010 Sep 15 3 NXP Semiconductors Product specification N-channel dual-gate MOS-FET BF909WR THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS VALUE UNIT Rth j-a thermal resistance from junction to ambient note 1 350 K/W Rth j-s thermal resistance from junction to soldering point Ts = 91 C; note 2 210 K/W Notes 1. Device mounted on a printed-circuit board. 2. Ts is the temperature at the soldering point of the source lead. STATIC CHARACTERISTICS Tj = 25 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS V(BR)G1-SS gate 1-source breakdown voltage V(BR)G2-SS V(F)S-G1 MIN. MAX. UNIT VG2-S = VDS = 0; IG1-S = 10 mA 6 15 V gate 2-source breakdown voltage VG1-S = VDS = 0; IG2-S = 10 mA 6 15 V forward source-gate 1 voltage VG2-S = VDS = 0; IS-G1 = 10 mA 0.5 1.5 V V(F)S-G2 forward source-gate 2 voltage VG1-S = VDS = 0; IS-G2 = 10 mA 0.5 1.5 V VG1-S(th) gate 1-source threshold voltage VG2-S = 4 V; VDS = 5 V; ID = 20 A 0.3 1 V VG2-S(th) gate 2-source threshold voltage VG1-S = VDS = 5 V; ID = 20 A 0.3 1.2 V IDSX drain-source current VG2-S = 4 V; VDS = 5 V; RG1 = 120 k; note 1 12 20 mA IG1-SS gate 1 cut-off current VG2-S = VDS = 0; VG1-S = 5 V 50 nA IG2-SS gate 2 cut-off current VG1-S = VDS = 0; VG2-S = 5 V 50 nA Note 1. RG1 connects gate 1 to VGG = 5 V. DYNAMIC CHARACTERISTICS Common source; Tamb = 25 C; VDS = 5 V; VG2-S = 4 V; ID = 15 mA; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. yfs forward transfer admittance pulsed; Tj = 25 C 36 43 MAX. 50 UNIT mS Cig1-s input capacitance at gate 1 f = 1 MHz 3.6 4.3 pF Cig2-s input capacitance at gate 2 f = 1 MHz 2.3 3 pF Cos drain-source capacitance f = 1 MHz 2.3 3 pF Crs reverse transfer capacitance f = 1 MHz 30 50 fF F noise figure 2 2.8 dB 2010 Sep 15 f = 800 MHz; GS = GSopt; BS = BSopt 4 NXP Semiconductors Product specification N-channel dual-gate MOS-FET BF909WR MLB937 30 MLB936 handbook, halfpage 110 handbook, halfpage V G2 S = 4 V 3 V ID Vunw (dBμV) 2.5 V (mA) 2V 20 100 1.5 V 10 90 1V 80 0 0 10 20 30 40 50 gain reduction (dB) 0 0.4 0.8 1.2 1.6 2.0 V G1 S (V) VDS = 5 V; VGG = 5 V; fw = 50 MHz. funw = 60 MHz; Tamb = 25 C; RG1 = 120 k. Fig.3 VDS = 5 V. Tj = 25 C. Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; see Fig.17. Fig.4 Transfer characteristics; typical values. MLB938 30 handbook, halfpage I G1 (μA) ID (mA) 1.3 V 20 MLB939 200 handbook, halfpage V G1 S = 1.4 V V G2 S = 4 V 150 3.5 V 1.2 V 3V 100 1.1 V 2.5 V 1.0 V 10 50 0.9 V 0 0 2 4 6 8 2V 0 10 V DS (V) 0 VDS = 5 V. VG2-S = 4 V. Tj = 25 C. 2 V G1 S (V) 3 VDS = 5 V. Tj = 25 C. Fig.6 Fig.5 Output characteristics; typical values. 2010 Sep 15 1 5 Gate 1 current as a function of gate 1 voltage; typical values. NXP Semiconductors Product specification N-channel dual-gate MOS-FET BF909WR MLB941 MLB940 25 60 handbook, halfpage handbook, halfpage ID (mA) 20 V G2 S = 4 V y fs (mS) 3.5 V 3V 40 15 2.5 V 10 20 5 2V 0 0 0 10 20 I D (mA) 0 30 40 I G1 (μA) 60 VDS = 5 V. VG2-S = 4 V. Tj = 25 C. VDS = 5 V. Tj = 25 C. Fig.7 20 Forward transfer admittance as a function of drain current; typical values. Fig.8 Drain current as a function of gate 1 current; typical values. MLB942 16 MLB943 30 handbook, halfpage handbook, halfpage ID (mA) R G1 = 47 kΩ ID (mA) 68 kΩ 82 kΩ 12 100 kΩ 20 120 kΩ 150 kΩ 8 180 kΩ 220 kΩ 10 4 0 0 0 2 4 V GG (V) 6 0 VDS = 5 V; VG2-S = 4 V. 2010 Sep 15 4 6 V GG = V DS (V) 8 VG2-S = 4 V. RG1 connected to VGG; Tj = 25 C. RG1 = 120 k (connected to VGG); Tj = 25 C. Fig.9 2 Drain current as a function of gate 1 supply voltage (= VGG); typical values; see Fig.17. Fig.10 Drain current as a function of gate 1 (= VGG) and drain supply voltage; typical values; see Fig.17. 6 NXP Semiconductors Product specification N-channel dual-gate MOS-FET BF909WR MLB944 MLB945 40 20 handbook, halfpage handbook, halfpage ID (mA) 16 V GG = 5 V I G1 (μA) 4.5 V V GG = 5 V 30 4V 4.5 V 3.5 V 12 4V 3V 3.5 V 20 3V 8 10 4 0 0 0 2 4 V G2 S (V) 0 6 VDS = 5 V; Tj = 25 C. RG1 = 120 k (connected to VGG). 2 4 V G2 S (V) 6 VDS = 5 V; Tj = 25 C. RG1 = 120 k (connected to VGG). Fig.11 Drain current as a function of gate 2 voltage; typical values; see Fig.17. Fig.12 Gate 1 current as a function of gate 2 voltage; typical values; see Fig.17. MLB946 10 2 handbook, halfpage MLB947 10 3 y is (mS) ϕ rs (deg) y rs (μS) ϕ rs 10 2 10 10 3 10 2 b is y rs 1 10 10 g is 10 1 10 102 f (MHz) 10 VDS = 5 V; VG2 = 4 V. ID = 15 mA; Tamb = 25 C. 102 f (MHz) 10 3 VDS = 5 V; VG2 = 4 V. ID = 15 mA; Tamb = 25 C. Fig.13 Input admittance as a function of frequency; typical values. 2010 Sep 15 1 1 10 3 Fig.14 Reverse transfer admittance and phase as a function of frequency; typical values. 7 NXP Semiconductors Product specification N-channel dual-gate MOS-FET MLB948 10 2 BF909WR y fs y fs MLB949 10 2 10 handbook, halfpage yos (mS) ϕ fs bos (deg) (mS) 1 ϕfs 10 10 gos 10 1 10 2 10 1 1 10 102 10 3 f (MHz) VDS = 5 V; VG2 = 4 V. ID = 15 mA; Tamb = 25 C. 102 10 3 VDS = 5 V; VG2 = 4 V. ID = 15 mA; Tamb = 25 C. Fig.15 Forward transfer admittance and phase as a function of frequency; typical values. Fig.16 Output admittance as a function of frequency; typical values. VAGC R1 10 k Ω C1 4.7 nF R GEN 50 Ω R2 50 Ω C3 R3 10 Ω C2 DUT 4.7 nF C5 2.2 pF R G1 12 pF L1 ≈ 350 nH RL 50 Ω C4 4.7 nF VI VGG VDS Fig.17 Cross-modulation test set-up. 2010 Sep 15 f (MHz) 8 MLD151 NXP Semiconductors Product specification N-channel dual-gate MOS-FET Table 1 f (MHz) BF909WR Scattering parameters: VDS = 5 V; VG2-S = 4 V; ID = 15 mA; Tamb = 25 C s11 s21 s12 s22 MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) 50 0.985 6.4 4.064 172.3 0.001 86.9 0.985 3.2 100 0.978 12.6 3.997 164.9 0.002 82.7 0.982 6.4 200 0.957 25.0 3.886 150.8 0.005 74.3 0.973 12.6 300 0.931 36.5 3.682 137.3 0.006 68.9 0.960 18.6 400 0.899 47.6 3.484 123.8 0.007 59.6 0.947 24.2 500 0.868 57.4 3.260 111.7 0.007 57.9 0.936 29.6 600 0.848 66.6 3.053 101.0 0.006 58.5 0.927 34.8 700 0.816 74.6 2.829 90.3 0.005 65.5 0.919 39.8 800 0.792 82.2 2.652 79.9 0.005 83.3 0.913 44.6 900 0.772 89.3 2.470 69.5 0.005 114.9 0.910 49.5 1000 0.754 95.6 2.328 59.5 0.006 138.7 0.909 54.6 Table 2 Noise data: VDS = 5 V; VG2-S = 4 V; ID = 15 mA; Tamb = 25 C opt f (MHz) Fmin (dB) (ratio) (deg) 800 2.00 0.603 67.71 2010 Sep 15 9 rn 0.581 NXP Semiconductors Product specification N-channel dual-gate MOS-FET BF909WR PACKAGE OUTLINE Plastic surface-mounted package; reverse pinning; 4 leads D SOT343R E B A X HE y v M A e 3 4 Q A A1 c 2 w M B 1 bp Lp b1 e1 detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp b1 c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.4 0.3 0.7 0.5 0.25 0.10 2.2 1.8 1.35 1.15 1.3 1.15 2.2 2.0 0.45 0.15 0.23 0.13 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 97-05-21 06-03-16 SOT343R 2010 Sep 15 EUROPEAN PROJECTION 10 NXP Semiconductors Product specification N-channel dual-gate MOS-FET BF909WR DATA SHEET STATUS DOCUMENT STATUS(1) PRODUCT STATUS(2) DEFINITION Objective data sheet Development This document contains data from the objective specification for product development. Preliminary data sheet Qualification This document contains data from the preliminary specification. Product data sheet Production This document contains the product specification. Notes 1. Please consult the most recently issued document before initiating or completing a design. 2. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. DISCLAIMERS property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 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NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe 2010 Sep 15 11 NXP Semiconductors Product specification N-channel dual-gate MOS-FET BF909WR Limiting values Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. 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Contact information For additional information please visit: http://www.nxp.com For sales offices addresses send e-mail to: [email protected] © NXP B.V. 2010 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R77/03/pp13 Date of release: 2010 Sep 15